proj.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 00000190 08000000 08000000 00010000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00001ef0 08000190 08000190 00010190 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000048 08002080 08002080 00012080 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 080020c8 080020c8 00020430 2**0 CONTENTS 4 .ARM 00000000 080020c8 080020c8 00020430 2**0 CONTENTS 5 .preinit_array 00000000 080020c8 080020c8 00020430 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000008 080020c8 080020c8 000120c8 2**2 CONTENTS, ALLOC, LOAD, DATA 7 .fini_array 00000008 080020d0 080020d0 000120d0 2**2 CONTENTS, ALLOC, LOAD, DATA 8 .data 00000430 20000000 080020d8 00020000 2**3 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000020 20000430 08002508 00020430 2**2 ALLOC 10 ._user_heap_stack 00000600 20000450 08002508 00020450 2**0 ALLOC 11 .ARM.attributes 00000030 00000000 00000000 00020430 2**0 CONTENTS, READONLY 12 .comment 00000070 00000000 00000000 00020460 2**0 CONTENTS, READONLY 13 .debug_line 00002999 00000000 00000000 000204d0 2**0 CONTENTS, READONLY, DEBUGGING 14 .debug_info 00007bf1 00000000 00000000 00022e69 2**0 CONTENTS, READONLY, DEBUGGING 15 .debug_abbrev 00001920 00000000 00000000 0002aa5a 2**0 CONTENTS, READONLY, DEBUGGING 16 .debug_aranges 00000678 00000000 00000000 0002c380 2**3 CONTENTS, READONLY, DEBUGGING 17 .debug_ranges 00000580 00000000 00000000 0002c9f8 2**3 CONTENTS, READONLY, DEBUGGING 18 .debug_str 00002654 00000000 00000000 0002cf78 2**0 CONTENTS, READONLY, DEBUGGING 19 .debug_frame 000015b0 00000000 00000000 0002f5cc 2**2 CONTENTS, READONLY, DEBUGGING 20 .debug_loc 00000413 00000000 00000000 00030b7c 2**0 CONTENTS, READONLY, DEBUGGING Disassembly of section .text: 08000190 : 8000190: 4b04 ldr r3, [pc, #16] ; (80001a4 ) 8000192: 4805 ldr r0, [pc, #20] ; (80001a8 ) 8000194: 1a1b subs r3, r3, r0 8000196: 2b06 cmp r3, #6 8000198: d902 bls.n 80001a0 800019a: 4b04 ldr r3, [pc, #16] ; (80001ac ) 800019c: b103 cbz r3, 80001a0 800019e: 4718 bx r3 80001a0: 4770 bx lr 80001a2: bf00 nop 80001a4: 20000433 .word 0x20000433 80001a8: 20000430 .word 0x20000430 80001ac: 00000000 .word 0x00000000 080001b0 : 80001b0: 4905 ldr r1, [pc, #20] ; (80001c8 ) 80001b2: 4806 ldr r0, [pc, #24] ; (80001cc ) 80001b4: 1a09 subs r1, r1, r0 80001b6: 1089 asrs r1, r1, #2 80001b8: eb01 71d1 add.w r1, r1, r1, lsr #31 80001bc: 1049 asrs r1, r1, #1 80001be: d002 beq.n 80001c6 80001c0: 4b03 ldr r3, [pc, #12] ; (80001d0 ) 80001c2: b103 cbz r3, 80001c6 80001c4: 4718 bx r3 80001c6: 4770 bx lr 80001c8: 20000430 .word 0x20000430 80001cc: 20000430 .word 0x20000430 80001d0: 00000000 .word 0x00000000 080001d4 <__do_global_dtors_aux>: 80001d4: b510 push {r4, lr} 80001d6: 4c06 ldr r4, [pc, #24] ; (80001f0 <__do_global_dtors_aux+0x1c>) 80001d8: 7823 ldrb r3, [r4, #0] 80001da: b943 cbnz r3, 80001ee <__do_global_dtors_aux+0x1a> 80001dc: f7ff ffd8 bl 8000190 80001e0: 4b04 ldr r3, [pc, #16] ; (80001f4 <__do_global_dtors_aux+0x20>) 80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x16> 80001e4: 4804 ldr r0, [pc, #16] ; (80001f8 <__do_global_dtors_aux+0x24>) 80001e6: f3af 8000 nop.w 80001ea: 2301 movs r3, #1 80001ec: 7023 strb r3, [r4, #0] 80001ee: bd10 pop {r4, pc} 80001f0: 20000430 .word 0x20000430 80001f4: 00000000 .word 0x00000000 80001f8: 08002064 .word 0x08002064 080001fc : 80001fc: b508 push {r3, lr} 80001fe: 4b08 ldr r3, [pc, #32] ; (8000220 ) 8000200: b11b cbz r3, 800020a 8000202: 4808 ldr r0, [pc, #32] ; (8000224 ) 8000204: 4908 ldr r1, [pc, #32] ; (8000228 ) 8000206: f3af 8000 nop.w 800020a: 4808 ldr r0, [pc, #32] ; (800022c ) 800020c: 6803 ldr r3, [r0, #0] 800020e: b913 cbnz r3, 8000216 8000210: e8bd 4008 ldmia.w sp!, {r3, lr} 8000214: e7cc b.n 80001b0 8000216: 4b06 ldr r3, [pc, #24] ; (8000230 ) 8000218: 2b00 cmp r3, #0 800021a: d0f9 beq.n 8000210 800021c: 4798 blx r3 800021e: e7f7 b.n 8000210 8000220: 00000000 .word 0x00000000 8000224: 08002064 .word 0x08002064 8000228: 20000434 .word 0x20000434 800022c: 20000430 .word 0x20000430 8000230: 00000000 .word 0x00000000 08000234 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Atollic update: set stack pointer */ 8000234: f8df d034 ldr.w sp, [pc, #52] ; 800026c /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8000238: 2100 movs r1, #0 b LoopCopyDataInit 800023a: e003 b.n 8000244 0800023c : CopyDataInit: ldr r3, =_sidata 800023c: 4b0c ldr r3, [pc, #48] ; (8000270 ) ldr r3, [r3, r1] 800023e: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8000240: 5043 str r3, [r0, r1] adds r1, r1, #4 8000242: 3104 adds r1, #4 08000244 : LoopCopyDataInit: ldr r0, =_sdata 8000244: 480b ldr r0, [pc, #44] ; (8000274 ) ldr r3, =_edata 8000246: 4b0c ldr r3, [pc, #48] ; (8000278 ) adds r2, r0, r1 8000248: 1842 adds r2, r0, r1 cmp r2, r3 800024a: 429a cmp r2, r3 bcc CopyDataInit 800024c: d3f6 bcc.n 800023c ldr r2, =_sbss 800024e: 4a0b ldr r2, [pc, #44] ; (800027c ) b LoopFillZerobss 8000250: e002 b.n 8000258 08000252 : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 8000252: 2300 movs r3, #0 str r3, [r2], #4 8000254: f842 3b04 str.w r3, [r2], #4 08000258 : LoopFillZerobss: ldr r3, = _ebss 8000258: 4b09 ldr r3, [pc, #36] ; (8000280 ) cmp r2, r3 800025a: 429a cmp r2, r3 bcc FillZerobss 800025c: d3f9 bcc.n 8000252 /* Call the clock system intitialization function.*/ bl SystemInit 800025e: f001 fe2d bl 8001ebc /* Call static constructors */ bl __libc_init_array 8000262: f001 fe7b bl 8001f5c <__libc_init_array> /* Call the application's entry point.*/ bl main 8000266: f001 fcd3 bl 8001c10
0800026a : LoopForever: b LoopForever 800026a: e7fe b.n 800026a .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr sp, =_estack /* Atollic update: set stack pointer */ 800026c: 2000c000 .word 0x2000c000 /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 b LoopCopyDataInit CopyDataInit: ldr r3, =_sidata 8000270: 080020d8 .word 0x080020d8 ldr r3, [r3, r1] str r3, [r0, r1] adds r1, r1, #4 LoopCopyDataInit: ldr r0, =_sdata 8000274: 20000000 .word 0x20000000 ldr r3, =_edata 8000278: 20000430 .word 0x20000430 adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit ldr r2, =_sbss 800027c: 20000430 .word 0x20000430 FillZerobss: movs r3, #0 str r3, [r2], #4 LoopFillZerobss: ldr r3, = _ebss 8000280: 20000450 .word 0x20000450 08000284 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8000284: e7fe b.n 8000284 ... 08000288 : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8000288: b580 push {r7, lr} 800028a: af00 add r7, sp, #0 #if (PREFETCH_ENABLE != 0) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Set Interrupt Group Priority */ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 800028c: 2003 movs r0, #3 800028e: f000 f8ef bl 8000470 /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ HAL_InitTick(TICK_INT_PRIORITY); 8000292: 2000 movs r0, #0 8000294: f000 f806 bl 80002a4 /* Init the low level hardware */ HAL_MspInit(); 8000298: f001 fd92 bl 8001dc0 /* Return function status */ return HAL_OK; 800029c: 2300 movs r3, #0 } 800029e: 4618 mov r0, r3 80002a0: bd80 pop {r7, pc} 80002a2: bf00 nop 080002a4 : * implementation in user file. * @param TickPriority: Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 80002a4: b580 push {r7, lr} 80002a6: b082 sub sp, #8 80002a8: af00 add r7, sp, #0 80002aa: 6078 str r0, [r7, #4] /*Configure the SysTick to have interrupt in 1ms time basis*/ HAL_SYSTICK_Config(SystemCoreClock/1000); 80002ac: 4b09 ldr r3, [pc, #36] ; (80002d4 ) 80002ae: 681b ldr r3, [r3, #0] 80002b0: 4a09 ldr r2, [pc, #36] ; (80002d8 ) 80002b2: fba2 2303 umull r2, r3, r2, r3 80002b6: 099b lsrs r3, r3, #6 80002b8: 4618 mov r0, r3 80002ba: f000 f8ff bl 80004bc /*Configure the SysTick IRQ priority */ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0); 80002be: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 80002c2: 6879 ldr r1, [r7, #4] 80002c4: 2200 movs r2, #0 80002c6: f000 f8dd bl 8000484 /* Return function status */ return HAL_OK; 80002ca: 2300 movs r3, #0 } 80002cc: 4618 mov r0, r3 80002ce: 3708 adds r7, #8 80002d0: 46bd mov sp, r7 80002d2: bd80 pop {r7, pc} 80002d4: 20000000 .word 0x20000000 80002d8: 10624dd3 .word 0x10624dd3 080002dc : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80002dc: b480 push {r7} 80002de: af00 add r7, sp, #0 uwTick++; 80002e0: 4b04 ldr r3, [pc, #16] ; (80002f4 ) 80002e2: 681b ldr r3, [r3, #0] 80002e4: 3301 adds r3, #1 80002e6: 4a03 ldr r2, [pc, #12] ; (80002f4 ) 80002e8: 6013 str r3, [r2, #0] } 80002ea: 46bd mov sp, r7 80002ec: f85d 7b04 ldr.w r7, [sp], #4 80002f0: 4770 bx lr 80002f2: bf00 nop 80002f4: 2000044c .word 0x2000044c 080002f8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80002f8: b480 push {r7} 80002fa: af00 add r7, sp, #0 return uwTick; 80002fc: 4b03 ldr r3, [pc, #12] ; (800030c ) 80002fe: 681b ldr r3, [r3, #0] } 8000300: 4618 mov r0, r3 8000302: 46bd mov sp, r7 8000304: f85d 7b04 ldr.w r7, [sp], #4 8000308: 4770 bx lr 800030a: bf00 nop 800030c: 2000044c .word 0x2000044c 08000310 : In case of a conflict between priority grouping and available priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. \param [in] PriorityGroup Priority grouping field. */ __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000310: b480 push {r7} 8000312: b085 sub sp, #20 8000314: af00 add r7, sp, #0 8000316: 6078 str r0, [r7, #4] uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 8000318: 687b ldr r3, [r7, #4] 800031a: f003 0307 and.w r3, r3, #7 800031e: 60fb str r3, [r7, #12] reg_value = SCB->AIRCR; /* read old register configuration */ 8000320: 4b0c ldr r3, [pc, #48] ; (8000354 ) 8000322: 68db ldr r3, [r3, #12] 8000324: 60bb str r3, [r7, #8] reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ 8000326: 68ba ldr r2, [r7, #8] 8000328: f64f 03ff movw r3, #63743 ; 0xf8ff 800032c: 4013 ands r3, r2 800032e: 60bb str r3, [r7, #8] reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ 8000330: 68fb ldr r3, [r7, #12] 8000332: 021a lsls r2, r3, #8 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000334: 68bb ldr r3, [r7, #8] 8000336: 4313 orrs r3, r2 uint32_t reg_value; uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ reg_value = SCB->AIRCR; /* read old register configuration */ reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ reg_value = (reg_value | 8000338: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 800033c: f443 3300 orr.w r3, r3, #131072 ; 0x20000 8000340: 60bb str r3, [r7, #8] ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ SCB->AIRCR = reg_value; 8000342: 4a04 ldr r2, [pc, #16] ; (8000354 ) 8000344: 68bb ldr r3, [r7, #8] 8000346: 60d3 str r3, [r2, #12] } 8000348: 3714 adds r7, #20 800034a: 46bd mov sp, r7 800034c: f85d 7b04 ldr.w r7, [sp], #4 8000350: 4770 bx lr 8000352: bf00 nop 8000354: e000ed00 .word 0xe000ed00 08000358 : \brief Get Priority Grouping \details Reads the priority grouping field from the NVIC Interrupt Controller. \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). */ __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) { 8000358: b480 push {r7} 800035a: af00 add r7, sp, #0 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); 800035c: 4b04 ldr r3, [pc, #16] ; (8000370 ) 800035e: 68db ldr r3, [r3, #12] 8000360: f403 63e0 and.w r3, r3, #1792 ; 0x700 8000364: 0a1b lsrs r3, r3, #8 } 8000366: 4618 mov r0, r3 8000368: 46bd mov sp, r7 800036a: f85d 7b04 ldr.w r7, [sp], #4 800036e: 4770 bx lr 8000370: e000ed00 .word 0xe000ed00 08000374 : \note The priority cannot be set for every core interrupt. \param [in] IRQn Interrupt number. \param [in] priority Priority to set. */ __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) { 8000374: b480 push {r7} 8000376: b083 sub sp, #12 8000378: af00 add r7, sp, #0 800037a: 4603 mov r3, r0 800037c: 6039 str r1, [r7, #0] 800037e: 71fb strb r3, [r7, #7] if ((int32_t)(IRQn) < 0) 8000380: f997 3007 ldrsb.w r3, [r7, #7] 8000384: 2b00 cmp r3, #0 8000386: da0b bge.n 80003a0 { SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 8000388: 490d ldr r1, [pc, #52] ; (80003c0 ) 800038a: 79fb ldrb r3, [r7, #7] 800038c: f003 030f and.w r3, r3, #15 8000390: 3b04 subs r3, #4 8000392: 683a ldr r2, [r7, #0] 8000394: b2d2 uxtb r2, r2 8000396: 0112 lsls r2, r2, #4 8000398: b2d2 uxtb r2, r2 800039a: 440b add r3, r1 800039c: 761a strb r2, [r3, #24] 800039e: e009 b.n 80003b4 } else { NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); 80003a0: 4908 ldr r1, [pc, #32] ; (80003c4 ) 80003a2: f997 3007 ldrsb.w r3, [r7, #7] 80003a6: 683a ldr r2, [r7, #0] 80003a8: b2d2 uxtb r2, r2 80003aa: 0112 lsls r2, r2, #4 80003ac: b2d2 uxtb r2, r2 80003ae: 440b add r3, r1 80003b0: f883 2300 strb.w r2, [r3, #768] ; 0x300 } } 80003b4: 370c adds r7, #12 80003b6: 46bd mov sp, r7 80003b8: f85d 7b04 ldr.w r7, [sp], #4 80003bc: 4770 bx lr 80003be: bf00 nop 80003c0: e000ed00 .word 0xe000ed00 80003c4: e000e100 .word 0xe000e100 080003c8 : \param [in] PreemptPriority Preemptive priority value (starting from 0). \param [in] SubPriority Subpriority value (starting from 0). \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). */ __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) { 80003c8: b480 push {r7} 80003ca: b089 sub sp, #36 ; 0x24 80003cc: af00 add r7, sp, #0 80003ce: 60f8 str r0, [r7, #12] 80003d0: 60b9 str r1, [r7, #8] 80003d2: 607a str r2, [r7, #4] uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ 80003d4: 68fb ldr r3, [r7, #12] 80003d6: f003 0307 and.w r3, r3, #7 80003da: 61fb str r3, [r7, #28] uint32_t PreemptPriorityBits; uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); 80003dc: 69fb ldr r3, [r7, #28] 80003de: f1c3 0307 rsb r3, r3, #7 80003e2: 2b04 cmp r3, #4 80003e4: bf28 it cs 80003e6: 2304 movcs r3, #4 80003e8: 61bb str r3, [r7, #24] SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); 80003ea: 69fb ldr r3, [r7, #28] 80003ec: 3304 adds r3, #4 80003ee: 2b06 cmp r3, #6 80003f0: d902 bls.n 80003f8 80003f2: 69fb ldr r3, [r7, #28] 80003f4: 3b03 subs r3, #3 80003f6: e000 b.n 80003fa 80003f8: 2300 movs r3, #0 80003fa: 617b str r3, [r7, #20] return ( ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | 80003fc: 69bb ldr r3, [r7, #24] 80003fe: 2201 movs r2, #1 8000400: fa02 f303 lsl.w r3, r2, r3 8000404: 1e5a subs r2, r3, #1 8000406: 68bb ldr r3, [r7, #8] 8000408: 401a ands r2, r3 800040a: 697b ldr r3, [r7, #20] 800040c: 409a lsls r2, r3 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) 800040e: 697b ldr r3, [r7, #20] 8000410: 2101 movs r1, #1 8000412: fa01 f303 lsl.w r3, r1, r3 8000416: 1e59 subs r1, r3, #1 8000418: 687b ldr r3, [r7, #4] 800041a: 400b ands r3, r1 uint32_t SubPriorityBits; PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); return ( 800041c: 4313 orrs r3, r2 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) ); } 800041e: 4618 mov r0, r3 8000420: 3724 adds r7, #36 ; 0x24 8000422: 46bd mov sp, r7 8000424: f85d 7b04 ldr.w r7, [sp], #4 8000428: 4770 bx lr 800042a: bf00 nop 0800042c : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 800042c: b580 push {r7, lr} 800042e: b082 sub sp, #8 8000430: af00 add r7, sp, #0 8000432: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8000434: 687b ldr r3, [r7, #4] 8000436: 3b01 subs r3, #1 8000438: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 800043c: d301 bcc.n 8000442 { return (1UL); /* Reload value impossible */ 800043e: 2301 movs r3, #1 8000440: e00f b.n 8000462 } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8000442: 4a0a ldr r2, [pc, #40] ; (800046c ) 8000444: 687b ldr r3, [r7, #4] 8000446: 3b01 subs r3, #1 8000448: 6053 str r3, [r2, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 800044a: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 800044e: 210f movs r1, #15 8000450: f7ff ff90 bl 8000374 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 8000454: 4b05 ldr r3, [pc, #20] ; (800046c ) 8000456: 2200 movs r2, #0 8000458: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 800045a: 4b04 ldr r3, [pc, #16] ; (800046c ) 800045c: 2207 movs r2, #7 800045e: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 8000460: 2300 movs r3, #0 } 8000462: 4618 mov r0, r3 8000464: 3708 adds r7, #8 8000466: 46bd mov sp, r7 8000468: bd80 pop {r7, pc} 800046a: bf00 nop 800046c: e000e010 .word 0xe000e010 08000470 : * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. * The pending IRQ priority will be managed only by the subpriority. * @retval None */ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) { 8000470: b580 push {r7, lr} 8000472: b082 sub sp, #8 8000474: af00 add r7, sp, #0 8000476: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ NVIC_SetPriorityGrouping(PriorityGroup); 8000478: 6878 ldr r0, [r7, #4] 800047a: f7ff ff49 bl 8000310 } 800047e: 3708 adds r7, #8 8000480: 46bd mov sp, r7 8000482: bd80 pop {r7, pc} 08000484 : * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 8000484: b580 push {r7, lr} 8000486: b086 sub sp, #24 8000488: af00 add r7, sp, #0 800048a: 4603 mov r3, r0 800048c: 60b9 str r1, [r7, #8] 800048e: 607a str r2, [r7, #4] 8000490: 73fb strb r3, [r7, #15] uint32_t prioritygroup = 0x00; 8000492: 2300 movs r3, #0 8000494: 617b str r3, [r7, #20] /* Check the parameters */ assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); prioritygroup = NVIC_GetPriorityGrouping(); 8000496: f7ff ff5f bl 8000358 800049a: 6178 str r0, [r7, #20] NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 800049c: 6978 ldr r0, [r7, #20] 800049e: 68b9 ldr r1, [r7, #8] 80004a0: 687a ldr r2, [r7, #4] 80004a2: f7ff ff91 bl 80003c8 80004a6: 4602 mov r2, r0 80004a8: f997 300f ldrsb.w r3, [r7, #15] 80004ac: 4618 mov r0, r3 80004ae: 4611 mov r1, r2 80004b0: f7ff ff60 bl 8000374 } 80004b4: 3718 adds r7, #24 80004b6: 46bd mov sp, r7 80004b8: bd80 pop {r7, pc} 80004ba: bf00 nop 080004bc : * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 80004bc: b580 push {r7, lr} 80004be: b082 sub sp, #8 80004c0: af00 add r7, sp, #0 80004c2: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 80004c4: 6878 ldr r0, [r7, #4] 80004c6: f7ff ffb1 bl 800042c 80004ca: 4603 mov r3, r0 } 80004cc: 4618 mov r0, r3 80004ce: 3708 adds r7, #8 80004d0: 46bd mov sp, r7 80004d2: bd80 pop {r7, pc} 080004d4 : * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. * @retval None */ void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) { 80004d4: b480 push {r7} 80004d6: b083 sub sp, #12 80004d8: af00 add r7, sp, #0 80004da: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); if (CLKSource == SYSTICK_CLKSOURCE_HCLK) 80004dc: 687b ldr r3, [r7, #4] 80004de: 2b04 cmp r3, #4 80004e0: d106 bne.n 80004f0 { SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; 80004e2: 4a09 ldr r2, [pc, #36] ; (8000508 ) 80004e4: 4b08 ldr r3, [pc, #32] ; (8000508 ) 80004e6: 681b ldr r3, [r3, #0] 80004e8: f043 0304 orr.w r3, r3, #4 80004ec: 6013 str r3, [r2, #0] 80004ee: e005 b.n 80004fc } else { SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; 80004f0: 4a05 ldr r2, [pc, #20] ; (8000508 ) 80004f2: 4b05 ldr r3, [pc, #20] ; (8000508 ) 80004f4: 681b ldr r3, [r3, #0] 80004f6: f023 0304 bic.w r3, r3, #4 80004fa: 6013 str r3, [r2, #0] } } 80004fc: 370c adds r7, #12 80004fe: 46bd mov sp, r7 8000500: f85d 7b04 ldr.w r7, [sp], #4 8000504: 4770 bx lr 8000506: bf00 nop 8000508: e000e010 .word 0xe000e010 0800050c : /** * @brief Handle SYSTICK interrupt request. * @retval None */ void HAL_SYSTICK_IRQHandler(void) { 800050c: b580 push {r7, lr} 800050e: af00 add r7, sp, #0 HAL_SYSTICK_Callback(); 8000510: f000 f802 bl 8000518 } 8000514: bd80 pop {r7, pc} 8000516: bf00 nop 08000518 : /** * @brief SYSTICK callback. * @retval None */ __weak void HAL_SYSTICK_Callback(void) { 8000518: b480 push {r7} 800051a: af00 add r7, sp, #0 /* NOTE : This function should not be modified, when the callback is needed, the HAL_SYSTICK_Callback could be implemented in the user file */ } 800051c: 46bd mov sp, r7 800051e: f85d 7b04 ldr.w r7, [sp], #4 8000522: 4770 bx lr 08000524 : * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) { 8000524: b480 push {r7} 8000526: b087 sub sp, #28 8000528: af00 add r7, sp, #0 800052a: 6078 str r0, [r7, #4] 800052c: 6039 str r1, [r7, #0] uint32_t position = 0x00; 800052e: 2300 movs r3, #0 8000530: 617b str r3, [r7, #20] uint32_t iocurrent = 0x00; 8000532: 2300 movs r3, #0 8000534: 60fb str r3, [r7, #12] uint32_t temp = 0x00; 8000536: 2300 movs r3, #0 8000538: 613b str r3, [r7, #16] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != RESET) 800053a: e144 b.n 80007c6 { /* Get current io position */ iocurrent = (GPIO_Init->Pin) & (1U << position); 800053c: 683b ldr r3, [r7, #0] 800053e: 681a ldr r2, [r3, #0] 8000540: 697b ldr r3, [r7, #20] 8000542: 2101 movs r1, #1 8000544: fa01 f303 lsl.w r3, r1, r3 8000548: 4013 ands r3, r2 800054a: 60fb str r3, [r7, #12] if(iocurrent) 800054c: 68fb ldr r3, [r7, #12] 800054e: 2b00 cmp r3, #0 8000550: f000 8136 beq.w 80007c0 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 8000554: 683b ldr r3, [r7, #0] 8000556: 685b ldr r3, [r3, #4] 8000558: 2b02 cmp r3, #2 800055a: d003 beq.n 8000564 800055c: 683b ldr r3, [r7, #0] 800055e: 685b ldr r3, [r3, #4] 8000560: 2b12 cmp r3, #18 8000562: d122 bne.n 80005aa /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ temp = GPIOx->AFR[position >> 3]; 8000564: 697b ldr r3, [r7, #20] 8000566: 08da lsrs r2, r3, #3 8000568: 687b ldr r3, [r7, #4] 800056a: 3208 adds r2, #8 800056c: f853 3022 ldr.w r3, [r3, r2, lsl #2] 8000570: 613b str r3, [r7, #16] temp &= ~((uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ; 8000572: 697b ldr r3, [r7, #20] 8000574: f003 0307 and.w r3, r3, #7 8000578: 009b lsls r3, r3, #2 800057a: 461a mov r2, r3 800057c: 230f movs r3, #15 800057e: 4093 lsls r3, r2 8000580: 43db mvns r3, r3 8000582: 693a ldr r2, [r7, #16] 8000584: 4013 ands r3, r2 8000586: 613b str r3, [r7, #16] temp |= ((uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4)); 8000588: 683b ldr r3, [r7, #0] 800058a: 691b ldr r3, [r3, #16] 800058c: 697a ldr r2, [r7, #20] 800058e: f002 0207 and.w r2, r2, #7 8000592: 0092 lsls r2, r2, #2 8000594: 4093 lsls r3, r2 8000596: 693a ldr r2, [r7, #16] 8000598: 4313 orrs r3, r2 800059a: 613b str r3, [r7, #16] GPIOx->AFR[position >> 3] = temp; 800059c: 697b ldr r3, [r7, #20] 800059e: 08da lsrs r2, r3, #3 80005a0: 687b ldr r3, [r7, #4] 80005a2: 3208 adds r2, #8 80005a4: 6939 ldr r1, [r7, #16] 80005a6: f843 1022 str.w r1, [r3, r2, lsl #2] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ temp = GPIOx->MODER; 80005aa: 687b ldr r3, [r7, #4] 80005ac: 681b ldr r3, [r3, #0] 80005ae: 613b str r3, [r7, #16] temp &= ~(GPIO_MODER_MODE0 << (position * 2)); 80005b0: 697b ldr r3, [r7, #20] 80005b2: 005b lsls r3, r3, #1 80005b4: 461a mov r2, r3 80005b6: 2303 movs r3, #3 80005b8: 4093 lsls r3, r2 80005ba: 43db mvns r3, r3 80005bc: 693a ldr r2, [r7, #16] 80005be: 4013 ands r3, r2 80005c0: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); 80005c2: 683b ldr r3, [r7, #0] 80005c4: 685b ldr r3, [r3, #4] 80005c6: f003 0303 and.w r3, r3, #3 80005ca: 697a ldr r2, [r7, #20] 80005cc: 0052 lsls r2, r2, #1 80005ce: 4093 lsls r3, r2 80005d0: 693a ldr r2, [r7, #16] 80005d2: 4313 orrs r3, r2 80005d4: 613b str r3, [r7, #16] GPIOx->MODER = temp; 80005d6: 687b ldr r3, [r7, #4] 80005d8: 693a ldr r2, [r7, #16] 80005da: 601a str r2, [r3, #0] /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 80005dc: 683b ldr r3, [r7, #0] 80005de: 685b ldr r3, [r3, #4] 80005e0: 2b01 cmp r3, #1 80005e2: d00b beq.n 80005fc 80005e4: 683b ldr r3, [r7, #0] 80005e6: 685b ldr r3, [r3, #4] 80005e8: 2b02 cmp r3, #2 80005ea: d007 beq.n 80005fc (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 80005ec: 683b ldr r3, [r7, #0] 80005ee: 685b ldr r3, [r3, #4] temp &= ~(GPIO_MODER_MODE0 << (position * 2)); temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2)); GPIOx->MODER = temp; /* In case of Output or Alternate function mode selection */ if((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) || 80005f0: 2b11 cmp r3, #17 80005f2: d003 beq.n 80005fc (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 80005f4: 683b ldr r3, [r7, #0] 80005f6: 685b ldr r3, [r3, #4] 80005f8: 2b12 cmp r3, #18 80005fa: d12f bne.n 800065c { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); /* Configure the IO Speed */ temp = GPIOx->OSPEEDR; 80005fc: 687b ldr r3, [r7, #4] 80005fe: 689b ldr r3, [r3, #8] 8000600: 613b str r3, [r7, #16] temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2)); 8000602: 697b ldr r3, [r7, #20] 8000604: 005b lsls r3, r3, #1 8000606: 461a mov r2, r3 8000608: 2303 movs r3, #3 800060a: 4093 lsls r3, r2 800060c: 43db mvns r3, r3 800060e: 693a ldr r2, [r7, #16] 8000610: 4013 ands r3, r2 8000612: 613b str r3, [r7, #16] temp |= (GPIO_Init->Speed << (position * 2)); 8000614: 683b ldr r3, [r7, #0] 8000616: 68db ldr r3, [r3, #12] 8000618: 697a ldr r2, [r7, #20] 800061a: 0052 lsls r2, r2, #1 800061c: 4093 lsls r3, r2 800061e: 693a ldr r2, [r7, #16] 8000620: 4313 orrs r3, r2 8000622: 613b str r3, [r7, #16] GPIOx->OSPEEDR = temp; 8000624: 687b ldr r3, [r7, #4] 8000626: 693a ldr r2, [r7, #16] 8000628: 609a str r2, [r3, #8] /* Configure the IO Output Type */ temp = GPIOx->OTYPER; 800062a: 687b ldr r3, [r7, #4] 800062c: 685b ldr r3, [r3, #4] 800062e: 613b str r3, [r7, #16] temp &= ~(GPIO_OTYPER_OT0 << position) ; 8000630: 697b ldr r3, [r7, #20] 8000632: 2201 movs r2, #1 8000634: fa02 f303 lsl.w r3, r2, r3 8000638: 43db mvns r3, r3 800063a: 693a ldr r2, [r7, #16] 800063c: 4013 ands r3, r2 800063e: 613b str r3, [r7, #16] temp |= (((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position); 8000640: 683b ldr r3, [r7, #0] 8000642: 685b ldr r3, [r3, #4] 8000644: f003 0310 and.w r3, r3, #16 8000648: 091a lsrs r2, r3, #4 800064a: 697b ldr r3, [r7, #20] 800064c: fa02 f303 lsl.w r3, r2, r3 8000650: 693a ldr r2, [r7, #16] 8000652: 4313 orrs r3, r2 8000654: 613b str r3, [r7, #16] GPIOx->OTYPER = temp; 8000656: 687b ldr r3, [r7, #4] 8000658: 693a ldr r2, [r7, #16] 800065a: 605a str r2, [r3, #4] } #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */ /* Activate the Pull-up or Pull down resistor for the current IO */ temp = GPIOx->PUPDR; 800065c: 687b ldr r3, [r7, #4] 800065e: 68db ldr r3, [r3, #12] 8000660: 613b str r3, [r7, #16] temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2)); 8000662: 697b ldr r3, [r7, #20] 8000664: 005b lsls r3, r3, #1 8000666: 461a mov r2, r3 8000668: 2303 movs r3, #3 800066a: 4093 lsls r3, r2 800066c: 43db mvns r3, r3 800066e: 693a ldr r2, [r7, #16] 8000670: 4013 ands r3, r2 8000672: 613b str r3, [r7, #16] temp |= ((GPIO_Init->Pull) << (position * 2)); 8000674: 683b ldr r3, [r7, #0] 8000676: 689b ldr r3, [r3, #8] 8000678: 697a ldr r2, [r7, #20] 800067a: 0052 lsls r2, r2, #1 800067c: 4093 lsls r3, r2 800067e: 693a ldr r2, [r7, #16] 8000680: 4313 orrs r3, r2 8000682: 613b str r3, [r7, #16] GPIOx->PUPDR = temp; 8000684: 687b ldr r3, [r7, #4] 8000686: 693a ldr r2, [r7, #16] 8000688: 60da str r2, [r3, #12] /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 800068a: 683b ldr r3, [r7, #0] 800068c: 685b ldr r3, [r3, #4] 800068e: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000692: 2b00 cmp r3, #0 8000694: f000 8094 beq.w 80007c0 { /* Enable SYSCFG Clock */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8000698: 4a51 ldr r2, [pc, #324] ; (80007e0 ) 800069a: 4b51 ldr r3, [pc, #324] ; (80007e0 ) 800069c: 6e1b ldr r3, [r3, #96] ; 0x60 800069e: f043 0301 orr.w r3, r3, #1 80006a2: 6613 str r3, [r2, #96] ; 0x60 80006a4: 4b4e ldr r3, [pc, #312] ; (80007e0 ) 80006a6: 6e1b ldr r3, [r3, #96] ; 0x60 80006a8: f003 0301 and.w r3, r3, #1 80006ac: 60bb str r3, [r7, #8] 80006ae: 68bb ldr r3, [r7, #8] temp = SYSCFG->EXTICR[position >> 2]; 80006b0: 4a4c ldr r2, [pc, #304] ; (80007e4 ) 80006b2: 697b ldr r3, [r7, #20] 80006b4: 089b lsrs r3, r3, #2 80006b6: 3302 adds r3, #2 80006b8: f852 3023 ldr.w r3, [r2, r3, lsl #2] 80006bc: 613b str r3, [r7, #16] temp &= ~(((uint32_t)0x0F) << (4 * (position & 0x03))); 80006be: 697b ldr r3, [r7, #20] 80006c0: f003 0303 and.w r3, r3, #3 80006c4: 009b lsls r3, r3, #2 80006c6: 461a mov r2, r3 80006c8: 230f movs r3, #15 80006ca: 4093 lsls r3, r2 80006cc: 43db mvns r3, r3 80006ce: 693a ldr r2, [r7, #16] 80006d0: 4013 ands r3, r2 80006d2: 613b str r3, [r7, #16] temp |= (GPIO_GET_INDEX(GPIOx) << (4 * (position & 0x03))); 80006d4: 687b ldr r3, [r7, #4] 80006d6: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000 80006da: d00d beq.n 80006f8 80006dc: 687b ldr r3, [r7, #4] 80006de: 4a42 ldr r2, [pc, #264] ; (80007e8 ) 80006e0: 4293 cmp r3, r2 80006e2: d007 beq.n 80006f4 80006e4: 687b ldr r3, [r7, #4] 80006e6: 4a41 ldr r2, [pc, #260] ; (80007ec ) 80006e8: 4293 cmp r3, r2 80006ea: d101 bne.n 80006f0 80006ec: 2302 movs r3, #2 80006ee: e004 b.n 80006fa 80006f0: 2307 movs r3, #7 80006f2: e002 b.n 80006fa 80006f4: 2301 movs r3, #1 80006f6: e000 b.n 80006fa 80006f8: 2300 movs r3, #0 80006fa: 697a ldr r2, [r7, #20] 80006fc: f002 0203 and.w r2, r2, #3 8000700: 0092 lsls r2, r2, #2 8000702: 4093 lsls r3, r2 8000704: 693a ldr r2, [r7, #16] 8000706: 4313 orrs r3, r2 8000708: 613b str r3, [r7, #16] SYSCFG->EXTICR[position >> 2] = temp; 800070a: 4936 ldr r1, [pc, #216] ; (80007e4 ) 800070c: 697b ldr r3, [r7, #20] 800070e: 089b lsrs r3, r3, #2 8000710: 3302 adds r3, #2 8000712: 693a ldr r2, [r7, #16] 8000714: f841 2023 str.w r2, [r1, r3, lsl #2] /* Clear EXTI line configuration */ temp = EXTI->IMR1; 8000718: 4b35 ldr r3, [pc, #212] ; (80007f0 ) 800071a: 681b ldr r3, [r3, #0] 800071c: 613b str r3, [r7, #16] temp &= ~((uint32_t)iocurrent); 800071e: 68fb ldr r3, [r7, #12] 8000720: 43db mvns r3, r3 8000722: 693a ldr r2, [r7, #16] 8000724: 4013 ands r3, r2 8000726: 613b str r3, [r7, #16] if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 8000728: 683b ldr r3, [r7, #0] 800072a: 685b ldr r3, [r3, #4] 800072c: f403 3380 and.w r3, r3, #65536 ; 0x10000 8000730: 2b00 cmp r3, #0 8000732: d003 beq.n 800073c { temp |= iocurrent; 8000734: 693a ldr r2, [r7, #16] 8000736: 68fb ldr r3, [r7, #12] 8000738: 4313 orrs r3, r2 800073a: 613b str r3, [r7, #16] } EXTI->IMR1 = temp; 800073c: 4a2c ldr r2, [pc, #176] ; (80007f0 ) 800073e: 693b ldr r3, [r7, #16] 8000740: 6013 str r3, [r2, #0] temp = EXTI->EMR1; 8000742: 4b2b ldr r3, [pc, #172] ; (80007f0 ) 8000744: 685b ldr r3, [r3, #4] 8000746: 613b str r3, [r7, #16] temp &= ~((uint32_t)iocurrent); 8000748: 68fb ldr r3, [r7, #12] 800074a: 43db mvns r3, r3 800074c: 693a ldr r2, [r7, #16] 800074e: 4013 ands r3, r2 8000750: 613b str r3, [r7, #16] if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8000752: 683b ldr r3, [r7, #0] 8000754: 685b ldr r3, [r3, #4] 8000756: f403 3300 and.w r3, r3, #131072 ; 0x20000 800075a: 2b00 cmp r3, #0 800075c: d003 beq.n 8000766 { temp |= iocurrent; 800075e: 693a ldr r2, [r7, #16] 8000760: 68fb ldr r3, [r7, #12] 8000762: 4313 orrs r3, r2 8000764: 613b str r3, [r7, #16] } EXTI->EMR1 = temp; 8000766: 4a22 ldr r2, [pc, #136] ; (80007f0 ) 8000768: 693b ldr r3, [r7, #16] 800076a: 6053 str r3, [r2, #4] /* Clear Rising Falling edge configuration */ temp = EXTI->RTSR1; 800076c: 4b20 ldr r3, [pc, #128] ; (80007f0 ) 800076e: 689b ldr r3, [r3, #8] 8000770: 613b str r3, [r7, #16] temp &= ~((uint32_t)iocurrent); 8000772: 68fb ldr r3, [r7, #12] 8000774: 43db mvns r3, r3 8000776: 693a ldr r2, [r7, #16] 8000778: 4013 ands r3, r2 800077a: 613b str r3, [r7, #16] if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 800077c: 683b ldr r3, [r7, #0] 800077e: 685b ldr r3, [r3, #4] 8000780: f403 1380 and.w r3, r3, #1048576 ; 0x100000 8000784: 2b00 cmp r3, #0 8000786: d003 beq.n 8000790 { temp |= iocurrent; 8000788: 693a ldr r2, [r7, #16] 800078a: 68fb ldr r3, [r7, #12] 800078c: 4313 orrs r3, r2 800078e: 613b str r3, [r7, #16] } EXTI->RTSR1 = temp; 8000790: 4a17 ldr r2, [pc, #92] ; (80007f0 ) 8000792: 693b ldr r3, [r7, #16] 8000794: 6093 str r3, [r2, #8] temp = EXTI->FTSR1; 8000796: 4b16 ldr r3, [pc, #88] ; (80007f0 ) 8000798: 68db ldr r3, [r3, #12] 800079a: 613b str r3, [r7, #16] temp &= ~((uint32_t)iocurrent); 800079c: 68fb ldr r3, [r7, #12] 800079e: 43db mvns r3, r3 80007a0: 693a ldr r2, [r7, #16] 80007a2: 4013 ands r3, r2 80007a4: 613b str r3, [r7, #16] if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 80007a6: 683b ldr r3, [r7, #0] 80007a8: 685b ldr r3, [r3, #4] 80007aa: f403 1300 and.w r3, r3, #2097152 ; 0x200000 80007ae: 2b00 cmp r3, #0 80007b0: d003 beq.n 80007ba { temp |= iocurrent; 80007b2: 693a ldr r2, [r7, #16] 80007b4: 68fb ldr r3, [r7, #12] 80007b6: 4313 orrs r3, r2 80007b8: 613b str r3, [r7, #16] } EXTI->FTSR1 = temp; 80007ba: 4a0d ldr r2, [pc, #52] ; (80007f0 ) 80007bc: 693b ldr r3, [r7, #16] 80007be: 60d3 str r3, [r2, #12] } } position++; 80007c0: 697b ldr r3, [r7, #20] 80007c2: 3301 adds r3, #1 80007c4: 617b str r3, [r7, #20] assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); /* Configure the port pins */ while (((GPIO_Init->Pin) >> position) != RESET) 80007c6: 683b ldr r3, [r7, #0] 80007c8: 681a ldr r2, [r3, #0] 80007ca: 697b ldr r3, [r7, #20] 80007cc: fa22 f303 lsr.w r3, r2, r3 80007d0: 2b00 cmp r3, #0 80007d2: f47f aeb3 bne.w 800053c } } position++; } } 80007d6: 371c adds r7, #28 80007d8: 46bd mov sp, r7 80007da: f85d 7b04 ldr.w r7, [sp], #4 80007de: 4770 bx lr 80007e0: 40021000 .word 0x40021000 80007e4: 40010000 .word 0x40010000 80007e8: 48000400 .word 0x48000400 80007ec: 48000800 .word 0x48000800 80007f0: 40010400 .word 0x40010400 080007f4 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 80007f4: b480 push {r7} 80007f6: b083 sub sp, #12 80007f8: af00 add r7, sp, #0 80007fa: 6078 str r0, [r7, #4] 80007fc: 460b mov r3, r1 80007fe: 807b strh r3, [r7, #2] 8000800: 4613 mov r3, r2 8000802: 707b strb r3, [r7, #1] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if(PinState != GPIO_PIN_RESET) 8000804: 787b ldrb r3, [r7, #1] 8000806: 2b00 cmp r3, #0 8000808: d003 beq.n 8000812 { GPIOx->BSRR = (uint32_t)GPIO_Pin; 800080a: 887a ldrh r2, [r7, #2] 800080c: 687b ldr r3, [r7, #4] 800080e: 619a str r2, [r3, #24] 8000810: e002 b.n 8000818 } else { GPIOx->BRR = (uint32_t)GPIO_Pin; 8000812: 887a ldrh r2, [r7, #2] 8000814: 687b ldr r3, [r7, #4] 8000816: 629a str r2, [r3, #40] ; 0x28 } } 8000818: 370c adds r7, #12 800081a: 46bd mov sp, r7 800081c: f85d 7b04 ldr.w r7, [sp], #4 8000820: 4770 bx lr 8000822: bf00 nop 08000824 : /** * @brief Return Voltage Scaling Range. * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) */ uint32_t HAL_PWREx_GetVoltageRange(void) { 8000824: b480 push {r7} 8000826: af00 add r7, sp, #0 return (PWR->CR1 & PWR_CR1_VOS); 8000828: 4b04 ldr r3, [pc, #16] ; (800083c ) 800082a: 681b ldr r3, [r3, #0] 800082c: f403 63c0 and.w r3, r3, #1536 ; 0x600 } 8000830: 4618 mov r0, r3 8000832: 46bd mov sp, r7 8000834: f85d 7b04 ldr.w r7, [sp], #4 8000838: 4770 bx lr 800083a: bf00 nop 800083c: 40007000 .word 0x40007000 08000840 : * cleared before returning the status. If the flag is not cleared within * 50 microseconds, HAL_TIMEOUT status is reported. * @retval HAL Status */ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) { 8000840: b480 push {r7} 8000842: b085 sub sp, #20 8000844: af00 add r7, sp, #0 8000846: 6078 str r0, [r7, #4] uint32_t wait_loop_index = 0; 8000848: 2300 movs r3, #0 800084a: 60fb str r3, [r7, #12] assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); /* If Set Range 1 */ if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 800084c: 687b ldr r3, [r7, #4] 800084e: f5b3 7f00 cmp.w r3, #512 ; 0x200 8000852: d12d bne.n 80008b0 { if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1) 8000854: 4b21 ldr r3, [pc, #132] ; (80008dc ) 8000856: 681b ldr r3, [r3, #0] 8000858: f403 63c0 and.w r3, r3, #1536 ; 0x600 800085c: f5b3 7f00 cmp.w r3, #512 ; 0x200 8000860: d035 beq.n 80008ce { /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 8000862: 4a1e ldr r2, [pc, #120] ; (80008dc ) 8000864: 4b1d ldr r3, [pc, #116] ; (80008dc ) 8000866: 681b ldr r3, [r3, #0] 8000868: f423 63c0 bic.w r3, r3, #1536 ; 0x600 800086c: f443 7300 orr.w r3, r3, #512 ; 0x200 8000870: 6013 str r3, [r2, #0] /* Wait until VOSF is cleared */ wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); 8000872: 4b1b ldr r3, [pc, #108] ; (80008e0 ) 8000874: 681b ldr r3, [r3, #0] 8000876: 4a1b ldr r2, [pc, #108] ; (80008e4 ) 8000878: fba2 2303 umull r2, r3, r2, r3 800087c: 0c9b lsrs r3, r3, #18 800087e: 2232 movs r2, #50 ; 0x32 8000880: fb02 f303 mul.w r3, r2, r3 8000884: 60fb str r3, [r7, #12] while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) 8000886: e002 b.n 800088e { wait_loop_index--; 8000888: 68fb ldr r3, [r7, #12] 800088a: 3b01 subs r3, #1 800088c: 60fb str r3, [r7, #12] /* Set Range 1 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); /* Wait until VOSF is cleared */ wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) 800088e: 68fb ldr r3, [r7, #12] 8000890: 2b00 cmp r3, #0 8000892: d005 beq.n 80008a0 8000894: 4b11 ldr r3, [pc, #68] ; (80008dc ) 8000896: 695b ldr r3, [r3, #20] 8000898: f403 6380 and.w r3, r3, #1024 ; 0x400 800089c: 2b00 cmp r3, #0 800089e: d1f3 bne.n 8000888 { wait_loop_index--; } if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 80008a0: 4b0e ldr r3, [pc, #56] ; (80008dc ) 80008a2: 695b ldr r3, [r3, #20] 80008a4: f403 6380 and.w r3, r3, #1024 ; 0x400 80008a8: 2b00 cmp r3, #0 80008aa: d010 beq.n 80008ce { return HAL_TIMEOUT; 80008ac: 2303 movs r3, #3 80008ae: e00f b.n 80008d0 } } } else { if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2) 80008b0: 4b0a ldr r3, [pc, #40] ; (80008dc ) 80008b2: 681b ldr r3, [r3, #0] 80008b4: f403 63c0 and.w r3, r3, #1536 ; 0x600 80008b8: f5b3 6f80 cmp.w r3, #1024 ; 0x400 80008bc: d007 beq.n 80008ce { /* Set Range 2 */ MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); 80008be: 4a07 ldr r2, [pc, #28] ; (80008dc ) 80008c0: 4b06 ldr r3, [pc, #24] ; (80008dc ) 80008c2: 681b ldr r3, [r3, #0] 80008c4: f423 63c0 bic.w r3, r3, #1536 ; 0x600 80008c8: f443 6380 orr.w r3, r3, #1024 ; 0x400 80008cc: 6013 str r3, [r2, #0] /* No need to wait for VOSF to be cleared for this transition */ } } return HAL_OK; 80008ce: 2300 movs r3, #0 } 80008d0: 4618 mov r0, r3 80008d2: 3714 adds r7, #20 80008d4: 46bd mov sp, r7 80008d6: f85d 7b04 ldr.w r7, [sp], #4 80008da: 4770 bx lr 80008dc: 40007000 .word 0x40007000 80008e0: 20000000 .word 0x20000000 80008e4: 431bde83 .word 0x431bde83 080008e8 : * supported by this macro. User should request a transition to HSE Off * first and then HSE On or HSE Bypass. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) { 80008e8: b580 push {r7, lr} 80008ea: b08c sub sp, #48 ; 0x30 80008ec: af00 add r7, sp, #0 80008ee: 6078 str r0, [r7, #4] uint32_t tickstart = 0; 80008f0: 2300 movs r3, #0 80008f2: 62bb str r3, [r7, #40] ; 0x28 /* Check the parameters */ assert_param(RCC_OscInitStruct != NULL); assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*----------------------------- MSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) 80008f4: 687b ldr r3, [r7, #4] 80008f6: 681b ldr r3, [r3, #0] 80008f8: f003 0310 and.w r3, r3, #16 80008fc: 2b00 cmp r3, #0 80008fe: f000 80db beq.w 8000ab8 assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); /* When the MSI is used as system clock it will not be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) ) 8000902: 4ba3 ldr r3, [pc, #652] ; (8000b90 ) 8000904: 689b ldr r3, [r3, #8] 8000906: f003 030c and.w r3, r3, #12 800090a: 2b00 cmp r3, #0 800090c: f040 8084 bne.w 8000a18 { if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF)) 8000910: 4b9f ldr r3, [pc, #636] ; (8000b90 ) 8000912: 681b ldr r3, [r3, #0] 8000914: f003 0302 and.w r3, r3, #2 8000918: 2b00 cmp r3, #0 800091a: d005 beq.n 8000928 800091c: 687b ldr r3, [r7, #4] 800091e: 699b ldr r3, [r3, #24] 8000920: 2b00 cmp r3, #0 8000922: d101 bne.n 8000928 { return HAL_ERROR; 8000924: 2301 movs r3, #1 8000926: e39b b.n 8001060 else { /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) 8000928: 687b ldr r3, [r7, #4] 800092a: 6a1a ldr r2, [r3, #32] 800092c: 4b98 ldr r3, [pc, #608] ; (8000b90 ) 800092e: 681b ldr r3, [r3, #0] 8000930: f003 0308 and.w r3, r3, #8 8000934: 2b00 cmp r3, #0 8000936: d004 beq.n 8000942 8000938: 4b95 ldr r3, [pc, #596] ; (8000b90 ) 800093a: 681b ldr r3, [r3, #0] 800093c: f003 03f0 and.w r3, r3, #240 ; 0xf0 8000940: e005 b.n 800094e 8000942: 4b93 ldr r3, [pc, #588] ; (8000b90 ) 8000944: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8000948: f403 6370 and.w r3, r3, #3840 ; 0xf00 800094c: 091b lsrs r3, r3, #4 800094e: 429a cmp r2, r3 8000950: d923 bls.n 800099a { /* First increase number of wait states update if necessary */ if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 8000952: 687b ldr r3, [r7, #4] 8000954: 6a1b ldr r3, [r3, #32] 8000956: 4618 mov r0, r3 8000958: f000 fdb4 bl 80014c4 800095c: 4603 mov r3, r0 800095e: 2b00 cmp r3, #0 8000960: d001 beq.n 8000966 { return HAL_ERROR; 8000962: 2301 movs r3, #1 8000964: e37c b.n 8001060 } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 8000966: 4a8a ldr r2, [pc, #552] ; (8000b90 ) 8000968: 4b89 ldr r3, [pc, #548] ; (8000b90 ) 800096a: 681b ldr r3, [r3, #0] 800096c: f043 0308 orr.w r3, r3, #8 8000970: 6013 str r3, [r2, #0] 8000972: 4987 ldr r1, [pc, #540] ; (8000b90 ) 8000974: 4b86 ldr r3, [pc, #536] ; (8000b90 ) 8000976: 681b ldr r3, [r3, #0] 8000978: f023 02f0 bic.w r2, r3, #240 ; 0xf0 800097c: 687b ldr r3, [r7, #4] 800097e: 6a1b ldr r3, [r3, #32] 8000980: 4313 orrs r3, r2 8000982: 600b str r3, [r1, #0] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 8000984: 4982 ldr r1, [pc, #520] ; (8000b90 ) 8000986: 4b82 ldr r3, [pc, #520] ; (8000b90 ) 8000988: 685b ldr r3, [r3, #4] 800098a: f423 427f bic.w r2, r3, #65280 ; 0xff00 800098e: 687b ldr r3, [r7, #4] 8000990: 69db ldr r3, [r3, #28] 8000992: 021b lsls r3, r3, #8 8000994: 4313 orrs r3, r2 8000996: 604b str r3, [r1, #4] 8000998: e022 b.n 80009e0 } else { /* Else, keep current flash latency while decreasing applies */ /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 800099a: 4a7d ldr r2, [pc, #500] ; (8000b90 ) 800099c: 4b7c ldr r3, [pc, #496] ; (8000b90 ) 800099e: 681b ldr r3, [r3, #0] 80009a0: f043 0308 orr.w r3, r3, #8 80009a4: 6013 str r3, [r2, #0] 80009a6: 497a ldr r1, [pc, #488] ; (8000b90 ) 80009a8: 4b79 ldr r3, [pc, #484] ; (8000b90 ) 80009aa: 681b ldr r3, [r3, #0] 80009ac: f023 02f0 bic.w r2, r3, #240 ; 0xf0 80009b0: 687b ldr r3, [r7, #4] 80009b2: 6a1b ldr r3, [r3, #32] 80009b4: 4313 orrs r3, r2 80009b6: 600b str r3, [r1, #0] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 80009b8: 4975 ldr r1, [pc, #468] ; (8000b90 ) 80009ba: 4b75 ldr r3, [pc, #468] ; (8000b90 ) 80009bc: 685b ldr r3, [r3, #4] 80009be: f423 427f bic.w r2, r3, #65280 ; 0xff00 80009c2: 687b ldr r3, [r7, #4] 80009c4: 69db ldr r3, [r3, #28] 80009c6: 021b lsls r3, r3, #8 80009c8: 4313 orrs r3, r2 80009ca: 604b str r3, [r1, #4] /* Decrease number of wait states update if necessary */ if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) 80009cc: 687b ldr r3, [r7, #4] 80009ce: 6a1b ldr r3, [r3, #32] 80009d0: 4618 mov r0, r3 80009d2: f000 fd77 bl 80014c4 80009d6: 4603 mov r3, r0 80009d8: 2b00 cmp r3, #0 80009da: d001 beq.n 80009e0 { return HAL_ERROR; 80009dc: 2301 movs r3, #1 80009de: e33f b.n 8001060 } } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; 80009e0: f000 fc68 bl 80012b4 80009e4: 4601 mov r1, r0 80009e6: 4b6a ldr r3, [pc, #424] ; (8000b90 ) 80009e8: 689b ldr r3, [r3, #8] 80009ea: f003 02f0 and.w r2, r3, #240 ; 0xf0 80009ee: 23f0 movs r3, #240 ; 0xf0 80009f0: 627b str r3, [r7, #36] ; 0x24 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80009f2: 6a7b ldr r3, [r7, #36] ; 0x24 80009f4: fa93 f3a3 rbit r3, r3 80009f8: 623b str r3, [r7, #32] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 80009fa: 6a3b ldr r3, [r7, #32] 80009fc: fab3 f383 clz r3, r3 8000a00: fa22 f303 lsr.w r3, r2, r3 8000a04: 4a63 ldr r2, [pc, #396] ; (8000b94 ) 8000a06: 5cd3 ldrb r3, [r2, r3] 8000a08: fa21 f303 lsr.w r3, r1, r3 8000a0c: 4a62 ldr r2, [pc, #392] ; (8000b98 ) 8000a0e: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); 8000a10: 2000 movs r0, #0 8000a12: f7ff fc47 bl 80002a4 8000a16: e04f b.n 8000ab8 } } else { /* Check the MSI State */ if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF) 8000a18: 687b ldr r3, [r7, #4] 8000a1a: 699b ldr r3, [r3, #24] 8000a1c: 2b00 cmp r3, #0 8000a1e: d032 beq.n 8000a86 { /* Enable the Internal High Speed oscillator (MSI). */ __HAL_RCC_MSI_ENABLE(); 8000a20: 4a5b ldr r2, [pc, #364] ; (8000b90 ) 8000a22: 4b5b ldr r3, [pc, #364] ; (8000b90 ) 8000a24: 681b ldr r3, [r3, #0] 8000a26: f043 0301 orr.w r3, r3, #1 8000a2a: 6013 str r3, [r2, #0] /* Get timeout */ tickstart = HAL_GetTick(); 8000a2c: f7ff fc64 bl 80002f8 8000a30: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till MSI is ready */ while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) 8000a32: e008 b.n 8000a46 { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 8000a34: f7ff fc60 bl 80002f8 8000a38: 4602 mov r2, r0 8000a3a: 6abb ldr r3, [r7, #40] ; 0x28 8000a3c: 1ad3 subs r3, r2, r3 8000a3e: 2b02 cmp r3, #2 8000a40: d901 bls.n 8000a46 { return HAL_TIMEOUT; 8000a42: 2303 movs r3, #3 8000a44: e30c b.n 8001060 /* Get timeout */ tickstart = HAL_GetTick(); /* Wait till MSI is ready */ while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) 8000a46: 4b52 ldr r3, [pc, #328] ; (8000b90 ) 8000a48: 681b ldr r3, [r3, #0] 8000a4a: f003 0302 and.w r3, r3, #2 8000a4e: 2b00 cmp r3, #0 8000a50: d0f0 beq.n 8000a34 { return HAL_TIMEOUT; } } /* Selects the Multiple Speed oscillator (MSI) clock range .*/ __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); 8000a52: 4a4f ldr r2, [pc, #316] ; (8000b90 ) 8000a54: 4b4e ldr r3, [pc, #312] ; (8000b90 ) 8000a56: 681b ldr r3, [r3, #0] 8000a58: f043 0308 orr.w r3, r3, #8 8000a5c: 6013 str r3, [r2, #0] 8000a5e: 494c ldr r1, [pc, #304] ; (8000b90 ) 8000a60: 4b4b ldr r3, [pc, #300] ; (8000b90 ) 8000a62: 681b ldr r3, [r3, #0] 8000a64: f023 02f0 bic.w r2, r3, #240 ; 0xf0 8000a68: 687b ldr r3, [r7, #4] 8000a6a: 6a1b ldr r3, [r3, #32] 8000a6c: 4313 orrs r3, r2 8000a6e: 600b str r3, [r1, #0] /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); 8000a70: 4947 ldr r1, [pc, #284] ; (8000b90 ) 8000a72: 4b47 ldr r3, [pc, #284] ; (8000b90 ) 8000a74: 685b ldr r3, [r3, #4] 8000a76: f423 427f bic.w r2, r3, #65280 ; 0xff00 8000a7a: 687b ldr r3, [r7, #4] 8000a7c: 69db ldr r3, [r3, #28] 8000a7e: 021b lsls r3, r3, #8 8000a80: 4313 orrs r3, r2 8000a82: 604b str r3, [r1, #4] 8000a84: e018 b.n 8000ab8 } else { /* Disable the Internal High Speed oscillator (MSI). */ __HAL_RCC_MSI_DISABLE(); 8000a86: 4a42 ldr r2, [pc, #264] ; (8000b90 ) 8000a88: 4b41 ldr r3, [pc, #260] ; (8000b90 ) 8000a8a: 681b ldr r3, [r3, #0] 8000a8c: f023 0301 bic.w r3, r3, #1 8000a90: 6013 str r3, [r2, #0] /* Get timeout */ tickstart = HAL_GetTick(); 8000a92: f7ff fc31 bl 80002f8 8000a96: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till MSI is ready */ while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) 8000a98: e008 b.n 8000aac { if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) 8000a9a: f7ff fc2d bl 80002f8 8000a9e: 4602 mov r2, r0 8000aa0: 6abb ldr r3, [r7, #40] ; 0x28 8000aa2: 1ad3 subs r3, r2, r3 8000aa4: 2b02 cmp r3, #2 8000aa6: d901 bls.n 8000aac { return HAL_TIMEOUT; 8000aa8: 2303 movs r3, #3 8000aaa: e2d9 b.n 8001060 /* Get timeout */ tickstart = HAL_GetTick(); /* Wait till MSI is ready */ while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != RESET) 8000aac: 4b38 ldr r3, [pc, #224] ; (8000b90 ) 8000aae: 681b ldr r3, [r3, #0] 8000ab0: f003 0302 and.w r3, r3, #2 8000ab4: 2b00 cmp r3, #0 8000ab6: d1f0 bne.n 8000a9a } } } } /*------------------------------- HSE Configuration ------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8000ab8: 687b ldr r3, [r7, #4] 8000aba: 681b ldr r3, [r3, #0] 8000abc: f003 0301 and.w r3, r3, #1 8000ac0: 2b00 cmp r3, #0 8000ac2: d07a beq.n 8000bba { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || 8000ac4: 4b32 ldr r3, [pc, #200] ; (8000b90 ) 8000ac6: 689b ldr r3, [r3, #8] 8000ac8: f003 030c and.w r3, r3, #12 8000acc: 2b08 cmp r3, #8 8000ace: d00b beq.n 8000ae8 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8000ad0: 4b2f ldr r3, [pc, #188] ; (8000b90 ) 8000ad2: 689b ldr r3, [r3, #8] 8000ad4: f003 030c and.w r3, r3, #12 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || 8000ad8: 2b0c cmp r3, #12 8000ada: d112 bne.n 8000b02 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) 8000adc: 4b2c ldr r3, [pc, #176] ; (8000b90 ) 8000ade: 68db ldr r3, [r3, #12] 8000ae0: f003 0303 and.w r3, r3, #3 8000ae4: 2b03 cmp r3, #3 8000ae6: d10c bne.n 8000b02 { if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000ae8: 4b29 ldr r3, [pc, #164] ; (8000b90 ) 8000aea: 681b ldr r3, [r3, #0] 8000aec: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000af0: 2b00 cmp r3, #0 8000af2: d005 beq.n 8000b00 8000af4: 687b ldr r3, [r7, #4] 8000af6: 685b ldr r3, [r3, #4] 8000af8: 2b00 cmp r3, #0 8000afa: d101 bne.n 8000b00 { return HAL_ERROR; 8000afc: 2301 movs r3, #1 8000afe: e2af b.n 8001060 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE))) { if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)) 8000b00: e05b b.n 8000bba } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8000b02: 687b ldr r3, [r7, #4] 8000b04: 685b ldr r3, [r3, #4] 8000b06: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 8000b0a: d106 bne.n 8000b1a 8000b0c: 4a20 ldr r2, [pc, #128] ; (8000b90 ) 8000b0e: 4b20 ldr r3, [pc, #128] ; (8000b90 ) 8000b10: 681b ldr r3, [r3, #0] 8000b12: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000b16: 6013 str r3, [r2, #0] 8000b18: e01d b.n 8000b56 8000b1a: 687b ldr r3, [r7, #4] 8000b1c: 685b ldr r3, [r3, #4] 8000b1e: f5b3 2fa0 cmp.w r3, #327680 ; 0x50000 8000b22: d10c bne.n 8000b3e 8000b24: 4a1a ldr r2, [pc, #104] ; (8000b90 ) 8000b26: 4b1a ldr r3, [pc, #104] ; (8000b90 ) 8000b28: 681b ldr r3, [r3, #0] 8000b2a: f443 2380 orr.w r3, r3, #262144 ; 0x40000 8000b2e: 6013 str r3, [r2, #0] 8000b30: 4a17 ldr r2, [pc, #92] ; (8000b90 ) 8000b32: 4b17 ldr r3, [pc, #92] ; (8000b90 ) 8000b34: 681b ldr r3, [r3, #0] 8000b36: f443 3380 orr.w r3, r3, #65536 ; 0x10000 8000b3a: 6013 str r3, [r2, #0] 8000b3c: e00b b.n 8000b56 8000b3e: 4a14 ldr r2, [pc, #80] ; (8000b90 ) 8000b40: 4b13 ldr r3, [pc, #76] ; (8000b90 ) 8000b42: 681b ldr r3, [r3, #0] 8000b44: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8000b48: 6013 str r3, [r2, #0] 8000b4a: 4a11 ldr r2, [pc, #68] ; (8000b90 ) 8000b4c: 4b10 ldr r3, [pc, #64] ; (8000b90 ) 8000b4e: 681b ldr r3, [r3, #0] 8000b50: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8000b54: 6013 str r3, [r2, #0] /* Check the HSE State */ if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8000b56: 687b ldr r3, [r7, #4] 8000b58: 685b ldr r3, [r3, #4] 8000b5a: 2b00 cmp r3, #0 8000b5c: d013 beq.n 8000b86 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8000b5e: f7ff fbcb bl 80002f8 8000b62: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till HSE is ready */ while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) 8000b64: e008 b.n 8000b78 { if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000b66: f7ff fbc7 bl 80002f8 8000b6a: 4602 mov r2, r0 8000b6c: 6abb ldr r3, [r7, #40] ; 0x28 8000b6e: 1ad3 subs r3, r2, r3 8000b70: 2b64 cmp r3, #100 ; 0x64 8000b72: d901 bls.n 8000b78 { return HAL_TIMEOUT; 8000b74: 2303 movs r3, #3 8000b76: e273 b.n 8001060 { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSE is ready */ while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) 8000b78: 4b05 ldr r3, [pc, #20] ; (8000b90 ) 8000b7a: 681b ldr r3, [r3, #0] 8000b7c: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000b80: 2b00 cmp r3, #0 8000b82: d0f0 beq.n 8000b66 8000b84: e019 b.n 8000bba } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8000b86: f7ff fbb7 bl 80002f8 8000b8a: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till HSE is disabled */ while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8000b8c: e00f b.n 8000bae 8000b8e: bf00 nop 8000b90: 40021000 .word 0x40021000 8000b94: 08002080 .word 0x08002080 8000b98: 20000000 .word 0x20000000 { if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) 8000b9c: f7ff fbac bl 80002f8 8000ba0: 4602 mov r2, r0 8000ba2: 6abb ldr r3, [r7, #40] ; 0x28 8000ba4: 1ad3 subs r3, r2, r3 8000ba6: 2b64 cmp r3, #100 ; 0x64 8000ba8: d901 bls.n 8000bae { return HAL_TIMEOUT; 8000baa: 2303 movs r3, #3 8000bac: e258 b.n 8001060 { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSE is disabled */ while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET) 8000bae: 4baf ldr r3, [pc, #700] ; (8000e6c ) 8000bb0: 681b ldr r3, [r3, #0] 8000bb2: f403 3300 and.w r3, r3, #131072 ; 0x20000 8000bb6: 2b00 cmp r3, #0 8000bb8: d1f0 bne.n 8000b9c } } } } /*----------------------------- HSI Configuration --------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8000bba: 687b ldr r3, [r7, #4] 8000bbc: 681b ldr r3, [r3, #0] 8000bbe: f003 0302 and.w r3, r3, #2 8000bc2: 2b00 cmp r3, #0 8000bc4: d07f beq.n 8000cc6 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || 8000bc6: 4ba9 ldr r3, [pc, #676] ; (8000e6c ) 8000bc8: 689b ldr r3, [r3, #8] 8000bca: f003 030c and.w r3, r3, #12 8000bce: 2b04 cmp r3, #4 8000bd0: d00b beq.n 8000bea ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 8000bd2: 4ba6 ldr r3, [pc, #664] ; (8000e6c ) 8000bd4: 689b ldr r3, [r3, #8] 8000bd6: f003 030c and.w r3, r3, #12 /* Check the parameters */ assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || 8000bda: 2b0c cmp r3, #12 8000bdc: d127 bne.n 8000c2e ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) 8000bde: 4ba3 ldr r3, [pc, #652] ; (8000e6c ) 8000be0: 68db ldr r3, [r3, #12] 8000be2: f003 0303 and.w r3, r3, #3 8000be6: 2b02 cmp r3, #2 8000be8: d121 bne.n 8000c2e { /* When HSI is used as system clock it will not be disabled */ if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8000bea: 4ba0 ldr r3, [pc, #640] ; (8000e6c ) 8000bec: 681b ldr r3, [r3, #0] 8000bee: f403 6380 and.w r3, r3, #1024 ; 0x400 8000bf2: 2b00 cmp r3, #0 8000bf4: d005 beq.n 8000c02 8000bf6: 687b ldr r3, [r7, #4] 8000bf8: 68db ldr r3, [r3, #12] 8000bfa: 2b00 cmp r3, #0 8000bfc: d101 bne.n 8000c02 { return HAL_ERROR; 8000bfe: 2301 movs r3, #1 8000c00: e22e b.n 8001060 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000c02: 489a ldr r0, [pc, #616] ; (8000e6c ) 8000c04: 4b99 ldr r3, [pc, #612] ; (8000e6c ) 8000c06: 685b ldr r3, [r3, #4] 8000c08: f023 52f8 bic.w r2, r3, #520093696 ; 0x1f000000 8000c0c: 687b ldr r3, [r7, #4] 8000c0e: 6919 ldr r1, [r3, #16] 8000c10: f04f 53f8 mov.w r3, #520093696 ; 0x1f000000 8000c14: 61fb str r3, [r7, #28] __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8000c16: 69fb ldr r3, [r7, #28] 8000c18: fa93 f3a3 rbit r3, r3 8000c1c: 61bb str r3, [r7, #24] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 8000c1e: 69bb ldr r3, [r7, #24] 8000c20: fab3 f383 clz r3, r3 8000c24: fa01 f303 lsl.w r3, r1, r3 8000c28: 4313 orrs r3, r2 8000c2a: 6043 str r3, [r0, #4] /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI))) { /* When HSI is used as system clock it will not be disabled */ if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)) 8000c2c: e04b b.n 8000cc6 } } else { /* Check the HSI State */ if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8000c2e: 687b ldr r3, [r7, #4] 8000c30: 68db ldr r3, [r3, #12] 8000c32: 2b00 cmp r3, #0 8000c34: d02e beq.n 8000c94 { /* Enable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_ENABLE(); 8000c36: 4a8d ldr r2, [pc, #564] ; (8000e6c ) 8000c38: 4b8c ldr r3, [pc, #560] ; (8000e6c ) 8000c3a: 681b ldr r3, [r3, #0] 8000c3c: f443 7380 orr.w r3, r3, #256 ; 0x100 8000c40: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8000c42: f7ff fb59 bl 80002f8 8000c46: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till HSI is ready */ while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8000c48: e008 b.n 8000c5c { if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8000c4a: f7ff fb55 bl 80002f8 8000c4e: 4602 mov r2, r0 8000c50: 6abb ldr r3, [r7, #40] ; 0x28 8000c52: 1ad3 subs r3, r2, r3 8000c54: 2b02 cmp r3, #2 8000c56: d901 bls.n 8000c5c { return HAL_TIMEOUT; 8000c58: 2303 movs r3, #3 8000c5a: e201 b.n 8001060 /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI is ready */ while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 8000c5c: 4b83 ldr r3, [pc, #524] ; (8000e6c ) 8000c5e: 681b ldr r3, [r3, #0] 8000c60: f403 6380 and.w r3, r3, #1024 ; 0x400 8000c64: 2b00 cmp r3, #0 8000c66: d0f0 beq.n 8000c4a return HAL_TIMEOUT; } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8000c68: 4880 ldr r0, [pc, #512] ; (8000e6c ) 8000c6a: 4b80 ldr r3, [pc, #512] ; (8000e6c ) 8000c6c: 685b ldr r3, [r3, #4] 8000c6e: f023 52f8 bic.w r2, r3, #520093696 ; 0x1f000000 8000c72: 687b ldr r3, [r7, #4] 8000c74: 6919 ldr r1, [r3, #16] 8000c76: f04f 53f8 mov.w r3, #520093696 ; 0x1f000000 8000c7a: 617b str r3, [r7, #20] __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8000c7c: 697b ldr r3, [r7, #20] 8000c7e: fa93 f3a3 rbit r3, r3 8000c82: 613b str r3, [r7, #16] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 8000c84: 693b ldr r3, [r7, #16] 8000c86: fab3 f383 clz r3, r3 8000c8a: fa01 f303 lsl.w r3, r1, r3 8000c8e: 4313 orrs r3, r2 8000c90: 6043 str r3, [r0, #4] 8000c92: e018 b.n 8000cc6 } else { /* Disable the Internal High Speed oscillator (HSI). */ __HAL_RCC_HSI_DISABLE(); 8000c94: 4a75 ldr r2, [pc, #468] ; (8000e6c ) 8000c96: 4b75 ldr r3, [pc, #468] ; (8000e6c ) 8000c98: 681b ldr r3, [r3, #0] 8000c9a: f423 7380 bic.w r3, r3, #256 ; 0x100 8000c9e: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8000ca0: f7ff fb2a bl 80002f8 8000ca4: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till HSI is disabled */ while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) 8000ca6: e008 b.n 8000cba { if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) 8000ca8: f7ff fb26 bl 80002f8 8000cac: 4602 mov r2, r0 8000cae: 6abb ldr r3, [r7, #40] ; 0x28 8000cb0: 1ad3 subs r3, r2, r3 8000cb2: 2b02 cmp r3, #2 8000cb4: d901 bls.n 8000cba { return HAL_TIMEOUT; 8000cb6: 2303 movs r3, #3 8000cb8: e1d2 b.n 8001060 /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI is disabled */ while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != RESET) 8000cba: 4b6c ldr r3, [pc, #432] ; (8000e6c ) 8000cbc: 681b ldr r3, [r3, #0] 8000cbe: f403 6380 and.w r3, r3, #1024 ; 0x400 8000cc2: 2b00 cmp r3, #0 8000cc4: d1f0 bne.n 8000ca8 } } } } /*------------------------------ LSI Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8000cc6: 687b ldr r3, [r7, #4] 8000cc8: 681b ldr r3, [r3, #0] 8000cca: f003 0308 and.w r3, r3, #8 8000cce: 2b00 cmp r3, #0 8000cd0: d03c beq.n 8000d4c { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check the LSI State */ if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8000cd2: 687b ldr r3, [r7, #4] 8000cd4: 695b ldr r3, [r3, #20] 8000cd6: 2b00 cmp r3, #0 8000cd8: d01c beq.n 8000d14 { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8000cda: 4a64 ldr r2, [pc, #400] ; (8000e6c ) 8000cdc: 4b63 ldr r3, [pc, #396] ; (8000e6c ) 8000cde: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8000ce2: f043 0301 orr.w r3, r3, #1 8000ce6: f8c2 3094 str.w r3, [r2, #148] ; 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8000cea: f7ff fb05 bl 80002f8 8000cee: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till LSI is ready */ while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RESET) 8000cf0: e008 b.n 8000d04 { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8000cf2: f7ff fb01 bl 80002f8 8000cf6: 4602 mov r2, r0 8000cf8: 6abb ldr r3, [r7, #40] ; 0x28 8000cfa: 1ad3 subs r3, r2, r3 8000cfc: 2b02 cmp r3, #2 8000cfe: d901 bls.n 8000d04 { return HAL_TIMEOUT; 8000d00: 2303 movs r3, #3 8000d02: e1ad b.n 8001060 /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSI is ready */ while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == RESET) 8000d04: 4b59 ldr r3, [pc, #356] ; (8000e6c ) 8000d06: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8000d0a: f003 0302 and.w r3, r3, #2 8000d0e: 2b00 cmp r3, #0 8000d10: d0ef beq.n 8000cf2 8000d12: e01b b.n 8000d4c } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8000d14: 4a55 ldr r2, [pc, #340] ; (8000e6c ) 8000d16: 4b55 ldr r3, [pc, #340] ; (8000e6c ) 8000d18: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8000d1c: f023 0301 bic.w r3, r3, #1 8000d20: f8c2 3094 str.w r3, [r2, #148] ; 0x94 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8000d24: f7ff fae8 bl 80002f8 8000d28: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till LSI is disabled */ while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != RESET) 8000d2a: e008 b.n 8000d3e { if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) 8000d2c: f7ff fae4 bl 80002f8 8000d30: 4602 mov r2, r0 8000d32: 6abb ldr r3, [r7, #40] ; 0x28 8000d34: 1ad3 subs r3, r2, r3 8000d36: 2b02 cmp r3, #2 8000d38: d901 bls.n 8000d3e { return HAL_TIMEOUT; 8000d3a: 2303 movs r3, #3 8000d3c: e190 b.n 8001060 /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSI is disabled */ while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != RESET) 8000d3e: 4b4b ldr r3, [pc, #300] ; (8000e6c ) 8000d40: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8000d44: f003 0302 and.w r3, r3, #2 8000d48: 2b00 cmp r3, #0 8000d4a: d1ef bne.n 8000d2c } } } } /*------------------------------ LSE Configuration -------------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8000d4c: 687b ldr r3, [r7, #4] 8000d4e: 681b ldr r3, [r3, #0] 8000d50: f003 0304 and.w r3, r3, #4 8000d54: 2b00 cmp r3, #0 8000d56: f000 80a9 beq.w 8000eac { FlagStatus pwrclkchanged = RESET; 8000d5a: 2300 movs r3, #0 8000d5c: f887 302f strb.w r3, [r7, #47] ; 0x2f /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* Update LSE configuration in Backup Domain control register */ /* Requires to enable write access to Backup Domain of necessary */ if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN)) 8000d60: 4b42 ldr r3, [pc, #264] ; (8000e6c ) 8000d62: 6d9b ldr r3, [r3, #88] ; 0x58 8000d64: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000d68: 2b00 cmp r3, #0 8000d6a: d10e bne.n 8000d8a { __HAL_RCC_PWR_CLK_ENABLE(); 8000d6c: 4a3f ldr r2, [pc, #252] ; (8000e6c ) 8000d6e: 4b3f ldr r3, [pc, #252] ; (8000e6c ) 8000d70: 6d9b ldr r3, [r3, #88] ; 0x58 8000d72: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8000d76: 6593 str r3, [r2, #88] ; 0x58 8000d78: 4b3c ldr r3, [pc, #240] ; (8000e6c ) 8000d7a: 6d9b ldr r3, [r3, #88] ; 0x58 8000d7c: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8000d80: 60fb str r3, [r7, #12] 8000d82: 68fb ldr r3, [r7, #12] pwrclkchanged = SET; 8000d84: 2301 movs r3, #1 8000d86: f887 302f strb.w r3, [r7, #47] ; 0x2f } if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8000d8a: 4b39 ldr r3, [pc, #228] ; (8000e70 ) 8000d8c: 681b ldr r3, [r3, #0] 8000d8e: f403 7380 and.w r3, r3, #256 ; 0x100 8000d92: 2b00 cmp r3, #0 8000d94: d118 bne.n 8000dc8 { /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8000d96: 4a36 ldr r2, [pc, #216] ; (8000e70 ) 8000d98: 4b35 ldr r3, [pc, #212] ; (8000e70 ) 8000d9a: 681b ldr r3, [r3, #0] 8000d9c: f443 7380 orr.w r3, r3, #256 ; 0x100 8000da0: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8000da2: f7ff faa9 bl 80002f8 8000da6: 62b8 str r0, [r7, #40] ; 0x28 while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8000da8: e008 b.n 8000dbc { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 8000daa: f7ff faa5 bl 80002f8 8000dae: 4602 mov r2, r0 8000db0: 6abb ldr r3, [r7, #40] ; 0x28 8000db2: 1ad3 subs r3, r2, r3 8000db4: 2b02 cmp r3, #2 8000db6: d901 bls.n 8000dbc { return HAL_TIMEOUT; 8000db8: 2303 movs r3, #3 8000dba: e151 b.n 8001060 SET_BIT(PWR->CR1, PWR_CR1_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) 8000dbc: 4b2c ldr r3, [pc, #176] ; (8000e70 ) 8000dbe: 681b ldr r3, [r3, #0] 8000dc0: f403 7380 and.w r3, r3, #256 ; 0x100 8000dc4: 2b00 cmp r3, #0 8000dc6: d0f0 beq.n 8000daa } } } /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8000dc8: 687b ldr r3, [r7, #4] 8000dca: 689b ldr r3, [r3, #8] 8000dcc: 2b01 cmp r3, #1 8000dce: d108 bne.n 8000de2 8000dd0: 4a26 ldr r2, [pc, #152] ; (8000e6c ) 8000dd2: 4b26 ldr r3, [pc, #152] ; (8000e6c ) 8000dd4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8000dd8: f043 0301 orr.w r3, r3, #1 8000ddc: f8c2 3090 str.w r3, [r2, #144] ; 0x90 8000de0: e024 b.n 8000e2c 8000de2: 687b ldr r3, [r7, #4] 8000de4: 689b ldr r3, [r3, #8] 8000de6: 2b05 cmp r3, #5 8000de8: d110 bne.n 8000e0c 8000dea: 4a20 ldr r2, [pc, #128] ; (8000e6c ) 8000dec: 4b1f ldr r3, [pc, #124] ; (8000e6c ) 8000dee: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8000df2: f043 0304 orr.w r3, r3, #4 8000df6: f8c2 3090 str.w r3, [r2, #144] ; 0x90 8000dfa: 4a1c ldr r2, [pc, #112] ; (8000e6c ) 8000dfc: 4b1b ldr r3, [pc, #108] ; (8000e6c ) 8000dfe: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8000e02: f043 0301 orr.w r3, r3, #1 8000e06: f8c2 3090 str.w r3, [r2, #144] ; 0x90 8000e0a: e00f b.n 8000e2c 8000e0c: 4a17 ldr r2, [pc, #92] ; (8000e6c ) 8000e0e: 4b17 ldr r3, [pc, #92] ; (8000e6c ) 8000e10: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8000e14: f023 0301 bic.w r3, r3, #1 8000e18: f8c2 3090 str.w r3, [r2, #144] ; 0x90 8000e1c: 4a13 ldr r2, [pc, #76] ; (8000e6c ) 8000e1e: 4b13 ldr r3, [pc, #76] ; (8000e6c ) 8000e20: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8000e24: f023 0304 bic.w r3, r3, #4 8000e28: f8c2 3090 str.w r3, [r2, #144] ; 0x90 /* Check the LSE State */ if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8000e2c: 687b ldr r3, [r7, #4] 8000e2e: 689b ldr r3, [r3, #8] 8000e30: 2b00 cmp r3, #0 8000e32: d016 beq.n 8000e62 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8000e34: f7ff fa60 bl 80002f8 8000e38: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) 8000e3a: e00a b.n 8000e52 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8000e3c: f7ff fa5c bl 80002f8 8000e40: 4602 mov r2, r0 8000e42: 6abb ldr r3, [r7, #40] ; 0x28 8000e44: 1ad3 subs r3, r2, r3 8000e46: f241 3288 movw r2, #5000 ; 0x1388 8000e4a: 4293 cmp r3, r2 8000e4c: d901 bls.n 8000e52 { return HAL_TIMEOUT; 8000e4e: 2303 movs r3, #3 8000e50: e106 b.n 8001060 { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) 8000e52: 4b06 ldr r3, [pc, #24] ; (8000e6c ) 8000e54: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8000e58: f003 0302 and.w r3, r3, #2 8000e5c: 2b00 cmp r3, #0 8000e5e: d0ed beq.n 8000e3c 8000e60: e01a b.n 8000e98 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8000e62: f7ff fa49 bl 80002f8 8000e66: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till LSE is disabled */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != RESET) 8000e68: e00f b.n 8000e8a 8000e6a: bf00 nop 8000e6c: 40021000 .word 0x40021000 8000e70: 40007000 .word 0x40007000 { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8000e74: f7ff fa40 bl 80002f8 8000e78: 4602 mov r2, r0 8000e7a: 6abb ldr r3, [r7, #40] ; 0x28 8000e7c: 1ad3 subs r3, r2, r3 8000e7e: f241 3288 movw r2, #5000 ; 0x1388 8000e82: 4293 cmp r3, r2 8000e84: d901 bls.n 8000e8a { return HAL_TIMEOUT; 8000e86: 2303 movs r3, #3 8000e88: e0ea b.n 8001060 { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSE is disabled */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != RESET) 8000e8a: 4b77 ldr r3, [pc, #476] ; (8001068 ) 8000e8c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8000e90: f003 0302 and.w r3, r3, #2 8000e94: 2b00 cmp r3, #0 8000e96: d1ed bne.n 8000e74 } } } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) 8000e98: f897 302f ldrb.w r3, [r7, #47] ; 0x2f 8000e9c: 2b01 cmp r3, #1 8000e9e: d105 bne.n 8000eac { __HAL_RCC_PWR_CLK_DISABLE(); 8000ea0: 4a71 ldr r2, [pc, #452] ; (8001068 ) 8000ea2: 4b71 ldr r3, [pc, #452] ; (8001068 ) 8000ea4: 6d9b ldr r3, [r3, #88] ; 0x58 8000ea6: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8000eaa: 6593 str r3, [r2, #88] ; 0x58 } } #if defined(RCC_HSI48_SUPPORT) /*------------------------------ HSI48 Configuration -----------------------*/ if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) 8000eac: 687b ldr r3, [r7, #4] 8000eae: 681b ldr r3, [r3, #0] 8000eb0: f003 0320 and.w r3, r3, #32 8000eb4: 2b00 cmp r3, #0 8000eb6: d03c beq.n 8000f32 { /* Check the parameters */ assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State)); /* Check the LSI State */ if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) 8000eb8: 687b ldr r3, [r7, #4] 8000eba: 6a5b ldr r3, [r3, #36] ; 0x24 8000ebc: 2b00 cmp r3, #0 8000ebe: d01c beq.n 8000efa { /* Enable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_ENABLE(); 8000ec0: 4a69 ldr r2, [pc, #420] ; (8001068 ) 8000ec2: 4b69 ldr r3, [pc, #420] ; (8001068 ) 8000ec4: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 8000ec8: f043 0301 orr.w r3, r3, #1 8000ecc: f8c2 3098 str.w r3, [r2, #152] ; 0x98 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8000ed0: f7ff fa12 bl 80002f8 8000ed4: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till HSI48 is ready */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RESET) 8000ed6: e008 b.n 8000eea { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8000ed8: f7ff fa0e bl 80002f8 8000edc: 4602 mov r2, r0 8000ede: 6abb ldr r3, [r7, #40] ; 0x28 8000ee0: 1ad3 subs r3, r2, r3 8000ee2: 2b02 cmp r3, #2 8000ee4: d901 bls.n 8000eea { return HAL_TIMEOUT; 8000ee6: 2303 movs r3, #3 8000ee8: e0ba b.n 8001060 /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI48 is ready */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == RESET) 8000eea: 4b5f ldr r3, [pc, #380] ; (8001068 ) 8000eec: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 8000ef0: f003 0302 and.w r3, r3, #2 8000ef4: 2b00 cmp r3, #0 8000ef6: d0ef beq.n 8000ed8 8000ef8: e01b b.n 8000f32 } } else { /* Disable the Internal Low Speed oscillator (HSI48). */ __HAL_RCC_HSI48_DISABLE(); 8000efa: 4a5b ldr r2, [pc, #364] ; (8001068 ) 8000efc: 4b5a ldr r3, [pc, #360] ; (8001068 ) 8000efe: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 8000f02: f023 0301 bic.w r3, r3, #1 8000f06: f8c2 3098 str.w r3, [r2, #152] ; 0x98 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8000f0a: f7ff f9f5 bl 80002f8 8000f0e: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till HSI48 is disabled */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != RESET) 8000f10: e008 b.n 8000f24 { if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) 8000f12: f7ff f9f1 bl 80002f8 8000f16: 4602 mov r2, r0 8000f18: 6abb ldr r3, [r7, #40] ; 0x28 8000f1a: 1ad3 subs r3, r2, r3 8000f1c: 2b02 cmp r3, #2 8000f1e: d901 bls.n 8000f24 { return HAL_TIMEOUT; 8000f20: 2303 movs r3, #3 8000f22: e09d b.n 8001060 /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till HSI48 is disabled */ while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != RESET) 8000f24: 4b50 ldr r3, [pc, #320] ; (8001068 ) 8000f26: f8d3 3098 ldr.w r3, [r3, #152] ; 0x98 8000f2a: f003 0302 and.w r3, r3, #2 8000f2e: 2b00 cmp r3, #0 8000f30: d1ef bne.n 8000f12 #endif /* RCC_HSI48_SUPPORT */ /*-------------------------------- PLL Configuration -----------------------*/ /* Check the parameters */ assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) 8000f32: 687b ldr r3, [r7, #4] 8000f34: 6a9b ldr r3, [r3, #40] ; 0x28 8000f36: 2b00 cmp r3, #0 8000f38: f000 8091 beq.w 800105e { /* Check if the PLL is used as system clock or not */ if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 8000f3c: 4b4a ldr r3, [pc, #296] ; (8001068 ) 8000f3e: 689b ldr r3, [r3, #8] 8000f40: f003 030c and.w r3, r3, #12 8000f44: 2b0c cmp r3, #12 8000f46: f000 8088 beq.w 800105a { if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) 8000f4a: 687b ldr r3, [r7, #4] 8000f4c: 6a9b ldr r3, [r3, #40] ; 0x28 8000f4e: 2b02 cmp r3, #2 8000f50: d155 bne.n 8000ffe assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8000f52: 4a45 ldr r2, [pc, #276] ; (8001068 ) 8000f54: 4b44 ldr r3, [pc, #272] ; (8001068 ) 8000f56: 681b ldr r3, [r3, #0] 8000f58: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8000f5c: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8000f5e: f7ff f9cb bl 80002f8 8000f62: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till PLL is ready */ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 8000f64: e008 b.n 8000f78 { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8000f66: f7ff f9c7 bl 80002f8 8000f6a: 4602 mov r2, r0 8000f6c: 6abb ldr r3, [r7, #40] ; 0x28 8000f6e: 1ad3 subs r3, r2, r3 8000f70: 2b02 cmp r3, #2 8000f72: d901 bls.n 8000f78 { return HAL_TIMEOUT; 8000f74: 2303 movs r3, #3 8000f76: e073 b.n 8001060 /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is ready */ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 8000f78: 4b3b ldr r3, [pc, #236] ; (8001068 ) 8000f7a: 681b ldr r3, [r3, #0] 8000f7c: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000f80: 2b00 cmp r3, #0 8000f82: d1f0 bne.n 8000f66 return HAL_TIMEOUT; } } /* Configure the main PLL clock source, multiplication and division factors. */ __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, 8000f84: 4938 ldr r1, [pc, #224] ; (8001068 ) 8000f86: 687b ldr r3, [r7, #4] 8000f88: 6b1b ldr r3, [r3, #48] ; 0x30 8000f8a: 3b01 subs r3, #1 8000f8c: 011a lsls r2, r3, #4 8000f8e: 687b ldr r3, [r7, #4] 8000f90: 6b5b ldr r3, [r3, #52] ; 0x34 8000f92: 021b lsls r3, r3, #8 8000f94: 431a orrs r2, r3 8000f96: 687b ldr r3, [r7, #4] 8000f98: 6adb ldr r3, [r3, #44] ; 0x2c 8000f9a: 431a orrs r2, r3 8000f9c: 687b ldr r3, [r7, #4] 8000f9e: 6bdb ldr r3, [r3, #60] ; 0x3c 8000fa0: 085b lsrs r3, r3, #1 8000fa2: 3b01 subs r3, #1 8000fa4: 055b lsls r3, r3, #21 8000fa6: 431a orrs r2, r3 8000fa8: 687b ldr r3, [r7, #4] 8000faa: 6c1b ldr r3, [r3, #64] ; 0x40 8000fac: 085b lsrs r3, r3, #1 8000fae: 3b01 subs r3, #1 8000fb0: 065b lsls r3, r3, #25 8000fb2: 431a orrs r2, r3 8000fb4: 687b ldr r3, [r7, #4] 8000fb6: 6b9b ldr r3, [r3, #56] ; 0x38 8000fb8: 06db lsls r3, r3, #27 8000fba: 4313 orrs r3, r2 8000fbc: 60cb str r3, [r1, #12] RCC_OscInitStruct->PLL.PLLP, RCC_OscInitStruct->PLL.PLLQ, RCC_OscInitStruct->PLL.PLLR); /* Enable the main PLL. */ __HAL_RCC_PLL_ENABLE(); 8000fbe: 4a2a ldr r2, [pc, #168] ; (8001068 ) 8000fc0: 4b29 ldr r3, [pc, #164] ; (8001068 ) 8000fc2: 681b ldr r3, [r3, #0] 8000fc4: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8000fc8: 6013 str r3, [r2, #0] /* Enable PLL System Clock output. */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); 8000fca: 4a27 ldr r2, [pc, #156] ; (8001068 ) 8000fcc: 4b26 ldr r3, [pc, #152] ; (8001068 ) 8000fce: 68db ldr r3, [r3, #12] 8000fd0: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 8000fd4: 60d3 str r3, [r2, #12] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8000fd6: f7ff f98f bl 80002f8 8000fda: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till PLL is ready */ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) 8000fdc: e008 b.n 8000ff0 { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 8000fde: f7ff f98b bl 80002f8 8000fe2: 4602 mov r2, r0 8000fe4: 6abb ldr r3, [r7, #40] ; 0x28 8000fe6: 1ad3 subs r3, r2, r3 8000fe8: 2b02 cmp r3, #2 8000fea: d901 bls.n 8000ff0 { return HAL_TIMEOUT; 8000fec: 2303 movs r3, #3 8000fee: e037 b.n 8001060 /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is ready */ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) 8000ff0: 4b1d ldr r3, [pc, #116] ; (8001068 ) 8000ff2: 681b ldr r3, [r3, #0] 8000ff4: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8000ff8: 2b00 cmp r3, #0 8000ffa: d0f0 beq.n 8000fde 8000ffc: e02f b.n 800105e } } else { /* Disable the main PLL. */ __HAL_RCC_PLL_DISABLE(); 8000ffe: 4a1a ldr r2, [pc, #104] ; (8001068 ) 8001000: 4b19 ldr r3, [pc, #100] ; (8001068 ) 8001002: 681b ldr r3, [r3, #0] 8001004: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 8001008: 6013 str r3, [r2, #0] /* Disable all PLL outputs to save power if no PLLs on */ if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) 800100a: 4b17 ldr r3, [pc, #92] ; (8001068 ) 800100c: 681b ldr r3, [r3, #0] 800100e: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8001012: 2b00 cmp r3, #0 8001014: d105 bne.n 8001022 && (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == RESET) #endif /* RCC_PLLSAI2_SUPPORT */ ) { MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, RCC_PLLSOURCE_NONE); 8001016: 4a14 ldr r2, [pc, #80] ; (8001068 ) 8001018: 4b13 ldr r3, [pc, #76] ; (8001068 ) 800101a: 68db ldr r3, [r3, #12] 800101c: f023 0303 bic.w r3, r3, #3 8001020: 60d3 str r3, [r2, #12] } #if defined(RCC_PLLSAI2_SUPPORT) __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK); #else __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI2CLK); 8001022: 4a11 ldr r2, [pc, #68] ; (8001068 ) 8001024: 4b10 ldr r3, [pc, #64] ; (8001068 ) 8001026: 68db ldr r3, [r3, #12] 8001028: f023 7388 bic.w r3, r3, #17825792 ; 0x1100000 800102c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 8001030: 60d3 str r3, [r2, #12] #endif /* RCC_PLLSAI2_SUPPORT */ /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001032: f7ff f961 bl 80002f8 8001036: 62b8 str r0, [r7, #40] ; 0x28 /* Wait till PLL is disabled */ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 8001038: e008 b.n 800104c { if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) 800103a: f7ff f95d bl 80002f8 800103e: 4602 mov r2, r0 8001040: 6abb ldr r3, [r7, #40] ; 0x28 8001042: 1ad3 subs r3, r2, r3 8001044: 2b02 cmp r3, #2 8001046: d901 bls.n 800104c { return HAL_TIMEOUT; 8001048: 2303 movs r3, #3 800104a: e009 b.n 8001060 /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLL is disabled */ while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET) 800104c: 4b06 ldr r3, [pc, #24] ; (8001068 ) 800104e: 681b ldr r3, [r3, #0] 8001050: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 8001054: 2b00 cmp r3, #0 8001056: d1f0 bne.n 800103a 8001058: e001 b.n 800105e } } } else { return HAL_ERROR; 800105a: 2301 movs r3, #1 800105c: e000 b.n 8001060 } } return HAL_OK; 800105e: 2300 movs r3, #0 } 8001060: 4618 mov r0, r3 8001062: 3730 adds r7, #48 ; 0x30 8001064: 46bd mov sp, r7 8001066: bd80 pop {r7, pc} 8001068: 40021000 .word 0x40021000 0800106c : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 800106c: b580 push {r7, lr} 800106e: b086 sub sp, #24 8001070: af00 add r7, sp, #0 8001072: 6078 str r0, [r7, #4] 8001074: 6039 str r1, [r7, #0] uint32_t tickstart = 0; 8001076: 2300 movs r3, #0 8001078: 617b str r3, [r7, #20] /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the CPU clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY)) 800107a: 4b8a ldr r3, [pc, #552] ; (80012a4 ) 800107c: 681b ldr r3, [r3, #0] 800107e: f003 0207 and.w r2, r3, #7 8001082: 683b ldr r3, [r7, #0] 8001084: 429a cmp r2, r3 8001086: d210 bcs.n 80010aa { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001088: 4986 ldr r1, [pc, #536] ; (80012a4 ) 800108a: 4b86 ldr r3, [pc, #536] ; (80012a4 ) 800108c: 681b ldr r3, [r3, #0] 800108e: f023 0207 bic.w r2, r3, #7 8001092: 683b ldr r3, [r7, #0] 8001094: 4313 orrs r3, r2 8001096: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8001098: 4b82 ldr r3, [pc, #520] ; (80012a4 ) 800109a: 681b ldr r3, [r3, #0] 800109c: f003 0207 and.w r2, r3, #7 80010a0: 683b ldr r3, [r7, #0] 80010a2: 429a cmp r2, r3 80010a4: d001 beq.n 80010aa { return HAL_ERROR; 80010a6: 2301 movs r3, #1 80010a8: e0f7 b.n 800129a } } /*-------------------------- HCLK Configuration --------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 80010aa: 687b ldr r3, [r7, #4] 80010ac: 681b ldr r3, [r3, #0] 80010ae: f003 0302 and.w r3, r3, #2 80010b2: 2b00 cmp r3, #0 80010b4: d008 beq.n 80010c8 { assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 80010b6: 497c ldr r1, [pc, #496] ; (80012a8 ) 80010b8: 4b7b ldr r3, [pc, #492] ; (80012a8 ) 80010ba: 689b ldr r3, [r3, #8] 80010bc: f023 02f0 bic.w r2, r3, #240 ; 0xf0 80010c0: 687b ldr r3, [r7, #4] 80010c2: 689b ldr r3, [r3, #8] 80010c4: 4313 orrs r3, r2 80010c6: 608b str r3, [r1, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 80010c8: 687b ldr r3, [r7, #4] 80010ca: 681b ldr r3, [r3, #0] 80010cc: f003 0301 and.w r3, r3, #1 80010d0: 2b00 cmp r3, #0 80010d2: f000 808f beq.w 80011f4 { assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); /* HSE is selected as System Clock Source */ if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 80010d6: 687b ldr r3, [r7, #4] 80010d8: 685b ldr r3, [r3, #4] 80010da: 2b02 cmp r3, #2 80010dc: d107 bne.n 80010ee { /* Check the HSE ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == RESET) 80010de: 4b72 ldr r3, [pc, #456] ; (80012a8 ) 80010e0: 681b ldr r3, [r3, #0] 80010e2: f403 3300 and.w r3, r3, #131072 ; 0x20000 80010e6: 2b00 cmp r3, #0 80010e8: d121 bne.n 800112e { return HAL_ERROR; 80010ea: 2301 movs r3, #1 80010ec: e0d5 b.n 800129a } } /* PLL is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 80010ee: 687b ldr r3, [r7, #4] 80010f0: 685b ldr r3, [r3, #4] 80010f2: 2b03 cmp r3, #3 80010f4: d107 bne.n 8001106 { /* Check the PLL ready flag */ if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == RESET) 80010f6: 4b6c ldr r3, [pc, #432] ; (80012a8 ) 80010f8: 681b ldr r3, [r3, #0] 80010fa: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 80010fe: 2b00 cmp r3, #0 8001100: d115 bne.n 800112e { return HAL_ERROR; 8001102: 2301 movs r3, #1 8001104: e0c9 b.n 800129a } } /* MSI is selected as System Clock Source */ else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) 8001106: 687b ldr r3, [r7, #4] 8001108: 685b ldr r3, [r3, #4] 800110a: 2b00 cmp r3, #0 800110c: d107 bne.n 800111e { /* Check the MSI ready flag */ if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == RESET) 800110e: 4b66 ldr r3, [pc, #408] ; (80012a8 ) 8001110: 681b ldr r3, [r3, #0] 8001112: f003 0302 and.w r3, r3, #2 8001116: 2b00 cmp r3, #0 8001118: d109 bne.n 800112e { return HAL_ERROR; 800111a: 2301 movs r3, #1 800111c: e0bd b.n 800129a } /* HSI is selected as System Clock Source */ else { /* Check the HSI ready flag */ if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET) 800111e: 4b62 ldr r3, [pc, #392] ; (80012a8 ) 8001120: 681b ldr r3, [r3, #0] 8001122: f403 6380 and.w r3, r3, #1024 ; 0x400 8001126: 2b00 cmp r3, #0 8001128: d101 bne.n 800112e { return HAL_ERROR; 800112a: 2301 movs r3, #1 800112c: e0b5 b.n 800129a } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 800112e: 495e ldr r1, [pc, #376] ; (80012a8 ) 8001130: 4b5d ldr r3, [pc, #372] ; (80012a8 ) 8001132: 689b ldr r3, [r3, #8] 8001134: f023 0203 bic.w r2, r3, #3 8001138: 687b ldr r3, [r7, #4] 800113a: 685b ldr r3, [r3, #4] 800113c: 4313 orrs r3, r2 800113e: 608b str r3, [r1, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001140: f7ff f8da bl 80002f8 8001144: 6178 str r0, [r7, #20] if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8001146: 687b ldr r3, [r7, #4] 8001148: 685b ldr r3, [r3, #4] 800114a: 2b02 cmp r3, #2 800114c: d112 bne.n 8001174 { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) 800114e: e00a b.n 8001166 { if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 8001150: f7ff f8d2 bl 80002f8 8001154: 4602 mov r2, r0 8001156: 697b ldr r3, [r7, #20] 8001158: 1ad3 subs r3, r2, r3 800115a: f241 3288 movw r2, #5000 ; 0x1388 800115e: 4293 cmp r3, r2 8001160: d901 bls.n 8001166 { return HAL_TIMEOUT; 8001162: 2303 movs r3, #3 8001164: e099 b.n 800129a /* Get Start Tick*/ tickstart = HAL_GetTick(); if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE) 8001166: 4b50 ldr r3, [pc, #320] ; (80012a8 ) 8001168: 689b ldr r3, [r3, #8] 800116a: f003 030c and.w r3, r3, #12 800116e: 2b08 cmp r3, #8 8001170: d1ee bne.n 8001150 8001172: e03f b.n 80011f4 { return HAL_TIMEOUT; } } } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) 8001174: 687b ldr r3, [r7, #4] 8001176: 685b ldr r3, [r3, #4] 8001178: 2b03 cmp r3, #3 800117a: d112 bne.n 80011a2 { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 800117c: e00a b.n 8001194 { if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 800117e: f7ff f8bb bl 80002f8 8001182: 4602 mov r2, r0 8001184: 697b ldr r3, [r7, #20] 8001186: 1ad3 subs r3, r2, r3 8001188: f241 3288 movw r2, #5000 ; 0x1388 800118c: 4293 cmp r3, r2 800118e: d901 bls.n 8001194 { return HAL_TIMEOUT; 8001190: 2303 movs r3, #3 8001192: e082 b.n 800129a } } } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 8001194: 4b44 ldr r3, [pc, #272] ; (80012a8 ) 8001196: 689b ldr r3, [r3, #8] 8001198: f003 030c and.w r3, r3, #12 800119c: 2b0c cmp r3, #12 800119e: d1ee bne.n 800117e 80011a0: e028 b.n 80011f4 { return HAL_TIMEOUT; } } } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) 80011a2: 687b ldr r3, [r7, #4] 80011a4: 685b ldr r3, [r3, #4] 80011a6: 2b00 cmp r3, #0 80011a8: d112 bne.n 80011d0 { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) 80011aa: e00a b.n 80011c2 { if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80011ac: f7ff f8a4 bl 80002f8 80011b0: 4602 mov r2, r0 80011b2: 697b ldr r3, [r7, #20] 80011b4: 1ad3 subs r3, r2, r3 80011b6: f241 3288 movw r2, #5000 ; 0x1388 80011ba: 4293 cmp r3, r2 80011bc: d901 bls.n 80011c2 { return HAL_TIMEOUT; 80011be: 2303 movs r3, #3 80011c0: e06b b.n 800129a } } } else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) { while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI) 80011c2: 4b39 ldr r3, [pc, #228] ; (80012a8 ) 80011c4: 689b ldr r3, [r3, #8] 80011c6: f003 030c and.w r3, r3, #12 80011ca: 2b00 cmp r3, #0 80011cc: d1ee bne.n 80011ac 80011ce: e011 b.n 80011f4 } } } else { while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) 80011d0: e00a b.n 80011e8 { if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) 80011d2: f7ff f891 bl 80002f8 80011d6: 4602 mov r2, r0 80011d8: 697b ldr r3, [r7, #20] 80011da: 1ad3 subs r3, r2, r3 80011dc: f241 3288 movw r2, #5000 ; 0x1388 80011e0: 4293 cmp r3, r2 80011e2: d901 bls.n 80011e8 { return HAL_TIMEOUT; 80011e4: 2303 movs r3, #3 80011e6: e058 b.n 800129a } } } else { while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI) 80011e8: 4b2f ldr r3, [pc, #188] ; (80012a8 ) 80011ea: 689b ldr r3, [r3, #8] 80011ec: f003 030c and.w r3, r3, #12 80011f0: 2b04 cmp r3, #4 80011f2: d1ee bne.n 80011d2 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY)) 80011f4: 4b2b ldr r3, [pc, #172] ; (80012a4 ) 80011f6: 681b ldr r3, [r3, #0] 80011f8: f003 0207 and.w r2, r3, #7 80011fc: 683b ldr r3, [r7, #0] 80011fe: 429a cmp r2, r3 8001200: d910 bls.n 8001224 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8001202: 4928 ldr r1, [pc, #160] ; (80012a4 ) 8001204: 4b27 ldr r3, [pc, #156] ; (80012a4 ) 8001206: 681b ldr r3, [r3, #0] 8001208: f023 0207 bic.w r2, r3, #7 800120c: 683b ldr r3, [r7, #0] 800120e: 4313 orrs r3, r2 8001210: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8001212: 4b24 ldr r3, [pc, #144] ; (80012a4 ) 8001214: 681b ldr r3, [r3, #0] 8001216: f003 0207 and.w r2, r3, #7 800121a: 683b ldr r3, [r7, #0] 800121c: 429a cmp r2, r3 800121e: d001 beq.n 8001224 { return HAL_ERROR; 8001220: 2301 movs r3, #1 8001222: e03a b.n 800129a } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8001224: 687b ldr r3, [r7, #4] 8001226: 681b ldr r3, [r3, #0] 8001228: f003 0304 and.w r3, r3, #4 800122c: 2b00 cmp r3, #0 800122e: d008 beq.n 8001242 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider); 8001230: 491d ldr r1, [pc, #116] ; (80012a8 ) 8001232: 4b1d ldr r3, [pc, #116] ; (80012a8 ) 8001234: 689b ldr r3, [r3, #8] 8001236: f423 62e0 bic.w r2, r3, #1792 ; 0x700 800123a: 687b ldr r3, [r7, #4] 800123c: 68db ldr r3, [r3, #12] 800123e: 4313 orrs r3, r2 8001240: 608b str r3, [r1, #8] } /*-------------------------- PCLK2 Configuration ---------------------------*/ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) 8001242: 687b ldr r3, [r7, #4] 8001244: 681b ldr r3, [r3, #0] 8001246: f003 0308 and.w r3, r3, #8 800124a: 2b00 cmp r3, #0 800124c: d009 beq.n 8001262 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U)); 800124e: 4916 ldr r1, [pc, #88] ; (80012a8 ) 8001250: 4b15 ldr r3, [pc, #84] ; (80012a8 ) 8001252: 689b ldr r3, [r3, #8] 8001254: f423 5260 bic.w r2, r3, #14336 ; 0x3800 8001258: 687b ldr r3, [r7, #4] 800125a: 691b ldr r3, [r3, #16] 800125c: 00db lsls r3, r3, #3 800125e: 4313 orrs r3, r2 8001260: 608b str r3, [r1, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)]; 8001262: f000 f827 bl 80012b4 8001266: 4601 mov r1, r0 8001268: 4b0f ldr r3, [pc, #60] ; (80012a8 ) 800126a: 689b ldr r3, [r3, #8] 800126c: f003 02f0 and.w r2, r3, #240 ; 0xf0 8001270: 23f0 movs r3, #240 ; 0xf0 8001272: 613b str r3, [r7, #16] __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001274: 693b ldr r3, [r7, #16] 8001276: fa93 f3a3 rbit r3, r3 800127a: 60fb str r3, [r7, #12] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 800127c: 68fb ldr r3, [r7, #12] 800127e: fab3 f383 clz r3, r3 8001282: fa22 f303 lsr.w r3, r2, r3 8001286: 4a09 ldr r2, [pc, #36] ; (80012ac ) 8001288: 5cd3 ldrb r3, [r2, r3] 800128a: fa21 f303 lsr.w r3, r1, r3 800128e: 4a08 ldr r2, [pc, #32] ; (80012b0 ) 8001290: 6013 str r3, [r2, #0] /* Configure the source of time base considering new system clocks settings*/ HAL_InitTick (TICK_INT_PRIORITY); 8001292: 2000 movs r0, #0 8001294: f7ff f806 bl 80002a4 return HAL_OK; 8001298: 2300 movs r3, #0 } 800129a: 4618 mov r0, r3 800129c: 3718 adds r7, #24 800129e: 46bd mov sp, r7 80012a0: bd80 pop {r7, pc} 80012a2: bf00 nop 80012a4: 40022000 .word 0x40022000 80012a8: 40021000 .word 0x40021000 80012ac: 08002080 .word 0x08002080 80012b0: 20000000 .word 0x20000000 080012b4 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 80012b4: b480 push {r7} 80012b6: b095 sub sp, #84 ; 0x54 80012b8: af00 add r7, sp, #0 uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U; 80012ba: 2300 movs r3, #0 80012bc: 64fb str r3, [r7, #76] ; 0x4c 80012be: 2300 movs r3, #0 80012c0: 64bb str r3, [r7, #72] ; 0x48 80012c2: 2300 movs r3, #0 80012c4: 643b str r3, [r7, #64] ; 0x40 80012c6: 2302 movs r3, #2 80012c8: 63fb str r3, [r7, #60] ; 0x3c 80012ca: 2302 movs r3, #2 80012cc: 63bb str r3, [r7, #56] ; 0x38 uint32_t sysclockfreq = 0U; 80012ce: 2300 movs r3, #0 80012d0: 647b str r3, [r7, #68] ; 0x44 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) || 80012d2: 4b72 ldr r3, [pc, #456] ; (800149c ) 80012d4: 689b ldr r3, [r3, #8] 80012d6: f003 030c and.w r3, r3, #12 80012da: 2b00 cmp r3, #0 80012dc: d00b beq.n 80012f6 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI))) 80012de: 4b6f ldr r3, [pc, #444] ; (800149c ) 80012e0: 689b ldr r3, [r3, #8] 80012e2: f003 030c and.w r3, r3, #12 uint32_t HAL_RCC_GetSysClockFreq(void) { uint32_t msirange = 0U, pllvco = 0U, pllsource = 0U, pllr = 2U, pllm = 2U; uint32_t sysclockfreq = 0U; if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) || 80012e6: 2b0c cmp r3, #12 80012e8: d13d bne.n 8001366 ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_MSI))) 80012ea: 4b6c ldr r3, [pc, #432] ; (800149c ) 80012ec: 68db ldr r3, [r3, #12] 80012ee: f003 0303 and.w r3, r3, #3 80012f2: 2b01 cmp r3, #1 80012f4: d137 bne.n 8001366 { /* MSI or PLL with MSI source used as system clock source */ /* Get SYSCLK source */ if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == RESET) 80012f6: 4b69 ldr r3, [pc, #420] ; (800149c ) 80012f8: 681b ldr r3, [r3, #0] 80012fa: f003 0308 and.w r3, r3, #8 80012fe: 2b00 cmp r3, #0 8001300: d112 bne.n 8001328 { /* MSISRANGE from RCC_CSR applies */ msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> POSITION_VAL(RCC_CSR_MSISRANGE); 8001302: 4b66 ldr r3, [pc, #408] ; (800149c ) 8001304: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 8001308: f403 6270 and.w r2, r3, #3840 ; 0xf00 800130c: f44f 6370 mov.w r3, #3840 ; 0xf00 8001310: 637b str r3, [r7, #52] ; 0x34 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001312: 6b7b ldr r3, [r7, #52] ; 0x34 8001314: fa93 f3a3 rbit r3, r3 8001318: 633b str r3, [r7, #48] ; 0x30 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 800131a: 6b3b ldr r3, [r7, #48] ; 0x30 800131c: fab3 f383 clz r3, r3 8001320: fa22 f303 lsr.w r3, r2, r3 8001324: 64fb str r3, [r7, #76] ; 0x4c 8001326: e00f b.n 8001348 } else { /* MSIRANGE from RCC_CR applies */ msirange = (RCC->CR & RCC_CR_MSIRANGE) >> POSITION_VAL(RCC_CR_MSIRANGE); 8001328: 4b5c ldr r3, [pc, #368] ; (800149c ) 800132a: 681b ldr r3, [r3, #0] 800132c: f003 02f0 and.w r2, r3, #240 ; 0xf0 8001330: 23f0 movs r3, #240 ; 0xf0 8001332: 62fb str r3, [r7, #44] ; 0x2c __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001334: 6afb ldr r3, [r7, #44] ; 0x2c 8001336: fa93 f3a3 rbit r3, r3 800133a: 62bb str r3, [r7, #40] ; 0x28 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 800133c: 6abb ldr r3, [r7, #40] ; 0x28 800133e: fab3 f383 clz r3, r3 8001342: fa22 f303 lsr.w r3, r2, r3 8001346: 64fb str r3, [r7, #76] ; 0x4c } /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; 8001348: 4a55 ldr r2, [pc, #340] ; (80014a0 ) 800134a: 6cfb ldr r3, [r7, #76] ; 0x4c 800134c: f852 3023 ldr.w r3, [r2, r3, lsl #2] 8001350: 64fb str r3, [r7, #76] ; 0x4c if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) 8001352: 4b52 ldr r3, [pc, #328] ; (800149c ) 8001354: 689b ldr r3, [r3, #8] 8001356: f003 030c and.w r3, r3, #12 800135a: 2b00 cmp r3, #0 800135c: d102 bne.n 8001364 { /* MSI used as system clock source */ sysclockfreq = msirange; 800135e: 6cfb ldr r3, [r7, #76] ; 0x4c 8001360: 647b str r3, [r7, #68] ; 0x44 msirange = (RCC->CR & RCC_CR_MSIRANGE) >> POSITION_VAL(RCC_CR_MSIRANGE); } /*MSI frequency range in HZ*/ msirange = MSIRangeTable[msirange]; if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI) 8001362: e011 b.n 8001388 8001364: e010 b.n 8001388 { /* MSI used as system clock source */ sysclockfreq = msirange; } } else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 8001366: 4b4d ldr r3, [pc, #308] ; (800149c ) 8001368: 689b ldr r3, [r3, #8] 800136a: f003 030c and.w r3, r3, #12 800136e: 2b04 cmp r3, #4 8001370: d102 bne.n 8001378 { /* HSI used as system clock source */ sysclockfreq = HSI_VALUE; 8001372: 4b4c ldr r3, [pc, #304] ; (80014a4 ) 8001374: 647b str r3, [r7, #68] ; 0x44 8001376: e007 b.n 8001388 } else if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 8001378: 4b48 ldr r3, [pc, #288] ; (800149c ) 800137a: 689b ldr r3, [r3, #8] 800137c: f003 030c and.w r3, r3, #12 8001380: 2b08 cmp r3, #8 8001382: d101 bne.n 8001388 { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 8001384: 4b48 ldr r3, [pc, #288] ; (80014a8 ) 8001386: 647b str r3, [r7, #68] ; 0x44 } if(__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) 8001388: 4b44 ldr r3, [pc, #272] ; (800149c ) 800138a: 689b ldr r3, [r3, #8] 800138c: f003 030c and.w r3, r3, #12 8001390: 2b0c cmp r3, #12 8001392: d17b bne.n 800148c /* PLL used as system clock source */ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN SYSCLK = PLL_VCO / PLLR */ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); 8001394: 4b41 ldr r3, [pc, #260] ; (800149c ) 8001396: 68db ldr r3, [r3, #12] 8001398: f003 0303 and.w r3, r3, #3 800139c: 643b str r3, [r7, #64] ; 0x40 pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U ; 800139e: 4b3f ldr r3, [pc, #252] ; (800149c ) 80013a0: 68db ldr r3, [r3, #12] 80013a2: f003 0270 and.w r2, r3, #112 ; 0x70 80013a6: 2370 movs r3, #112 ; 0x70 80013a8: 627b str r3, [r7, #36] ; 0x24 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80013aa: 6a7b ldr r3, [r7, #36] ; 0x24 80013ac: fa93 f3a3 rbit r3, r3 80013b0: 623b str r3, [r7, #32] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 80013b2: 6a3b ldr r3, [r7, #32] 80013b4: fab3 f383 clz r3, r3 80013b8: fa22 f303 lsr.w r3, r2, r3 80013bc: 3301 adds r3, #1 80013be: 63bb str r3, [r7, #56] ; 0x38 switch (pllsource) 80013c0: 6c3b ldr r3, [r7, #64] ; 0x40 80013c2: 2b02 cmp r3, #2 80013c4: d002 beq.n 80013cc 80013c6: 2b03 cmp r3, #3 80013c8: d018 beq.n 80013fc 80013ca: e02f b.n 800142c { case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); 80013cc: 4a35 ldr r2, [pc, #212] ; (80014a4 ) 80013ce: 6bbb ldr r3, [r7, #56] ; 0x38 80013d0: fbb2 f3f3 udiv r3, r2, r3 80013d4: 4a31 ldr r2, [pc, #196] ; (800149c ) 80013d6: 68d2 ldr r2, [r2, #12] 80013d8: f402 41fe and.w r1, r2, #32512 ; 0x7f00 80013dc: f44f 42fe mov.w r2, #32512 ; 0x7f00 80013e0: 61fa str r2, [r7, #28] __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80013e2: 69fa ldr r2, [r7, #28] 80013e4: fa92 f2a2 rbit r2, r2 80013e8: 61ba str r2, [r7, #24] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 80013ea: 69ba ldr r2, [r7, #24] 80013ec: fab2 f282 clz r2, r2 80013f0: fa21 f202 lsr.w r2, r1, r2 80013f4: fb02 f303 mul.w r3, r2, r3 80013f8: 64bb str r3, [r7, #72] ; 0x48 break; 80013fa: e02f b.n 800145c case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); 80013fc: 4a2a ldr r2, [pc, #168] ; (80014a8 ) 80013fe: 6bbb ldr r3, [r7, #56] ; 0x38 8001400: fbb2 f3f3 udiv r3, r2, r3 8001404: 4a25 ldr r2, [pc, #148] ; (800149c ) 8001406: 68d2 ldr r2, [r2, #12] 8001408: f402 41fe and.w r1, r2, #32512 ; 0x7f00 800140c: f44f 42fe mov.w r2, #32512 ; 0x7f00 8001410: 617a str r2, [r7, #20] __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001412: 697a ldr r2, [r7, #20] 8001414: fa92 f2a2 rbit r2, r2 8001418: 613a str r2, [r7, #16] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 800141a: 693a ldr r2, [r7, #16] 800141c: fab2 f282 clz r2, r2 8001420: fa21 f202 lsr.w r2, r1, r2 8001424: fb02 f303 mul.w r3, r2, r3 8001428: 64bb str r3, [r7, #72] ; 0x48 break; 800142a: e017 b.n 800145c case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ default: pllvco = (msirange / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)); 800142c: 6cfa ldr r2, [r7, #76] ; 0x4c 800142e: 6bbb ldr r3, [r7, #56] ; 0x38 8001430: fbb2 f3f3 udiv r3, r2, r3 8001434: 4a19 ldr r2, [pc, #100] ; (800149c ) 8001436: 68d2 ldr r2, [r2, #12] 8001438: f402 41fe and.w r1, r2, #32512 ; 0x7f00 800143c: f44f 42fe mov.w r2, #32512 ; 0x7f00 8001440: 60fa str r2, [r7, #12] __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001442: 68fa ldr r2, [r7, #12] 8001444: fa92 f2a2 rbit r2, r2 8001448: 60ba str r2, [r7, #8] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 800144a: 68ba ldr r2, [r7, #8] 800144c: fab2 f282 clz r2, r2 8001450: fa21 f202 lsr.w r2, r1, r2 8001454: fb02 f303 mul.w r3, r2, r3 8001458: 64bb str r3, [r7, #72] ; 0x48 break; 800145a: bf00 nop } pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR)) + 1U ) * 2U; 800145c: 4b0f ldr r3, [pc, #60] ; (800149c ) 800145e: 68db ldr r3, [r3, #12] 8001460: f003 62c0 and.w r2, r3, #100663296 ; 0x6000000 8001464: f04f 63c0 mov.w r3, #100663296 ; 0x6000000 8001468: 607b str r3, [r7, #4] __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 800146a: 687b ldr r3, [r7, #4] 800146c: fa93 f3a3 rbit r3, r3 8001470: 603b str r3, [r7, #0] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 8001472: 683b ldr r3, [r7, #0] 8001474: fab3 f383 clz r3, r3 8001478: fa22 f303 lsr.w r3, r2, r3 800147c: 3301 adds r3, #1 800147e: 005b lsls r3, r3, #1 8001480: 63fb str r3, [r7, #60] ; 0x3c sysclockfreq = pllvco/pllr; 8001482: 6cba ldr r2, [r7, #72] ; 0x48 8001484: 6bfb ldr r3, [r7, #60] ; 0x3c 8001486: fbb2 f3f3 udiv r3, r2, r3 800148a: 647b str r3, [r7, #68] ; 0x44 } return sysclockfreq; 800148c: 6c7b ldr r3, [r7, #68] ; 0x44 } 800148e: 4618 mov r0, r3 8001490: 3754 adds r7, #84 ; 0x54 8001492: 46bd mov sp, r7 8001494: f85d 7b04 ldr.w r7, [sp], #4 8001498: 4770 bx lr 800149a: bf00 nop 800149c: 40021000 .word 0x40021000 80014a0: 08002090 .word 0x08002090 80014a4: 00f42400 .word 0x00f42400 80014a8: 007a1200 .word 0x007a1200 080014ac : * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 80014ac: b480 push {r7} 80014ae: af00 add r7, sp, #0 return SystemCoreClock; 80014b0: 4b03 ldr r3, [pc, #12] ; (80014c0 ) 80014b2: 681b ldr r3, [r3, #0] } 80014b4: 4618 mov r0, r3 80014b6: 46bd mov sp, r7 80014b8: f85d 7b04 ldr.w r7, [sp], #4 80014bc: 4770 bx lr 80014be: bf00 nop 80014c0: 20000000 .word 0x20000000 080014c4 : voltage range. * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11 * @retval HAL status */ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) { 80014c4: b580 push {r7, lr} 80014c6: b086 sub sp, #24 80014c8: af00 add r7, sp, #0 80014ca: 6078 str r0, [r7, #4] uint32_t vos = 0; 80014cc: 2300 movs r3, #0 80014ce: 617b str r3, [r7, #20] uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ 80014d0: 2300 movs r3, #0 80014d2: 613b str r3, [r7, #16] if(__HAL_RCC_PWR_IS_CLK_ENABLED()) 80014d4: 4b2a ldr r3, [pc, #168] ; (8001580 ) 80014d6: 6d9b ldr r3, [r3, #88] ; 0x58 80014d8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80014dc: 2b00 cmp r3, #0 80014de: d003 beq.n 80014e8 { vos = HAL_PWREx_GetVoltageRange(); 80014e0: f7ff f9a0 bl 8000824 80014e4: 6178 str r0, [r7, #20] 80014e6: e014 b.n 8001512 } else { __HAL_RCC_PWR_CLK_ENABLE(); 80014e8: 4a25 ldr r2, [pc, #148] ; (8001580 ) 80014ea: 4b25 ldr r3, [pc, #148] ; (8001580 ) 80014ec: 6d9b ldr r3, [r3, #88] ; 0x58 80014ee: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 80014f2: 6593 str r3, [r2, #88] ; 0x58 80014f4: 4b22 ldr r3, [pc, #136] ; (8001580 ) 80014f6: 6d9b ldr r3, [r3, #88] ; 0x58 80014f8: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 80014fc: 60fb str r3, [r7, #12] 80014fe: 68fb ldr r3, [r7, #12] vos = HAL_PWREx_GetVoltageRange(); 8001500: f7ff f990 bl 8000824 8001504: 6178 str r0, [r7, #20] __HAL_RCC_PWR_CLK_DISABLE(); 8001506: 4a1e ldr r2, [pc, #120] ; (8001580 ) 8001508: 4b1d ldr r3, [pc, #116] ; (8001580 ) 800150a: 6d9b ldr r3, [r3, #88] ; 0x58 800150c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8001510: 6593 str r3, [r2, #88] ; 0x58 } if(vos == PWR_REGULATOR_VOLTAGE_SCALE1) 8001512: 697b ldr r3, [r7, #20] 8001514: f5b3 7f00 cmp.w r3, #512 ; 0x200 8001518: d10b bne.n 8001532 { if(msirange > RCC_MSIRANGE_8) 800151a: 687b ldr r3, [r7, #4] 800151c: 2b80 cmp r3, #128 ; 0x80 800151e: d919 bls.n 8001554 { /* MSI > 16Mhz */ if(msirange > RCC_MSIRANGE_10) 8001520: 687b ldr r3, [r7, #4] 8001522: 2ba0 cmp r3, #160 ; 0xa0 8001524: d902 bls.n 800152c { /* MSI 48Mhz */ latency = FLASH_LATENCY_2; /* 2WS */ 8001526: 2302 movs r3, #2 8001528: 613b str r3, [r7, #16] 800152a: e013 b.n 8001554 } else { /* MSI 24Mhz or 32Mhz */ latency = FLASH_LATENCY_1; /* 1WS */ 800152c: 2301 movs r3, #1 800152e: 613b str r3, [r7, #16] 8001530: e010 b.n 8001554 } /* else MSI <= 16Mhz default FLASH_LATENCY_0 0WS */ } else { if(msirange > RCC_MSIRANGE_8) 8001532: 687b ldr r3, [r7, #4] 8001534: 2b80 cmp r3, #128 ; 0x80 8001536: d902 bls.n 800153e { /* MSI > 16Mhz */ latency = FLASH_LATENCY_3; /* 3WS */ 8001538: 2303 movs r3, #3 800153a: 613b str r3, [r7, #16] 800153c: e00a b.n 8001554 } else { if(msirange == RCC_MSIRANGE_8) 800153e: 687b ldr r3, [r7, #4] 8001540: 2b80 cmp r3, #128 ; 0x80 8001542: d102 bne.n 800154a { /* MSI 16Mhz */ latency = FLASH_LATENCY_2; /* 2WS */ 8001544: 2302 movs r3, #2 8001546: 613b str r3, [r7, #16] 8001548: e004 b.n 8001554 } else if(msirange == RCC_MSIRANGE_7) 800154a: 687b ldr r3, [r7, #4] 800154c: 2b70 cmp r3, #112 ; 0x70 800154e: d101 bne.n 8001554 { /* MSI 8Mhz */ latency = FLASH_LATENCY_1; /* 1WS */ 8001550: 2301 movs r3, #1 8001552: 613b str r3, [r7, #16] } /* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */ } } __HAL_FLASH_SET_LATENCY(latency); 8001554: 490b ldr r1, [pc, #44] ; (8001584 ) 8001556: 4b0b ldr r3, [pc, #44] ; (8001584 ) 8001558: 681b ldr r3, [r3, #0] 800155a: f023 0207 bic.w r2, r3, #7 800155e: 693b ldr r3, [r7, #16] 8001560: 4313 orrs r3, r2 8001562: 600b str r3, [r1, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by reading the FLASH_ACR register */ if((FLASH->ACR & FLASH_ACR_LATENCY) != latency) 8001564: 4b07 ldr r3, [pc, #28] ; (8001584 ) 8001566: 681b ldr r3, [r3, #0] 8001568: f003 0207 and.w r2, r3, #7 800156c: 693b ldr r3, [r7, #16] 800156e: 429a cmp r2, r3 8001570: d001 beq.n 8001576 { return HAL_ERROR; 8001572: 2301 movs r3, #1 8001574: e000 b.n 8001578 } return HAL_OK; 8001576: 2300 movs r3, #0 } 8001578: 4618 mov r0, r3 800157a: 3718 adds r7, #24 800157c: 46bd mov sp, r7 800157e: bd80 pop {r7, pc} 8001580: 40021000 .word 0x40021000 8001584: 40022000 .word 0x40022000 08001588 : * the RTC clock source: in this case the access to Backup domain is enabled. * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 8001588: b580 push {r7, lr} 800158a: b086 sub sp, #24 800158c: af00 add r7, sp, #0 800158e: 6078 str r0, [r7, #4] uint32_t tmpregister = 0; 8001590: 2300 movs r3, #0 8001592: 617b str r3, [r7, #20] uint32_t tickstart = 0U; 8001594: 2300 movs r3, #0 8001596: 60fb str r3, [r7, #12] HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8001598: 2300 movs r3, #0 800159a: 74fb strb r3, [r7, #19] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800159c: 2300 movs r3, #0 800159e: 74bb strb r3, [r7, #18] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- SAI1 clock source configuration ---------------------*/ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) 80015a0: 687b ldr r3, [r7, #4] 80015a2: 681b ldr r3, [r3, #0] 80015a4: f403 6300 and.w r3, r3, #2048 ; 0x800 80015a8: 2b00 cmp r3, #0 80015aa: d02f beq.n 800160c { /* Check the parameters */ assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection)); switch(PeriphClkInit->Sai1ClockSelection) 80015ac: 687b ldr r3, [r7, #4] 80015ae: 6bdb ldr r3, [r3, #60] ; 0x3c 80015b0: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 80015b4: d005 beq.n 80015c2 80015b6: f5b3 0f40 cmp.w r3, #12582912 ; 0xc00000 80015ba: d015 beq.n 80015e8 80015bc: 2b00 cmp r3, #0 80015be: d007 beq.n 80015d0 80015c0: e00f b.n 80015e2 case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/ /* Enable SAI Clock output generated form System PLL . */ #if defined(RCC_PLLSAI2_SUPPORT) __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK); #else __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK); 80015c2: 4aaa ldr r2, [pc, #680] ; (800186c ) 80015c4: 4ba9 ldr r3, [pc, #676] ; (800186c ) 80015c6: 68db ldr r3, [r3, #12] 80015c8: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80015cc: 60d3 str r3, [r2, #12] #endif /* RCC_PLLSAI2_SUPPORT */ /* SAI1 clock source config set later after clock selection check */ break; 80015ce: e00c b.n 80015ea case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/ /* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE); 80015d0: 687b ldr r3, [r7, #4] 80015d2: 3304 adds r3, #4 80015d4: 4618 mov r0, r3 80015d6: 2100 movs r1, #0 80015d8: f000 f9c8 bl 800196c 80015dc: 4603 mov r3, r0 80015de: 74fb strb r3, [r7, #19] /* SAI1 clock source config set later after clock selection check */ break; 80015e0: e003 b.n 80015ea case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ /* SAI1 clock source config set later after clock selection check */ break; default: ret = HAL_ERROR; 80015e2: 2301 movs r3, #1 80015e4: 74fb strb r3, [r7, #19] break; 80015e6: e000 b.n 80015ea #endif /* RCC_PLLSAI2_SUPPORT */ case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ /* SAI1 clock source config set later after clock selection check */ break; 80015e8: bf00 nop default: ret = HAL_ERROR; break; } if(ret == HAL_OK) 80015ea: 7cfb ldrb r3, [r7, #19] 80015ec: 2b00 cmp r3, #0 80015ee: d10b bne.n 8001608 { /* Set the source of SAI1 clock*/ __HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection); 80015f0: 499e ldr r1, [pc, #632] ; (800186c ) 80015f2: 4b9e ldr r3, [pc, #632] ; (800186c ) 80015f4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80015f8: f423 0240 bic.w r2, r3, #12582912 ; 0xc00000 80015fc: 687b ldr r3, [r7, #4] 80015fe: 6bdb ldr r3, [r3, #60] ; 0x3c 8001600: 4313 orrs r3, r2 8001602: f8c1 3088 str.w r3, [r1, #136] ; 0x88 8001606: e001 b.n 800160c } else { /* set overall return value */ status = ret; 8001608: 7cfb ldrb r3, [r7, #19] 800160a: 74bb strb r3, [r7, #18] } } #endif /* SAI2 */ /*-------------------------- RTC clock source configuration ----------------------*/ if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 800160c: 687b ldr r3, [r7, #4] 800160e: 681b ldr r3, [r3, #0] 8001610: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001614: 2b00 cmp r3, #0 8001616: f000 8094 beq.w 8001742 { FlagStatus pwrclkchanged = RESET; 800161a: 2300 movs r3, #0 800161c: 747b strb r3, [r7, #17] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if(__HAL_RCC_PWR_IS_CLK_DISABLED()) 800161e: 4b93 ldr r3, [pc, #588] ; (800186c ) 8001620: 6d9b ldr r3, [r3, #88] ; 0x58 8001622: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001626: 2b00 cmp r3, #0 8001628: d10d bne.n 8001646 { __HAL_RCC_PWR_CLK_ENABLE(); 800162a: 4a90 ldr r2, [pc, #576] ; (800186c ) 800162c: 4b8f ldr r3, [pc, #572] ; (800186c ) 800162e: 6d9b ldr r3, [r3, #88] ; 0x58 8001630: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8001634: 6593 str r3, [r2, #88] ; 0x58 8001636: 4b8d ldr r3, [pc, #564] ; (800186c ) 8001638: 6d9b ldr r3, [r3, #88] ; 0x58 800163a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 800163e: 60bb str r3, [r7, #8] 8001640: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 8001642: 2301 movs r3, #1 8001644: 747b strb r3, [r7, #17] } /* Enable write access to Backup domain */ SET_BIT(PWR->CR1, PWR_CR1_DBP); 8001646: 4a8a ldr r2, [pc, #552] ; (8001870 ) 8001648: 4b89 ldr r3, [pc, #548] ; (8001870 ) 800164a: 681b ldr r3, [r3, #0] 800164c: f443 7380 orr.w r3, r3, #256 ; 0x100 8001650: 6013 str r3, [r2, #0] /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); 8001652: f7fe fe51 bl 80002f8 8001656: 60f8 str r0, [r7, #12] while((PWR->CR1 & PWR_CR1_DBP) == RESET) 8001658: e009 b.n 800166e { if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) 800165a: f7fe fe4d bl 80002f8 800165e: 4602 mov r2, r0 8001660: 68fb ldr r3, [r7, #12] 8001662: 1ad3 subs r3, r2, r3 8001664: 2b02 cmp r3, #2 8001666: d902 bls.n 800166e { ret = HAL_TIMEOUT; 8001668: 2303 movs r3, #3 800166a: 74fb strb r3, [r7, #19] break; 800166c: e005 b.n 800167a SET_BIT(PWR->CR1, PWR_CR1_DBP); /* Wait for Backup domain Write protection disable */ tickstart = HAL_GetTick(); while((PWR->CR1 & PWR_CR1_DBP) == RESET) 800166e: 4b80 ldr r3, [pc, #512] ; (8001870 ) 8001670: 681b ldr r3, [r3, #0] 8001672: f403 7380 and.w r3, r3, #256 ; 0x100 8001676: 2b00 cmp r3, #0 8001678: d0ef beq.n 800165a ret = HAL_TIMEOUT; break; } } if(ret == HAL_OK) 800167a: 7cfb ldrb r3, [r7, #19] 800167c: 2b00 cmp r3, #0 800167e: d155 bne.n 800172c { /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); 8001680: 4b7a ldr r3, [pc, #488] ; (800186c ) 8001682: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8001686: f403 7340 and.w r3, r3, #768 ; 0x300 800168a: 617b str r3, [r7, #20] if((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != PeriphClkInit->RTCClockSelection)) 800168c: 697b ldr r3, [r7, #20] 800168e: 2b00 cmp r3, #0 8001690: d01e beq.n 80016d0 8001692: 687b ldr r3, [r7, #4] 8001694: 6d1a ldr r2, [r3, #80] ; 0x50 8001696: 697b ldr r3, [r7, #20] 8001698: 429a cmp r2, r3 800169a: d019 beq.n 80016d0 { /* Store the content of BDCR register before the reset of Backup Domain */ tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); 800169c: 4b73 ldr r3, [pc, #460] ; (800186c ) 800169e: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 80016a2: f423 7340 bic.w r3, r3, #768 ; 0x300 80016a6: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the Backup Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80016a8: 4a70 ldr r2, [pc, #448] ; (800186c ) 80016aa: 4b70 ldr r3, [pc, #448] ; (800186c ) 80016ac: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 80016b0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 80016b4: f8c2 3090 str.w r3, [r2, #144] ; 0x90 __HAL_RCC_BACKUPRESET_RELEASE(); 80016b8: 4a6c ldr r2, [pc, #432] ; (800186c ) 80016ba: 4b6c ldr r3, [pc, #432] ; (800186c ) 80016bc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 80016c0: f423 3380 bic.w r3, r3, #65536 ; 0x10000 80016c4: f8c2 3090 str.w r3, [r2, #144] ; 0x90 /* Restore the Content of BDCR register */ RCC->BDCR = tmpregister; 80016c8: 4a68 ldr r2, [pc, #416] ; (800186c ) 80016ca: 697b ldr r3, [r7, #20] 80016cc: f8c2 3090 str.w r3, [r2, #144] ; 0x90 } /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) 80016d0: 697b ldr r3, [r7, #20] 80016d2: f003 0301 and.w r3, r3, #1 80016d6: 2b00 cmp r3, #0 80016d8: d016 beq.n 8001708 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 80016da: f7fe fe0d bl 80002f8 80016de: 60f8 str r0, [r7, #12] /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) 80016e0: e00b b.n 80016fa { if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 80016e2: f7fe fe09 bl 80002f8 80016e6: 4602 mov r2, r0 80016e8: 68fb ldr r3, [r7, #12] 80016ea: 1ad3 subs r3, r2, r3 80016ec: f241 3288 movw r2, #5000 ; 0x1388 80016f0: 4293 cmp r3, r2 80016f2: d902 bls.n 80016fa { ret = HAL_TIMEOUT; 80016f4: 2303 movs r3, #3 80016f6: 74fb strb r3, [r7, #19] break; 80016f8: e006 b.n 8001708 { /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till LSE is ready */ while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RESET) 80016fa: 4b5c ldr r3, [pc, #368] ; (800186c ) 80016fc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8001700: f003 0302 and.w r3, r3, #2 8001704: 2b00 cmp r3, #0 8001706: d0ec beq.n 80016e2 break; } } } if(ret == HAL_OK) 8001708: 7cfb ldrb r3, [r7, #19] 800170a: 2b00 cmp r3, #0 800170c: d10b bne.n 8001726 { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800170e: 4957 ldr r1, [pc, #348] ; (800186c ) 8001710: 4b56 ldr r3, [pc, #344] ; (800186c ) 8001712: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 8001716: f423 7240 bic.w r2, r3, #768 ; 0x300 800171a: 687b ldr r3, [r7, #4] 800171c: 6d1b ldr r3, [r3, #80] ; 0x50 800171e: 4313 orrs r3, r2 8001720: f8c1 3090 str.w r3, [r1, #144] ; 0x90 8001724: e004 b.n 8001730 } else { /* set overall return value */ status = ret; 8001726: 7cfb ldrb r3, [r7, #19] 8001728: 74bb strb r3, [r7, #18] 800172a: e001 b.n 8001730 } } else { /* set overall return value */ status = ret; 800172c: 7cfb ldrb r3, [r7, #19] 800172e: 74bb strb r3, [r7, #18] } /* Restore clock configuration if changed */ if(pwrclkchanged == SET) 8001730: 7c7b ldrb r3, [r7, #17] 8001732: 2b01 cmp r3, #1 8001734: d105 bne.n 8001742 { __HAL_RCC_PWR_CLK_DISABLE(); 8001736: 4a4d ldr r2, [pc, #308] ; (800186c ) 8001738: 4b4c ldr r3, [pc, #304] ; (800186c ) 800173a: 6d9b ldr r3, [r3, #88] ; 0x58 800173c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 8001740: 6593 str r3, [r2, #88] ; 0x58 } } /*-------------------------- USART1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 8001742: 687b ldr r3, [r7, #4] 8001744: 681b ldr r3, [r3, #0] 8001746: f003 0301 and.w r3, r3, #1 800174a: 2b00 cmp r3, #0 800174c: d00a beq.n 8001764 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 800174e: 4947 ldr r1, [pc, #284] ; (800186c ) 8001750: 4b46 ldr r3, [pc, #280] ; (800186c ) 8001752: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8001756: f023 0203 bic.w r2, r3, #3 800175a: 687b ldr r3, [r7, #4] 800175c: 6a1b ldr r3, [r3, #32] 800175e: 4313 orrs r3, r2 8001760: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } /*-------------------------- USART2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) 8001764: 687b ldr r3, [r7, #4] 8001766: 681b ldr r3, [r3, #0] 8001768: f003 0302 and.w r3, r3, #2 800176c: 2b00 cmp r3, #0 800176e: d00a beq.n 8001786 { /* Check the parameters */ assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); /* Configure the USART2 clock source */ __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); 8001770: 493e ldr r1, [pc, #248] ; (800186c ) 8001772: 4b3e ldr r3, [pc, #248] ; (800186c ) 8001774: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8001778: f023 020c bic.w r2, r3, #12 800177c: 687b ldr r3, [r7, #4] 800177e: 6a5b ldr r3, [r3, #36] ; 0x24 8001780: 4313 orrs r3, r2 8001782: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } #endif /* UART5 */ /*-------------------------- LPUART1 clock source configuration ------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) 8001786: 687b ldr r3, [r7, #4] 8001788: 681b ldr r3, [r3, #0] 800178a: f003 0320 and.w r3, r3, #32 800178e: 2b00 cmp r3, #0 8001790: d00a beq.n 80017a8 { /* Check the parameters */ assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); /* Configure the LPUAR1 clock source */ __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); 8001792: 4936 ldr r1, [pc, #216] ; (800186c ) 8001794: 4b35 ldr r3, [pc, #212] ; (800186c ) 8001796: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 800179a: f423 6240 bic.w r2, r3, #3072 ; 0xc00 800179e: 687b ldr r3, [r7, #4] 80017a0: 6a9b ldr r3, [r3, #40] ; 0x28 80017a2: 4313 orrs r3, r2 80017a4: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } /*-------------------------- LPTIM1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) 80017a8: 687b ldr r3, [r7, #4] 80017aa: 681b ldr r3, [r3, #0] 80017ac: f403 7300 and.w r3, r3, #512 ; 0x200 80017b0: 2b00 cmp r3, #0 80017b2: d00a beq.n 80017ca { assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection)); __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); 80017b4: 492d ldr r1, [pc, #180] ; (800186c ) 80017b6: 4b2d ldr r3, [pc, #180] ; (800186c ) 80017b8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80017bc: f423 2240 bic.w r2, r3, #786432 ; 0xc0000 80017c0: 687b ldr r3, [r7, #4] 80017c2: 6b5b ldr r3, [r3, #52] ; 0x34 80017c4: 4313 orrs r3, r2 80017c6: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } /*-------------------------- LPTIM2 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) 80017ca: 687b ldr r3, [r7, #4] 80017cc: 681b ldr r3, [r3, #0] 80017ce: f403 6380 and.w r3, r3, #1024 ; 0x400 80017d2: 2b00 cmp r3, #0 80017d4: d00a beq.n 80017ec { assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection)); __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); 80017d6: 4925 ldr r1, [pc, #148] ; (800186c ) 80017d8: 4b24 ldr r3, [pc, #144] ; (800186c ) 80017da: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80017de: f423 1240 bic.w r2, r3, #3145728 ; 0x300000 80017e2: 687b ldr r3, [r7, #4] 80017e4: 6b9b ldr r3, [r3, #56] ; 0x38 80017e6: 4313 orrs r3, r2 80017e8: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } /*-------------------------- I2C1 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 80017ec: 687b ldr r3, [r7, #4] 80017ee: 681b ldr r3, [r3, #0] 80017f0: f003 0340 and.w r3, r3, #64 ; 0x40 80017f4: 2b00 cmp r3, #0 80017f6: d00a beq.n 800180e { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 80017f8: 491c ldr r1, [pc, #112] ; (800186c ) 80017fa: 4b1c ldr r3, [pc, #112] ; (800186c ) 80017fc: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8001800: f423 5240 bic.w r2, r3, #12288 ; 0x3000 8001804: 687b ldr r3, [r7, #4] 8001806: 6adb ldr r3, [r3, #44] ; 0x2c 8001808: 4313 orrs r3, r2 800180a: f8c1 3088 str.w r3, [r1, #136] ; 0x88 } #endif /* I2C2 */ /*-------------------------- I2C3 clock source configuration ---------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) 800180e: 687b ldr r3, [r7, #4] 8001810: 681b ldr r3, [r3, #0] 8001812: f403 7380 and.w r3, r3, #256 ; 0x100 8001816: 2b00 cmp r3, #0 8001818: d00a beq.n 8001830 { /* Check the parameters */ assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); /* Configure the I2C3 clock source */ __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); 800181a: 4914 ldr r1, [pc, #80] ; (800186c ) 800181c: 4b13 ldr r3, [pc, #76] ; (800186c ) 800181e: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8001822: f423 3240 bic.w r2, r3, #196608 ; 0x30000 8001826: 687b ldr r3, [r7, #4] 8001828: 6b1b ldr r3, [r3, #48] ; 0x30 800182a: 4313 orrs r3, r2 800182c: f8c1 3088 str.w r3, [r1, #136] ; 0x88 #endif /* I2C4 */ #if defined(USB_OTG_FS) || defined(USB) /*-------------------------- USB clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) 8001830: 687b ldr r3, [r7, #4] 8001832: 681b ldr r3, [r3, #0] 8001834: f403 5300 and.w r3, r3, #8192 ; 0x2000 8001838: 2b00 cmp r3, #0 800183a: d02d beq.n 8001898 { assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); __HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection); 800183c: 490b ldr r1, [pc, #44] ; (800186c ) 800183e: 4b0b ldr r3, [pc, #44] ; (800186c ) 8001840: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8001844: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000 8001848: 687b ldr r3, [r7, #4] 800184a: 6c1b ldr r3, [r3, #64] ; 0x40 800184c: 4313 orrs r3, r2 800184e: f8c1 3088 str.w r3, [r1, #136] ; 0x88 if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL) 8001852: 687b ldr r3, [r7, #4] 8001854: 6c1b ldr r3, [r3, #64] ; 0x40 8001856: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 800185a: d10b bne.n 8001874 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 800185c: 4a03 ldr r2, [pc, #12] ; (800186c ) 800185e: 4b03 ldr r3, [pc, #12] ; (800186c ) 8001860: 68db ldr r3, [r3, #12] 8001862: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 8001866: 60d3 str r3, [r2, #12] 8001868: e016 b.n 8001898 800186a: bf00 nop 800186c: 40021000 .word 0x40021000 8001870: 40007000 .word 0x40007000 } else { if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) 8001874: 687b ldr r3, [r7, #4] 8001876: 6c1b ldr r3, [r3, #64] ; 0x40 8001878: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 800187c: d10c bne.n 8001898 { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); 800187e: 687b ldr r3, [r7, #4] 8001880: 3304 adds r3, #4 8001882: 4618 mov r0, r3 8001884: 2101 movs r1, #1 8001886: f000 f871 bl 800196c 800188a: 4603 mov r3, r0 800188c: 74fb strb r3, [r7, #19] if(ret != HAL_OK) 800188e: 7cfb ldrb r3, [r7, #19] 8001890: 2b00 cmp r3, #0 8001892: d001 beq.n 8001898 { /* set overall return value */ status = ret; 8001894: 7cfb ldrb r3, [r7, #19] 8001896: 74bb strb r3, [r7, #18] } #endif /* SDMMC1 */ /*-------------------------- RNG clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) 8001898: 687b ldr r3, [r7, #4] 800189a: 681b ldr r3, [r3, #0] 800189c: f403 2380 and.w r3, r3, #262144 ; 0x40000 80018a0: 2b00 cmp r3, #0 80018a2: d028 beq.n 80018f6 { assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); 80018a4: 4930 ldr r1, [pc, #192] ; (8001968 ) 80018a6: 4b30 ldr r3, [pc, #192] ; (8001968 ) 80018a8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 80018ac: f023 6240 bic.w r2, r3, #201326592 ; 0xc000000 80018b0: 687b ldr r3, [r7, #4] 80018b2: 6c5b ldr r3, [r3, #68] ; 0x44 80018b4: 4313 orrs r3, r2 80018b6: f8c1 3088 str.w r3, [r1, #136] ; 0x88 if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) 80018ba: 687b ldr r3, [r7, #4] 80018bc: 6c5b ldr r3, [r3, #68] ; 0x44 80018be: f1b3 6f00 cmp.w r3, #134217728 ; 0x8000000 80018c2: d106 bne.n 80018d2 { /* Enable PLL48M1CLK output */ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK); 80018c4: 4a28 ldr r2, [pc, #160] ; (8001968 ) 80018c6: 4b28 ldr r3, [pc, #160] ; (8001968 ) 80018c8: 68db ldr r3, [r3, #12] 80018ca: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 80018ce: 60d3 str r3, [r2, #12] 80018d0: e011 b.n 80018f6 } else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1) 80018d2: 687b ldr r3, [r7, #4] 80018d4: 6c5b ldr r3, [r3, #68] ; 0x44 80018d6: f1b3 6f80 cmp.w r3, #67108864 ; 0x4000000 80018da: d10c bne.n 80018f6 { /* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE); 80018dc: 687b ldr r3, [r7, #4] 80018de: 3304 adds r3, #4 80018e0: 4618 mov r0, r3 80018e2: 2101 movs r1, #1 80018e4: f000 f842 bl 800196c 80018e8: 4603 mov r3, r0 80018ea: 74fb strb r3, [r7, #19] if(ret != HAL_OK) 80018ec: 7cfb ldrb r3, [r7, #19] 80018ee: 2b00 cmp r3, #0 80018f0: d001 beq.n 80018f6 { /* set overall return value */ status = ret; 80018f2: 7cfb ldrb r3, [r7, #19] 80018f4: 74bb strb r3, [r7, #18] } } } /*-------------------------- ADC clock source configuration ----------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 80018f6: 687b ldr r3, [r7, #4] 80018f8: 681b ldr r3, [r3, #0] 80018fa: f403 4380 and.w r3, r3, #16384 ; 0x4000 80018fe: 2b00 cmp r3, #0 8001900: d01c beq.n 800193c { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 8001902: 4919 ldr r1, [pc, #100] ; (8001968 ) 8001904: 4b18 ldr r3, [pc, #96] ; (8001968 ) 8001906: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 800190a: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 800190e: 687b ldr r3, [r7, #4] 8001910: 6c9b ldr r3, [r3, #72] ; 0x48 8001912: 4313 orrs r3, r2 8001914: f8c1 3088 str.w r3, [r1, #136] ; 0x88 if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) 8001918: 687b ldr r3, [r7, #4] 800191a: 6c9b ldr r3, [r3, #72] ; 0x48 800191c: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 8001920: d10c bne.n 800193c { /* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */ ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE); 8001922: 687b ldr r3, [r7, #4] 8001924: 3304 adds r3, #4 8001926: 4618 mov r0, r3 8001928: 2102 movs r1, #2 800192a: f000 f81f bl 800196c 800192e: 4603 mov r3, r0 8001930: 74fb strb r3, [r7, #19] if(ret != HAL_OK) 8001932: 7cfb ldrb r3, [r7, #19] 8001934: 2b00 cmp r3, #0 8001936: d001 beq.n 800193c { /* set overall return value */ status = ret; 8001938: 7cfb ldrb r3, [r7, #19] 800193a: 74bb strb r3, [r7, #18] } #if defined(SWPMI1) /*-------------------------- SWPMI1 clock source configuration -------------------*/ if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1) 800193c: 687b ldr r3, [r7, #4] 800193e: 681b ldr r3, [r3, #0] 8001940: f403 4300 and.w r3, r3, #32768 ; 0x8000 8001944: 2b00 cmp r3, #0 8001946: d00a beq.n 800195e { /* Check the parameters */ assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection)); /* Configure the SWPMI1 clock source */ __HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection); 8001948: 4907 ldr r1, [pc, #28] ; (8001968 ) 800194a: 4b07 ldr r3, [pc, #28] ; (8001968 ) 800194c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8001950: f023 4280 bic.w r2, r3, #1073741824 ; 0x40000000 8001954: 687b ldr r3, [r7, #4] 8001956: 6cdb ldr r3, [r3, #76] ; 0x4c 8001958: 4313 orrs r3, r2 800195a: f8c1 3088 str.w r3, [r1, #136] ; 0x88 __HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection); } #endif /* DFSDM1_Filter0 */ return status; 800195e: 7cbb ldrb r3, [r7, #18] } 8001960: 4618 mov r0, r3 8001962: 3718 adds r7, #24 8001964: 46bd mov sp, r7 8001966: bd80 pop {r7, pc} 8001968: 40021000 .word 0x40021000 0800196c : * @note PLLSAI1 is temporary disable to apply new parameters * * @retval HAL status */ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider) { 800196c: b590 push {r4, r7, lr} 800196e: b095 sub sp, #84 ; 0x54 8001970: af00 add r7, sp, #0 8001972: 6078 str r0, [r7, #4] 8001974: 6039 str r1, [r7, #0] uint32_t tickstart = 0U; 8001976: 2300 movs r3, #0 8001978: 64bb str r3, [r7, #72] ; 0x48 HAL_StatusTypeDef status = HAL_OK; 800197a: 2300 movs r3, #0 800197c: f887 304f strb.w r3, [r7, #79] ; 0x4f assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M)); assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N)); assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut)); /* Check that PLLSAI1 clock source and divider M can be applied */ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) 8001980: 4ba2 ldr r3, [pc, #648] ; (8001c0c ) 8001982: 68db ldr r3, [r3, #12] 8001984: f003 0303 and.w r3, r3, #3 8001988: 2b00 cmp r3, #0 800198a: d023 beq.n 80019d4 { /* PLL clock source and divider M already set, check that no request for change */ if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) 800198c: 4b9f ldr r3, [pc, #636] ; (8001c0c ) 800198e: 68db ldr r3, [r3, #12] 8001990: f003 0203 and.w r2, r3, #3 8001994: 687b ldr r3, [r7, #4] 8001996: 681b ldr r3, [r3, #0] 8001998: 429a cmp r2, r3 800199a: d117 bne.n 80019cc || (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) 800199c: 687b ldr r3, [r7, #4] 800199e: 681b ldr r3, [r3, #0] /* Check that PLLSAI1 clock source and divider M can be applied */ if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE) { /* PLL clock source and divider M already set, check that no request for change */ if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) || 80019a0: 2b00 cmp r3, #0 80019a2: d013 beq.n 80019cc (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) || (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai1->PLLSAI1M) 80019a4: 4b99 ldr r3, [pc, #612] ; (8001c0c ) 80019a6: 68db ldr r3, [r3, #12] 80019a8: f003 0270 and.w r2, r3, #112 ; 0x70 80019ac: 2370 movs r3, #112 ; 0x70 80019ae: 647b str r3, [r7, #68] ; 0x44 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 80019b0: 6c7b ldr r3, [r7, #68] ; 0x44 80019b2: fa93 f3a3 rbit r3, r3 80019b6: 643b str r3, [r7, #64] ; 0x40 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 80019b8: 6c3b ldr r3, [r7, #64] ; 0x40 80019ba: fab3 f383 clz r3, r3 80019be: fa22 f303 lsr.w r3, r2, r3 80019c2: 1c5a adds r2, r3, #1 80019c4: 687b ldr r3, [r7, #4] 80019c6: 685b ldr r3, [r3, #4] { /* PLL clock source and divider M already set, check that no request for change */ if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source) || (PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE) || 80019c8: 429a cmp r2, r3 80019ca: d052 beq.n 8001a72 (((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> POSITION_VAL(RCC_PLLCFGR_PLLM)) + 1U) != PllSai1->PLLSAI1M) ) { status = HAL_ERROR; 80019cc: 2301 movs r3, #1 80019ce: f887 304f strb.w r3, [r7, #79] ; 0x4f 80019d2: e04e b.n 8001a72 } } else { /* Check PLLSAI1 clock source availability */ switch(PllSai1->PLLSAI1Source) 80019d4: 687b ldr r3, [r7, #4] 80019d6: 681b ldr r3, [r3, #0] 80019d8: 2b02 cmp r3, #2 80019da: d00e beq.n 80019fa 80019dc: 2b03 cmp r3, #3 80019de: d017 beq.n 8001a10 80019e0: 2b01 cmp r3, #1 80019e2: d126 bne.n 8001a32 { case RCC_PLLSOURCE_MSI: if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY)) 80019e4: 4b89 ldr r3, [pc, #548] ; (8001c0c ) 80019e6: 681b ldr r3, [r3, #0] 80019e8: f003 0302 and.w r3, r3, #2 80019ec: 2b00 cmp r3, #0 80019ee: d103 bne.n 80019f8 { status = HAL_ERROR; 80019f0: 2301 movs r3, #1 80019f2: f887 304f strb.w r3, [r7, #79] ; 0x4f } break; 80019f6: e020 b.n 8001a3a 80019f8: e01f b.n 8001a3a case RCC_PLLSOURCE_HSI: if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY)) 80019fa: 4b84 ldr r3, [pc, #528] ; (8001c0c ) 80019fc: 681b ldr r3, [r3, #0] 80019fe: f403 6380 and.w r3, r3, #1024 ; 0x400 8001a02: 2b00 cmp r3, #0 8001a04: d103 bne.n 8001a0e { status = HAL_ERROR; 8001a06: 2301 movs r3, #1 8001a08: f887 304f strb.w r3, [r7, #79] ; 0x4f } break; 8001a0c: e015 b.n 8001a3a 8001a0e: e014 b.n 8001a3a case RCC_PLLSOURCE_HSE: if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY) && HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP)) 8001a10: 4b7e ldr r3, [pc, #504] ; (8001c0c ) 8001a12: 681b ldr r3, [r3, #0] 8001a14: f403 3300 and.w r3, r3, #131072 ; 0x20000 8001a18: 2b00 cmp r3, #0 8001a1a: d109 bne.n 8001a30 8001a1c: 4b7b ldr r3, [pc, #492] ; (8001c0c ) 8001a1e: 681b ldr r3, [r3, #0] 8001a20: f403 2380 and.w r3, r3, #262144 ; 0x40000 8001a24: 2b00 cmp r3, #0 8001a26: d103 bne.n 8001a30 { status = HAL_ERROR; 8001a28: 2301 movs r3, #1 8001a2a: f887 304f strb.w r3, [r7, #79] ; 0x4f } break; 8001a2e: e004 b.n 8001a3a 8001a30: e003 b.n 8001a3a default: status = HAL_ERROR; 8001a32: 2301 movs r3, #1 8001a34: f887 304f strb.w r3, [r7, #79] ; 0x4f break; 8001a38: bf00 nop } if(status == HAL_OK) 8001a3a: f897 304f ldrb.w r3, [r7, #79] ; 0x4f 8001a3e: 2b00 cmp r3, #0 8001a40: d117 bne.n 8001a72 { /* Set PLLSAI1 clock source and divider M */ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLM)); 8001a42: 4c72 ldr r4, [pc, #456] ; (8001c0c ) 8001a44: 4b71 ldr r3, [pc, #452] ; (8001c0c ) 8001a46: 68db ldr r3, [r3, #12] 8001a48: f023 0273 bic.w r2, r3, #115 ; 0x73 8001a4c: 687b ldr r3, [r7, #4] 8001a4e: 6819 ldr r1, [r3, #0] 8001a50: 687b ldr r3, [r7, #4] 8001a52: 685b ldr r3, [r3, #4] 8001a54: 1e58 subs r0, r3, #1 8001a56: 2370 movs r3, #112 ; 0x70 8001a58: 63fb str r3, [r7, #60] ; 0x3c __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001a5a: 6bfb ldr r3, [r7, #60] ; 0x3c 8001a5c: fa93 f3a3 rbit r3, r3 8001a60: 63bb str r3, [r7, #56] ; 0x38 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 8001a62: 6bbb ldr r3, [r7, #56] ; 0x38 8001a64: fab3 f383 clz r3, r3 8001a68: fa00 f303 lsl.w r3, r0, r3 8001a6c: 430b orrs r3, r1 8001a6e: 4313 orrs r3, r2 8001a70: 60e3 str r3, [r4, #12] } } if(status == HAL_OK) 8001a72: f897 304f ldrb.w r3, [r7, #79] ; 0x4f 8001a76: 2b00 cmp r3, #0 8001a78: f040 80c1 bne.w 8001bfe { /* Disable the PLLSAI1 */ __HAL_RCC_PLLSAI1_DISABLE(); 8001a7c: 4a63 ldr r2, [pc, #396] ; (8001c0c ) 8001a7e: 4b63 ldr r3, [pc, #396] ; (8001c0c ) 8001a80: 681b ldr r3, [r3, #0] 8001a82: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 8001a86: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001a88: f7fe fc36 bl 80002f8 8001a8c: 64b8 str r0, [r7, #72] ; 0x48 /* Wait till PLLSAI1 is ready to be updated */ while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) 8001a8e: e00a b.n 8001aa6 { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 8001a90: f7fe fc32 bl 80002f8 8001a94: 4602 mov r2, r0 8001a96: 6cbb ldr r3, [r7, #72] ; 0x48 8001a98: 1ad3 subs r3, r2, r3 8001a9a: 2b02 cmp r3, #2 8001a9c: d903 bls.n 8001aa6 { status = HAL_TIMEOUT; 8001a9e: 2303 movs r3, #3 8001aa0: f887 304f strb.w r3, [r7, #79] ; 0x4f break; 8001aa4: e005 b.n 8001ab2 /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLLSAI1 is ready to be updated */ while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != RESET) 8001aa6: 4b59 ldr r3, [pc, #356] ; (8001c0c ) 8001aa8: 681b ldr r3, [r3, #0] 8001aaa: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8001aae: 2b00 cmp r3, #0 8001ab0: d1ee bne.n 8001a90 status = HAL_TIMEOUT; break; } } if(status == HAL_OK) 8001ab2: f897 304f ldrb.w r3, [r7, #79] ; 0x4f 8001ab6: 2b00 cmp r3, #0 8001ab8: f040 80a1 bne.w 8001bfe { if(Divider == DIVIDER_P_UPDATE) 8001abc: 683b ldr r3, [r7, #0] 8001abe: 2b00 cmp r3, #0 8001ac0: d125 bne.n 8001b0e { assert_param(IS_RCC_PLLSAI1P_VALUE(PllSai1->PLLSAI1P)); /* Configure the PLLSAI1 Division factor P and Multiplication factor N*/ #if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT) MODIFY_REG(RCC->PLLSAI1CFGR, 8001ac2: 4c52 ldr r4, [pc, #328] ; (8001c0c ) 8001ac4: 4b51 ldr r3, [pc, #324] ; (8001c0c ) 8001ac6: 691b ldr r3, [r3, #16] 8001ac8: f023 4378 bic.w r3, r3, #4160749568 ; 0xf8000000 8001acc: f423 43fe bic.w r3, r3, #32512 ; 0x7f00 8001ad0: 687a ldr r2, [r7, #4] 8001ad2: 6891 ldr r1, [r2, #8] 8001ad4: f44f 42fe mov.w r2, #32512 ; 0x7f00 8001ad8: 637a str r2, [r7, #52] ; 0x34 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001ada: 6b7a ldr r2, [r7, #52] ; 0x34 8001adc: fa92 f2a2 rbit r2, r2 8001ae0: 633a str r2, [r7, #48] ; 0x30 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 8001ae2: 6b3a ldr r2, [r7, #48] ; 0x30 8001ae4: fab2 f282 clz r2, r2 8001ae8: 4091 lsls r1, r2 8001aea: 687a ldr r2, [r7, #4] 8001aec: 68d0 ldr r0, [r2, #12] 8001aee: f04f 4278 mov.w r2, #4160749568 ; 0xf8000000 8001af2: 62fa str r2, [r7, #44] ; 0x2c __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001af4: 6afa ldr r2, [r7, #44] ; 0x2c 8001af6: fa92 f2a2 rbit r2, r2 8001afa: 62ba str r2, [r7, #40] ; 0x28 result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 8001afc: 6aba ldr r2, [r7, #40] ; 0x28 8001afe: fab2 f282 clz r2, r2 8001b02: fa00 f202 lsl.w r2, r0, r2 8001b06: 430a orrs r2, r1 8001b08: 4313 orrs r3, r2 8001b0a: 6123 str r3, [r4, #16] 8001b0c: e051 b.n 8001bb2 RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1P, (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | ((PllSai1->PLLSAI1P >> 4U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1P))); #endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */ } else if(Divider == DIVIDER_Q_UPDATE) 8001b0e: 683b ldr r3, [r7, #0] 8001b10: 2b01 cmp r3, #1 8001b12: d127 bne.n 8001b64 { assert_param(IS_RCC_PLLSAI1Q_VALUE(PllSai1->PLLSAI1Q)); /* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/ MODIFY_REG(RCC->PLLSAI1CFGR, 8001b14: 4c3d ldr r4, [pc, #244] ; (8001c0c ) 8001b16: 4b3d ldr r3, [pc, #244] ; (8001c0c ) 8001b18: 691b ldr r3, [r3, #16] 8001b1a: f423 03c0 bic.w r3, r3, #6291456 ; 0x600000 8001b1e: f423 43fe bic.w r3, r3, #32512 ; 0x7f00 8001b22: 687a ldr r2, [r7, #4] 8001b24: 6891 ldr r1, [r2, #8] 8001b26: f44f 42fe mov.w r2, #32512 ; 0x7f00 8001b2a: 627a str r2, [r7, #36] ; 0x24 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001b2c: 6a7a ldr r2, [r7, #36] ; 0x24 8001b2e: fa92 f2a2 rbit r2, r2 8001b32: 623a str r2, [r7, #32] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 8001b34: 6a3a ldr r2, [r7, #32] 8001b36: fab2 f282 clz r2, r2 8001b3a: 4091 lsls r1, r2 8001b3c: 687a ldr r2, [r7, #4] 8001b3e: 6912 ldr r2, [r2, #16] 8001b40: 0852 lsrs r2, r2, #1 8001b42: 1e50 subs r0, r2, #1 8001b44: f44f 02c0 mov.w r2, #6291456 ; 0x600000 8001b48: 61fa str r2, [r7, #28] __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001b4a: 69fa ldr r2, [r7, #28] 8001b4c: fa92 f2a2 rbit r2, r2 8001b50: 61ba str r2, [r7, #24] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 8001b52: 69ba ldr r2, [r7, #24] 8001b54: fab2 f282 clz r2, r2 8001b58: fa00 f202 lsl.w r2, r0, r2 8001b5c: 430a orrs r2, r1 8001b5e: 4313 orrs r3, r2 8001b60: 6123 str r3, [r4, #16] 8001b62: e026 b.n 8001bb2 } else { assert_param(IS_RCC_PLLSAI1R_VALUE(PllSai1->PLLSAI1R)); /* Configure the PLLSAI1 Division factor R and Multiplication factor N*/ MODIFY_REG(RCC->PLLSAI1CFGR, 8001b64: 4c29 ldr r4, [pc, #164] ; (8001c0c ) 8001b66: 4b29 ldr r3, [pc, #164] ; (8001c0c ) 8001b68: 691b ldr r3, [r3, #16] 8001b6a: f023 63c0 bic.w r3, r3, #100663296 ; 0x6000000 8001b6e: f423 43fe bic.w r3, r3, #32512 ; 0x7f00 8001b72: 687a ldr r2, [r7, #4] 8001b74: 6891 ldr r1, [r2, #8] 8001b76: f44f 42fe mov.w r2, #32512 ; 0x7f00 8001b7a: 617a str r2, [r7, #20] __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001b7c: 697a ldr r2, [r7, #20] 8001b7e: fa92 f2a2 rbit r2, r2 8001b82: 613a str r2, [r7, #16] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 8001b84: 693a ldr r2, [r7, #16] 8001b86: fab2 f282 clz r2, r2 8001b8a: 4091 lsls r1, r2 8001b8c: 687a ldr r2, [r7, #4] 8001b8e: 6952 ldr r2, [r2, #20] 8001b90: 0852 lsrs r2, r2, #1 8001b92: 1e50 subs r0, r2, #1 8001b94: f04f 62c0 mov.w r2, #100663296 ; 0x6000000 8001b98: 60fa str r2, [r7, #12] __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) { uint32_t result; #if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); 8001b9a: 68fa ldr r2, [r7, #12] 8001b9c: fa92 f2a2 rbit r2, r2 8001ba0: 60ba str r2, [r7, #8] result |= value & 1U; s--; } result <<= s; /* shift when v's highest bits are zero */ #endif return(result); 8001ba2: 68ba ldr r2, [r7, #8] 8001ba4: fab2 f282 clz r2, r2 8001ba8: fa00 f202 lsl.w r2, r0, r2 8001bac: 430a orrs r2, r1 8001bae: 4313 orrs r3, r2 8001bb0: 6123 str r3, [r4, #16] (PllSai1->PLLSAI1N << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1N)) | (((PllSai1->PLLSAI1R >> 1U) - 1U) << POSITION_VAL(RCC_PLLSAI1CFGR_PLLSAI1R))); } /* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/ __HAL_RCC_PLLSAI1_ENABLE(); 8001bb2: 4a16 ldr r2, [pc, #88] ; (8001c0c ) 8001bb4: 4b15 ldr r3, [pc, #84] ; (8001c0c ) 8001bb6: 681b ldr r3, [r3, #0] 8001bb8: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 8001bbc: 6013 str r3, [r2, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8001bbe: f7fe fb9b bl 80002f8 8001bc2: 64b8 str r0, [r7, #72] ; 0x48 /* Wait till PLLSAI1 is ready */ while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) 8001bc4: e00a b.n 8001bdc { if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE) 8001bc6: f7fe fb97 bl 80002f8 8001bca: 4602 mov r2, r0 8001bcc: 6cbb ldr r3, [r7, #72] ; 0x48 8001bce: 1ad3 subs r3, r2, r3 8001bd0: 2b02 cmp r3, #2 8001bd2: d903 bls.n 8001bdc { status = HAL_TIMEOUT; 8001bd4: 2303 movs r3, #3 8001bd6: f887 304f strb.w r3, [r7, #79] ; 0x4f break; 8001bda: e005 b.n 8001be8 /* Get Start Tick*/ tickstart = HAL_GetTick(); /* Wait till PLLSAI1 is ready */ while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == RESET) 8001bdc: 4b0b ldr r3, [pc, #44] ; (8001c0c ) 8001bde: 681b ldr r3, [r3, #0] 8001be0: f003 6300 and.w r3, r3, #134217728 ; 0x8000000 8001be4: 2b00 cmp r3, #0 8001be6: d0ee beq.n 8001bc6 status = HAL_TIMEOUT; break; } } if(status == HAL_OK) 8001be8: f897 304f ldrb.w r3, [r7, #79] ; 0x4f 8001bec: 2b00 cmp r3, #0 8001bee: d106 bne.n 8001bfe { /* Configure the PLLSAI1 Clock output(s) */ __HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut); 8001bf0: 4906 ldr r1, [pc, #24] ; (8001c0c ) 8001bf2: 4b06 ldr r3, [pc, #24] ; (8001c0c ) 8001bf4: 691a ldr r2, [r3, #16] 8001bf6: 687b ldr r3, [r7, #4] 8001bf8: 699b ldr r3, [r3, #24] 8001bfa: 4313 orrs r3, r2 8001bfc: 610b str r3, [r1, #16] } } } return status; 8001bfe: f897 304f ldrb.w r3, [r7, #79] ; 0x4f } 8001c02: 4618 mov r0, r3 8001c04: 3754 adds r7, #84 ; 0x54 8001c06: 46bd mov sp, r7 8001c08: bd90 pop {r4, r7, pc} 8001c0a: bf00 nop 8001c0c: 40021000 .word 0x40021000 08001c10
: /* USER CODE END 0 */ int main(void) { 8001c10: b580 push {r7, lr} 8001c12: b082 sub sp, #8 8001c14: af00 add r7, sp, #0 /* USER CODE END 1 */ /* MCU Configuration----------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 8001c16: f7fe fb37 bl 8000288 /* Configure the system clock */ SystemClock_Config(); 8001c1a: f000 f825 bl 8001c68 /* Initialize all configured peripherals */ MX_GPIO_Init(); 8001c1e: f000 f895 bl 8001d4c /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { for(i=0;i<40000;i++) 8001c22: 2300 movs r3, #0 8001c24: 607b str r3, [r7, #4] 8001c26: e007 b.n 8001c38 { HAL_GPIO_WritePin(GPIOB,GPIO_PIN_3,GPIO_PIN_SET); 8001c28: 480e ldr r0, [pc, #56] ; (8001c64 ) 8001c2a: 2108 movs r1, #8 8001c2c: 2201 movs r2, #1 8001c2e: f7fe fde1 bl 80007f4 /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { for(i=0;i<40000;i++) 8001c32: 687b ldr r3, [r7, #4] 8001c34: 3301 adds r3, #1 8001c36: 607b str r3, [r7, #4] 8001c38: 687b ldr r3, [r7, #4] 8001c3a: f649 423f movw r2, #39999 ; 0x9c3f 8001c3e: 4293 cmp r3, r2 8001c40: d9f2 bls.n 8001c28 { HAL_GPIO_WritePin(GPIOB,GPIO_PIN_3,GPIO_PIN_SET); } for(i=0;i<10000;i++) 8001c42: 2300 movs r3, #0 8001c44: 607b str r3, [r7, #4] 8001c46: e007 b.n 8001c58 { HAL_GPIO_WritePin(GPIOB,GPIO_PIN_3,GPIO_PIN_RESET); 8001c48: 4806 ldr r0, [pc, #24] ; (8001c64 ) 8001c4a: 2108 movs r1, #8 8001c4c: 2200 movs r2, #0 8001c4e: f7fe fdd1 bl 80007f4 { for(i=0;i<40000;i++) { HAL_GPIO_WritePin(GPIOB,GPIO_PIN_3,GPIO_PIN_SET); } for(i=0;i<10000;i++) 8001c52: 687b ldr r3, [r7, #4] 8001c54: 3301 adds r3, #1 8001c56: 607b str r3, [r7, #4] 8001c58: 687b ldr r3, [r7, #4] 8001c5a: f242 720f movw r2, #9999 ; 0x270f 8001c5e: 4293 cmp r3, r2 8001c60: d9f2 bls.n 8001c48 //GPIO_SetBits(GPIOB, GPIO_PIN_3); /* USER CODE END WHILE */ /* USER CODE BEGIN 3 */ } 8001c62: e7de b.n 8001c22 8001c64: 48000400 .word 0x48000400 08001c68 : } /** System Clock Configuration */ void SystemClock_Config(void) { 8001c68: b580 push {r7, lr} 8001c6a: b0ac sub sp, #176 ; 0xb0 8001c6c: af00 add r7, sp, #0 RCC_ClkInitTypeDef RCC_ClkInitStruct; RCC_PeriphCLKInitTypeDef PeriphClkInit; /**Initializes the CPU, AHB and APB busses clocks */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI; 8001c6e: 2310 movs r3, #16 8001c70: 66fb str r3, [r7, #108] ; 0x6c RCC_OscInitStruct.MSIState = RCC_MSI_ON; 8001c72: 2301 movs r3, #1 8001c74: f8c7 3084 str.w r3, [r7, #132] ; 0x84 RCC_OscInitStruct.MSICalibrationValue = 0; 8001c78: 2300 movs r3, #0 8001c7a: f8c7 3088 str.w r3, [r7, #136] ; 0x88 RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6; 8001c7e: 2360 movs r3, #96 ; 0x60 8001c80: f8c7 308c str.w r3, [r7, #140] ; 0x8c RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; 8001c84: 2300 movs r3, #0 8001c86: f8c7 3094 str.w r3, [r7, #148] ; 0x94 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 8001c8a: f107 036c add.w r3, r7, #108 ; 0x6c 8001c8e: 4618 mov r0, r3 8001c90: f7fe fe2a bl 80008e8 8001c94: 4603 mov r3, r0 8001c96: 2b00 cmp r3, #0 8001c98: d001 beq.n 8001c9e { Error_Handler(); 8001c9a: f000 f88d bl 8001db8 } /**Initializes the CPU, AHB and APB busses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 8001c9e: 230f movs r3, #15 8001ca0: 65bb str r3, [r7, #88] ; 0x58 |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; 8001ca2: 2300 movs r3, #0 8001ca4: 65fb str r3, [r7, #92] ; 0x5c RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; 8001ca6: 2300 movs r3, #0 8001ca8: 663b str r3, [r7, #96] ; 0x60 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; 8001caa: 2300 movs r3, #0 8001cac: 667b str r3, [r7, #100] ; 0x64 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; 8001cae: 2300 movs r3, #0 8001cb0: 66bb str r3, [r7, #104] ; 0x68 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) 8001cb2: f107 0358 add.w r3, r7, #88 ; 0x58 8001cb6: 4618 mov r0, r3 8001cb8: 2100 movs r1, #0 8001cba: f7ff f9d7 bl 800106c 8001cbe: 4603 mov r3, r0 8001cc0: 2b00 cmp r3, #0 8001cc2: d001 beq.n 8001cc8 { Error_Handler(); 8001cc4: f000 f878 bl 8001db8 } PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1|RCC_PERIPHCLK_ADC; 8001cc8: f244 0301 movw r3, #16385 ; 0x4001 8001ccc: 607b str r3, [r7, #4] PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; 8001cce: 2300 movs r3, #0 8001cd0: 627b str r3, [r7, #36] ; 0x24 PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1; 8001cd2: f04f 5380 mov.w r3, #268435456 ; 0x10000000 8001cd6: 64fb str r3, [r7, #76] ; 0x4c PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_MSI; 8001cd8: 2301 movs r3, #1 8001cda: 60bb str r3, [r7, #8] PeriphClkInit.PLLSAI1.PLLSAI1M = 1; 8001cdc: 2301 movs r3, #1 8001cde: 60fb str r3, [r7, #12] PeriphClkInit.PLLSAI1.PLLSAI1N = 16; 8001ce0: 2310 movs r3, #16 8001ce2: 613b str r3, [r7, #16] PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7; 8001ce4: 2307 movs r3, #7 8001ce6: 617b str r3, [r7, #20] PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2; 8001ce8: 2302 movs r3, #2 8001cea: 61bb str r3, [r7, #24] PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2; 8001cec: 2302 movs r3, #2 8001cee: 61fb str r3, [r7, #28] PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_ADC1CLK; 8001cf0: f04f 7380 mov.w r3, #16777216 ; 0x1000000 8001cf4: 623b str r3, [r7, #32] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8001cf6: 1d3b adds r3, r7, #4 8001cf8: 4618 mov r0, r3 8001cfa: f7ff fc45 bl 8001588 8001cfe: 4603 mov r3, r0 8001d00: 2b00 cmp r3, #0 8001d02: d001 beq.n 8001d08 { Error_Handler(); 8001d04: f000 f858 bl 8001db8 } /**Configure the main internal regulator output voltage */ if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) 8001d08: f44f 7000 mov.w r0, #512 ; 0x200 8001d0c: f7fe fd98 bl 8000840 8001d10: 4603 mov r3, r0 8001d12: 2b00 cmp r3, #0 8001d14: d001 beq.n 8001d1a { Error_Handler(); 8001d16: f000 f84f bl 8001db8 } /**Configure the Systick interrupt time */ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000); 8001d1a: f7ff fbc7 bl 80014ac 8001d1e: 4602 mov r2, r0 8001d20: 4b09 ldr r3, [pc, #36] ; (8001d48 ) 8001d22: fba3 2302 umull r2, r3, r3, r2 8001d26: 099b lsrs r3, r3, #6 8001d28: 4618 mov r0, r3 8001d2a: f7fe fbc7 bl 80004bc /**Configure the Systick */ HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); 8001d2e: 2004 movs r0, #4 8001d30: f7fe fbd0 bl 80004d4 /* SysTick_IRQn interrupt configuration */ HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); 8001d34: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001d38: 2100 movs r1, #0 8001d3a: 2200 movs r2, #0 8001d3c: f7fe fba2 bl 8000484 } 8001d40: 37b0 adds r7, #176 ; 0xb0 8001d42: 46bd mov sp, r7 8001d44: bd80 pop {r7, pc} 8001d46: bf00 nop 8001d48: 10624dd3 .word 0x10624dd3 08001d4c : * Output * EVENT_OUT * EXTI */ static void MX_GPIO_Init(void) { 8001d4c: b580 push {r7, lr} 8001d4e: b088 sub sp, #32 8001d50: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct; /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8001d52: 4a17 ldr r2, [pc, #92] ; (8001db0 ) 8001d54: 4b16 ldr r3, [pc, #88] ; (8001db0 ) 8001d56: 6cdb ldr r3, [r3, #76] ; 0x4c 8001d58: f043 0301 orr.w r3, r3, #1 8001d5c: 64d3 str r3, [r2, #76] ; 0x4c 8001d5e: 4b14 ldr r3, [pc, #80] ; (8001db0 ) 8001d60: 6cdb ldr r3, [r3, #76] ; 0x4c 8001d62: f003 0301 and.w r3, r3, #1 8001d66: 60bb str r3, [r7, #8] 8001d68: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001d6a: 4a11 ldr r2, [pc, #68] ; (8001db0 ) 8001d6c: 4b10 ldr r3, [pc, #64] ; (8001db0 ) 8001d6e: 6cdb ldr r3, [r3, #76] ; 0x4c 8001d70: f043 0302 orr.w r3, r3, #2 8001d74: 64d3 str r3, [r2, #76] ; 0x4c 8001d76: 4b0e ldr r3, [pc, #56] ; (8001db0 ) 8001d78: 6cdb ldr r3, [r3, #76] ; 0x4c 8001d7a: f003 0302 and.w r3, r3, #2 8001d7e: 607b str r3, [r7, #4] 8001d80: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, GPIO_PIN_3, GPIO_PIN_RESET); 8001d82: 480c ldr r0, [pc, #48] ; (8001db4 ) 8001d84: 2108 movs r1, #8 8001d86: 2200 movs r2, #0 8001d88: f7fe fd34 bl 80007f4 /*Configure GPIO pin : PB3 */ GPIO_InitStruct.Pin = GPIO_PIN_3; 8001d8c: 2308 movs r3, #8 8001d8e: 60fb str r3, [r7, #12] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 8001d90: 2301 movs r3, #1 8001d92: 613b str r3, [r7, #16] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001d94: 2300 movs r3, #0 8001d96: 617b str r3, [r7, #20] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8001d98: 2300 movs r3, #0 8001d9a: 61bb str r3, [r7, #24] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001d9c: f107 030c add.w r3, r7, #12 8001da0: 4804 ldr r0, [pc, #16] ; (8001db4 ) 8001da2: 4619 mov r1, r3 8001da4: f7fe fbbe bl 8000524 } 8001da8: 3720 adds r7, #32 8001daa: 46bd mov sp, r7 8001dac: bd80 pop {r7, pc} 8001dae: bf00 nop 8001db0: 40021000 .word 0x40021000 8001db4: 48000400 .word 0x48000400 08001db8 : * @brief This function is executed in case of error occurrence. * @param None * @retval None */ void Error_Handler(void) { 8001db8: b480 push {r7} 8001dba: af00 add r7, sp, #0 /* USER CODE BEGIN Error_Handler */ /* User can add his own implementation to report the HAL error return state */ while(1) { } 8001dbc: e7fe b.n 8001dbc 8001dbe: bf00 nop 08001dc0 : /* USER CODE END 0 */ /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8001dc0: b580 push {r7, lr} 8001dc2: b082 sub sp, #8 8001dc4: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8001dc6: 4a24 ldr r2, [pc, #144] ; (8001e58 ) 8001dc8: 4b23 ldr r3, [pc, #140] ; (8001e58 ) 8001dca: 6e1b ldr r3, [r3, #96] ; 0x60 8001dcc: f043 0301 orr.w r3, r3, #1 8001dd0: 6613 str r3, [r2, #96] ; 0x60 8001dd2: 4b21 ldr r3, [pc, #132] ; (8001e58 ) 8001dd4: 6e1b ldr r3, [r3, #96] ; 0x60 8001dd6: f003 0301 and.w r3, r3, #1 8001dda: 607b str r3, [r7, #4] 8001ddc: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8001dde: 4a1e ldr r2, [pc, #120] ; (8001e58 ) 8001de0: 4b1d ldr r3, [pc, #116] ; (8001e58 ) 8001de2: 6d9b ldr r3, [r3, #88] ; 0x58 8001de4: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 8001de8: 6593 str r3, [r2, #88] ; 0x58 8001dea: 4b1b ldr r3, [pc, #108] ; (8001e58 ) 8001dec: 6d9b ldr r3, [r3, #88] ; 0x58 8001dee: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 8001df2: 603b str r3, [r7, #0] 8001df4: 683b ldr r3, [r7, #0] HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); 8001df6: 2003 movs r0, #3 8001df8: f7fe fb3a bl 8000470 /* System interrupt init*/ /* MemoryManagement_IRQn interrupt configuration */ HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0); 8001dfc: f06f 000b mvn.w r0, #11 8001e00: 2100 movs r1, #0 8001e02: 2200 movs r2, #0 8001e04: f7fe fb3e bl 8000484 /* BusFault_IRQn interrupt configuration */ HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0); 8001e08: f06f 000a mvn.w r0, #10 8001e0c: 2100 movs r1, #0 8001e0e: 2200 movs r2, #0 8001e10: f7fe fb38 bl 8000484 /* UsageFault_IRQn interrupt configuration */ HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0); 8001e14: f06f 0009 mvn.w r0, #9 8001e18: 2100 movs r1, #0 8001e1a: 2200 movs r2, #0 8001e1c: f7fe fb32 bl 8000484 /* SVCall_IRQn interrupt configuration */ HAL_NVIC_SetPriority(SVCall_IRQn, 0, 0); 8001e20: f06f 0004 mvn.w r0, #4 8001e24: 2100 movs r1, #0 8001e26: 2200 movs r2, #0 8001e28: f7fe fb2c bl 8000484 /* DebugMonitor_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0); 8001e2c: f06f 0003 mvn.w r0, #3 8001e30: 2100 movs r1, #0 8001e32: 2200 movs r2, #0 8001e34: f7fe fb26 bl 8000484 /* PendSV_IRQn interrupt configuration */ HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0); 8001e38: f06f 0001 mvn.w r0, #1 8001e3c: 2100 movs r1, #0 8001e3e: 2200 movs r2, #0 8001e40: f7fe fb20 bl 8000484 /* SysTick_IRQn interrupt configuration */ HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); 8001e44: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8001e48: 2100 movs r1, #0 8001e4a: 2200 movs r2, #0 8001e4c: f7fe fb1a bl 8000484 /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8001e50: 3708 adds r7, #8 8001e52: 46bd mov sp, r7 8001e54: bd80 pop {r7, pc} 8001e56: bf00 nop 8001e58: 40021000 .word 0x40021000 08001e5c : /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8001e5c: b480 push {r7} 8001e5e: af00 add r7, sp, #0 /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ /* USER CODE END NonMaskableInt_IRQn 1 */ } 8001e60: 46bd mov sp, r7 8001e62: f85d 7b04 ldr.w r7, [sp], #4 8001e66: 4770 bx lr 08001e68 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8001e68: b480 push {r7} 8001e6a: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) { } 8001e6c: e7fe b.n 8001e6c 8001e6e: bf00 nop 08001e70 : /** * @brief This function handles Memory management fault. */ void MemManage_Handler(void) { 8001e70: b480 push {r7} 8001e72: af00 add r7, sp, #0 /* USER CODE BEGIN MemoryManagement_IRQn 0 */ /* USER CODE END MemoryManagement_IRQn 0 */ while (1) { } 8001e74: e7fe b.n 8001e74 8001e76: bf00 nop 08001e78 : /** * @brief This function handles Prefetch fault, memory access fault. */ void BusFault_Handler(void) { 8001e78: b480 push {r7} 8001e7a: af00 add r7, sp, #0 /* USER CODE BEGIN BusFault_IRQn 0 */ /* USER CODE END BusFault_IRQn 0 */ while (1) { } 8001e7c: e7fe b.n 8001e7c 8001e7e: bf00 nop 08001e80 : /** * @brief This function handles Undefined instruction or illegal state. */ void UsageFault_Handler(void) { 8001e80: b480 push {r7} 8001e82: af00 add r7, sp, #0 /* USER CODE BEGIN UsageFault_IRQn 0 */ /* USER CODE END UsageFault_IRQn 0 */ while (1) { } 8001e84: e7fe b.n 8001e84 8001e86: bf00 nop 08001e88 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8001e88: b480 push {r7} 8001e8a: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8001e8c: 46bd mov sp, r7 8001e8e: f85d 7b04 ldr.w r7, [sp], #4 8001e92: 4770 bx lr 08001e94 : /** * @brief This function handles Debug monitor. */ void DebugMon_Handler(void) { 8001e94: b480 push {r7} 8001e96: af00 add r7, sp, #0 /* USER CODE END DebugMonitor_IRQn 0 */ /* USER CODE BEGIN DebugMonitor_IRQn 1 */ /* USER CODE END DebugMonitor_IRQn 1 */ } 8001e98: 46bd mov sp, r7 8001e9a: f85d 7b04 ldr.w r7, [sp], #4 8001e9e: 4770 bx lr 08001ea0 : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8001ea0: b480 push {r7} 8001ea2: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8001ea4: 46bd mov sp, r7 8001ea6: f85d 7b04 ldr.w r7, [sp], #4 8001eaa: 4770 bx lr 08001eac : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8001eac: b580 push {r7, lr} 8001eae: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8001eb0: f7fe fa14 bl 80002dc HAL_SYSTICK_IRQHandler(); 8001eb4: f7fe fb2a bl 800050c /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8001eb8: bd80 pop {r7, pc} 8001eba: bf00 nop 08001ebc : * @param None * @retval None */ void SystemInit(void) { 8001ebc: b480 push {r7} 8001ebe: af00 add r7, sp, #0 /* FPU settings ------------------------------------------------------------*/ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ 8001ec0: 4a16 ldr r2, [pc, #88] ; (8001f1c ) 8001ec2: 4b16 ldr r3, [pc, #88] ; (8001f1c ) 8001ec4: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 8001ec8: f443 0370 orr.w r3, r3, #15728640 ; 0xf00000 8001ecc: f8c2 3088 str.w r3, [r2, #136] ; 0x88 #endif /* Reset the RCC clock configuration to the default reset state ------------*/ /* Set MSION bit */ RCC->CR |= RCC_CR_MSION; 8001ed0: 4a13 ldr r2, [pc, #76] ; (8001f20 ) 8001ed2: 4b13 ldr r3, [pc, #76] ; (8001f20 ) 8001ed4: 681b ldr r3, [r3, #0] 8001ed6: f043 0301 orr.w r3, r3, #1 8001eda: 6013 str r3, [r2, #0] /* Reset CFGR register */ RCC->CFGR = 0x00000000; 8001edc: 4b10 ldr r3, [pc, #64] ; (8001f20 ) 8001ede: 2200 movs r2, #0 8001ee0: 609a str r2, [r3, #8] /* Reset HSEON, CSSON , HSION, and PLLON bits */ RCC->CR &= (uint32_t)0xEAF6FFFF; 8001ee2: 4a0f ldr r2, [pc, #60] ; (8001f20 ) 8001ee4: 4b0e ldr r3, [pc, #56] ; (8001f20 ) 8001ee6: 681b ldr r3, [r3, #0] 8001ee8: f023 53a8 bic.w r3, r3, #352321536 ; 0x15000000 8001eec: f423 2310 bic.w r3, r3, #589824 ; 0x90000 8001ef0: 6013 str r3, [r2, #0] /* Reset PLLCFGR register */ RCC->PLLCFGR = 0x00001000; 8001ef2: 4b0b ldr r3, [pc, #44] ; (8001f20 ) 8001ef4: f44f 5280 mov.w r2, #4096 ; 0x1000 8001ef8: 60da str r2, [r3, #12] /* Reset HSEBYP bit */ RCC->CR &= (uint32_t)0xFFFBFFFF; 8001efa: 4a09 ldr r2, [pc, #36] ; (8001f20 ) 8001efc: 4b08 ldr r3, [pc, #32] ; (8001f20 ) 8001efe: 681b ldr r3, [r3, #0] 8001f00: f423 2380 bic.w r3, r3, #262144 ; 0x40000 8001f04: 6013 str r3, [r2, #0] /* Disable all interrupts */ RCC->CIER = 0x00000000; 8001f06: 4b06 ldr r3, [pc, #24] ; (8001f20 ) 8001f08: 2200 movs r2, #0 8001f0a: 619a str r2, [r3, #24] /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 8001f0c: 4b03 ldr r3, [pc, #12] ; (8001f1c ) 8001f0e: f04f 6200 mov.w r2, #134217728 ; 0x8000000 8001f12: 609a str r2, [r3, #8] #endif } 8001f14: 46bd mov sp, r7 8001f16: f85d 7b04 ldr.w r7, [sp], #4 8001f1a: 4770 bx lr 8001f1c: e000ed00 .word 0xe000ed00 8001f20: 40021000 .word 0x40021000 08001f24 : 8001f24: 4601 mov r1, r0 8001f26: 2000 movs r0, #0 8001f28: 4602 mov r2, r0 8001f2a: 4603 mov r3, r0 8001f2c: f000 b83e b.w 8001fac <__register_exitproc> 08001f30 <__libc_fini_array>: 8001f30: b538 push {r3, r4, r5, lr} 8001f32: 4b08 ldr r3, [pc, #32] ; (8001f54 <__libc_fini_array+0x24>) 8001f34: 4d08 ldr r5, [pc, #32] ; (8001f58 <__libc_fini_array+0x28>) 8001f36: 1aed subs r5, r5, r3 8001f38: 10ac asrs r4, r5, #2 8001f3a: bf18 it ne 8001f3c: 18ed addne r5, r5, r3 8001f3e: d005 beq.n 8001f4c <__libc_fini_array+0x1c> 8001f40: 3c01 subs r4, #1 8001f42: f855 3d04 ldr.w r3, [r5, #-4]! 8001f46: 4798 blx r3 8001f48: 2c00 cmp r4, #0 8001f4a: d1f9 bne.n 8001f40 <__libc_fini_array+0x10> 8001f4c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} 8001f50: f000 b88e b.w 8002070 <_fini> 8001f54: 080020d0 .word 0x080020d0 8001f58: 080020d4 .word 0x080020d4 08001f5c <__libc_init_array>: 8001f5c: b570 push {r4, r5, r6, lr} 8001f5e: 4e0f ldr r6, [pc, #60] ; (8001f9c <__libc_init_array+0x40>) 8001f60: 4d0f ldr r5, [pc, #60] ; (8001fa0 <__libc_init_array+0x44>) 8001f62: 1b76 subs r6, r6, r5 8001f64: 10b6 asrs r6, r6, #2 8001f66: bf18 it ne 8001f68: 2400 movne r4, #0 8001f6a: d005 beq.n 8001f78 <__libc_init_array+0x1c> 8001f6c: 3401 adds r4, #1 8001f6e: f855 3b04 ldr.w r3, [r5], #4 8001f72: 4798 blx r3 8001f74: 42a6 cmp r6, r4 8001f76: d1f9 bne.n 8001f6c <__libc_init_array+0x10> 8001f78: 4e0a ldr r6, [pc, #40] ; (8001fa4 <__libc_init_array+0x48>) 8001f7a: 4d0b ldr r5, [pc, #44] ; (8001fa8 <__libc_init_array+0x4c>) 8001f7c: 1b76 subs r6, r6, r5 8001f7e: f000 f871 bl 8002064 <_init> 8001f82: 10b6 asrs r6, r6, #2 8001f84: bf18 it ne 8001f86: 2400 movne r4, #0 8001f88: d006 beq.n 8001f98 <__libc_init_array+0x3c> 8001f8a: 3401 adds r4, #1 8001f8c: f855 3b04 ldr.w r3, [r5], #4 8001f90: 4798 blx r3 8001f92: 42a6 cmp r6, r4 8001f94: d1f9 bne.n 8001f8a <__libc_init_array+0x2e> 8001f96: bd70 pop {r4, r5, r6, pc} 8001f98: bd70 pop {r4, r5, r6, pc} 8001f9a: bf00 nop 8001f9c: 080020c8 .word 0x080020c8 8001fa0: 080020c8 .word 0x080020c8 8001fa4: 080020d0 .word 0x080020d0 8001fa8: 080020c8 .word 0x080020c8 08001fac <__register_exitproc>: 8001fac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} 8001fb0: 4c25 ldr r4, [pc, #148] ; (8002048 <__register_exitproc+0x9c>) 8001fb2: 6825 ldr r5, [r4, #0] 8001fb4: f8d5 4148 ldr.w r4, [r5, #328] ; 0x148 8001fb8: 4606 mov r6, r0 8001fba: 4688 mov r8, r1 8001fbc: 4692 mov sl, r2 8001fbe: 4699 mov r9, r3 8001fc0: b3cc cbz r4, 8002036 <__register_exitproc+0x8a> 8001fc2: 6860 ldr r0, [r4, #4] 8001fc4: 281f cmp r0, #31 8001fc6: dc18 bgt.n 8001ffa <__register_exitproc+0x4e> 8001fc8: 1c43 adds r3, r0, #1 8001fca: b17e cbz r6, 8001fec <__register_exitproc+0x40> 8001fcc: eb04 0580 add.w r5, r4, r0, lsl #2 8001fd0: 2101 movs r1, #1 8001fd2: f8c5 a088 str.w sl, [r5, #136] ; 0x88 8001fd6: f8d4 7188 ldr.w r7, [r4, #392] ; 0x188 8001fda: fa01 f200 lsl.w r2, r1, r0 8001fde: 4317 orrs r7, r2 8001fe0: 2e02 cmp r6, #2 8001fe2: f8c4 7188 str.w r7, [r4, #392] ; 0x188 8001fe6: f8c5 9108 str.w r9, [r5, #264] ; 0x108 8001fea: d01e beq.n 800202a <__register_exitproc+0x7e> 8001fec: 3002 adds r0, #2 8001fee: 6063 str r3, [r4, #4] 8001ff0: f844 8020 str.w r8, [r4, r0, lsl #2] 8001ff4: 2000 movs r0, #0 8001ff6: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8001ffa: 4b14 ldr r3, [pc, #80] ; (800204c <__register_exitproc+0xa0>) 8001ffc: b303 cbz r3, 8002040 <__register_exitproc+0x94> 8001ffe: f44f 70c8 mov.w r0, #400 ; 0x190 8002002: f3af 8000 nop.w 8002006: 4604 mov r4, r0 8002008: b1d0 cbz r0, 8002040 <__register_exitproc+0x94> 800200a: f8d5 3148 ldr.w r3, [r5, #328] ; 0x148 800200e: 2700 movs r7, #0 8002010: e880 0088 stmia.w r0, {r3, r7} 8002014: f8c5 4148 str.w r4, [r5, #328] ; 0x148 8002018: 4638 mov r0, r7 800201a: 2301 movs r3, #1 800201c: f8c4 7188 str.w r7, [r4, #392] ; 0x188 8002020: f8c4 718c str.w r7, [r4, #396] ; 0x18c 8002024: 2e00 cmp r6, #0 8002026: d0e1 beq.n 8001fec <__register_exitproc+0x40> 8002028: e7d0 b.n 8001fcc <__register_exitproc+0x20> 800202a: f8d4 118c ldr.w r1, [r4, #396] ; 0x18c 800202e: 430a orrs r2, r1 8002030: f8c4 218c str.w r2, [r4, #396] ; 0x18c 8002034: e7da b.n 8001fec <__register_exitproc+0x40> 8002036: f505 74a6 add.w r4, r5, #332 ; 0x14c 800203a: f8c5 4148 str.w r4, [r5, #328] ; 0x148 800203e: e7c0 b.n 8001fc2 <__register_exitproc+0x16> 8002040: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff 8002044: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} 8002048: 080020c4 .word 0x080020c4 800204c: 00000000 .word 0x00000000 08002050 : 8002050: 4b02 ldr r3, [pc, #8] ; (800205c ) 8002052: b113 cbz r3, 800205a 8002054: 4802 ldr r0, [pc, #8] ; (8002060 ) 8002056: f7ff bf65 b.w 8001f24 800205a: 4770 bx lr 800205c: 00000000 .word 0x00000000 8002060: 08001f31 .word 0x08001f31 08002064 <_init>: 8002064: b5f8 push {r3, r4, r5, r6, r7, lr} 8002066: bf00 nop 8002068: bcf8 pop {r3, r4, r5, r6, r7} 800206a: bc08 pop {r3} 800206c: 469e mov lr, r3 800206e: 4770 bx lr 08002070 <_fini>: 8002070: b5f8 push {r3, r4, r5, r6, r7, lr} 8002072: bf00 nop 8002074: bcf8 pop {r3, r4, r5, r6, r7} 8002076: bc08 pop {r3} 8002078: 469e mov lr, r3 800207a: 4770 bx lr 800207c: 0000 movs r0, r0 ...