# Register addresses					#Keil (main:start)
set RCC_APB2ENR          0x40021018		#0x0
set AFIO_MAPR            0x40010004		#0x0
set DBGMCU_CR            0xe0042004		#0xE7
set COREDEBUG_DEMCR      0xe000edfc		#0x01000000

set TPI_ACPR             0xe0040010		#0x0		//0 bei synchronous mode
set TPI_SPPR             0xe00400f0		#0x0
set TPI_FFCR             0xe0040304		#0x102
TPIU_SSPSR				 0xE0040000		#0x0B
TPIU_CSPSR				 0xE0040004		#0x01
TRIGGER					 0xE0040EE8		#0x0
FIFO data 0				 0xE0040EEC		#0x0

set DWT_CTRL             0xe0001000		#0x4005061F		--T32


set ITM_LAR              0xe0000fb0		#0x0
set ITM_TCR              0xe0000e80		#0x0001000D		--T32
set ITM_TER              0xe0000e00		#0xFFFFFFFF		--T32
TPR						 0xE0000E40		#0x0F


set ETM_LAR              0xe0041fb0		#0x0
set ETM_CR               0xe0041000		#0x00000910		--T32: 0x0410
set ETM_CCR				 0xE0041004     #0x8C840000	//RO
set ETM_TRIG			 0xE0041008		#0x000077FF		--T32: 0x77EF
ETM_SR					 0xE0041010		#0x0
ETM_SCR					 0xE0041014		#0x???			--T32: 0x00020D09
ETMTEEVR				 0xE0041020		#0x0000006F		--T32: ????
ETMTECR1				 0xE0041024		#0x0
ETMFFLR					 0xE0041028		#0x0
ETMCNTRLDVR1			 0xE0041140		#0x0
ETMSYNCFR				 0xE00411E0		#sync frequency register
ETMIDR					 0xE00411E4		#4114F242
ETMCCER				 	 0xE00411E8		#0x00018800
ETMTESSEICR				 0xE00411F0		#0x0
ETMTSEVR				 0xE00411F8		#0x0
ETMTRACEIDR				 0xE0041200		#0x02			--T32: 0x01
ETMIDR2					 0xE0041208		#0x00
ETMPDSR					 0xE0041314		#0x01
ITMISCIN  				 0xE0041EE0		#0x10
ITTRIGOUT				 0xE0041EE8		#0x0
ETM_ITATBCTR2			 0xE0041EF0		#0x01		//RO
ETM_ITATBCTR0			 0xE0041EF8		#0x00		//WO
ETMITCTRL				 0xE0041F00		#0x0
ETMCLAIMSET				 0xE0041FA0		#0x0F
ETMCLAIMCLR				 0xE0041FA4		#0x0
ETMLAR					 0xE0041FB0		#0x0 		//lock Access reg
ETMLSR					 0xE0041FB4		#0x01
ETMAUTHSTATUS			 0xE0041FB8		#0xC0
ETMDEVTYPE				 0xE0041FCC		#0x13		//default

set ETM_TRACEIDR         0xe0041200		#0x02
set ETM_TECR1            0xe0041024		#0x0
set ETM_FFRR             0xe0041028		#0x0
set ETM_FFLR             0xe004102c		#0x0

# Stop the CPU while we configure
init
halt

# STM32 IO pin config
setbits $RCC_APB2ENR 1                     ;# AFIOEN
setbits $AFIO_MAPR 0x2000000               ;# Disable JTAG
setbits $DBGMCU_CR 0x20                    ;# Enable trace IO pins

# TPIU config
setbits $COREDEBUG_DEMCR 0x1000000         ;# Enable access to trace regs
mww $TPI_ACPR 0                            ;# Trace clock divider HCLK/(x+1)
mww $TPI_SPPR 2                            ;# Pin protocol = NRZ/USART
mww $TPI_FFCR 0x102                        ;# Enable TPIU framing (0x100 to disable)

# DWT config
mww $DWT_CTRL 0x40011a01                   ;# 1/512 PC sampling, exc trace

# ITM config
mww $ITM_LAR 0xC5ACCE55
mww $ITM_TCR 0x0001000d                    ;# TraceBusID 1, enable dwt/itm/sync
mww $ITM_TER 0xffffffff                    ;# Enable all stimulus ports

# ETM config
mww $ETM_LAR 0xC5ACCE55
setbits $ETM_CR 0x400                      ;# ETM programming mode
mww $ETM_CR 0xd80                          ;# Stall processor, report all branches
# mww $ETM_CR 0x800                        ;# No stalling, only indirect branches
mww $ETM_TRACEIDR 2                        ;# TraceBusID 2
mww $ETM_TECR1 0x1000000                   ;# Trace always enabled
mww $ETM_FFRR 0x1000000                    ;# Stalling always enabled
mww $ETM_FFLR 24                           ;# Stall when less than N bytes free in FIFO (1..24)
# clearbits $ETM_CR 0x400                  ;# Start tracing

# Resume CPU and exit openocd
resume
shutdown