module fpgatest( input wire FPGA_CLK1_50, output wire [3:0] GPIO_1); assign clock_in = FPGA_CLK1_50; assign GPIO_1[1] = clock_out; reg [15:0] divider; initial divider = 2000; wire clock_in; wire clock_out; clockdiv_variabel #(.WIDTH(16)) clockdiv_variabel0 ( .divider(divider), .clock_in(clock_in), .clock_out(clock_out)); endmodule