Xilinx Design Summary

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	36	3,840	1%
Number of 4 input LUTs	53	3,840	1%
Logic Distribution
Number of occupied Slices	39	1,920	2%
Number of Slices containing only related logic	39	39	100%
Number of Slices containing unrelated logic	0	39	0%
Total Number of 4 input LUTs	53	3,840	1%
Number of bonded IOBs	2	97	2%
Number of GCLKs	1	8	12%
Number of RPM macros	36
Total equivalent gate count for design	609
Additional JTAG gate count for IOBs	96

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met