#----------------------------------------------------------- # Vivado v2016.4 (64-bit) # SW Build 1756540 on Mon Jan 23 19:11:23 MST 2017 # IP Build 1755317 on Mon Jan 23 20:30:07 MST 2017 # Start of session at: Wed Mar 08 12:20:48 2017 # Process ID: 11372 # Current directory: C:/Users/test/Desktop/24BitAnLV/23.02LV.runs/synth_1 # Command line: vivado.exe -log clk_ip_arty.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_ip_arty.tcl # Log file: C:/Users/test/Desktop/24BitAnLV/23.02LV.runs/synth_1/clk_ip_arty.vds # Journal file: C:/Users/test/Desktop/24BitAnLV/23.02LV.runs/synth_1\vivado.jou #----------------------------------------------------------- source clk_ip_arty.tcl -notrace Command: synth_design -top clk_ip_arty -part xc7a35tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a35t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a35t' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 11792 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:06 . Memory (MB): peak = 288.391 ; gain = 79.063 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'clk_ip_arty' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/clk_ip_arty.vhd:87] Parameter DATA_WIDTH bound to: 24 - type: integer INFO: [Synth 8-3491] module 'clk_wiz_0' declared at 'C:/Users/test/Desktop/24BitAnLV/23.02LV.runs/synth_1/.Xil/Vivado-11372-DESKTOP-V6B91O8/realtime/clk_wiz_0_stub.vhdl:5' bound to instance 'myclk' of component 'clk_wiz_0' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/clk_ip_arty.vhd:207] INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [C:/Users/test/Desktop/24BitAnLV/23.02LV.runs/synth_1/.Xil/Vivado-11372-DESKTOP-V6B91O8/realtime/clk_wiz_0_stub.vhdl:13] WARNING: [Synth 8-5640] Port 'valid_eth' is missing in component declaration [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/clk_ip_arty.vhd:116] INFO: [Synth 8-3491] module 'ethernet_test' declared at 'C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/ethernet_test.vhd:20' bound to instance 'MyEthernet' of component 'ethernet_test' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/clk_ip_arty.vhd:218] INFO: [Synth 8-638] synthesizing module 'ethernet_test' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/ethernet_test.vhd:54] Parameter eth_src_mac bound to: 48'b000000001010110110111110111011110000000100100011 Parameter eth_dst_mac bound to: 48'b100111000101110010001110000001111110001000001111 Parameter ip_src_addr bound to: 32'b00001010000010100000101000001010 Parameter ip_dst_addr bound to: 32'b11000000101010000110010001001111 INFO: [Synth 8-3491] module 'nibble_data' declared at 'C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/nibble_data.vhd:19' bound to instance 'data' of component 'nibble_data' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/ethernet_test.vhd:179] INFO: [Synth 8-638] synthesizing module 'nibble_data' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/nibble_data.vhd:47] Parameter eth_src_mac bound to: 48'b000000001010110110111110111011110000000100100011 Parameter eth_dst_mac bound to: 48'b100111000101110010001110000001111110001000001111 Parameter ip_src_addr bound to: 168430090 - type: integer Parameter ip_dst_addr bound to: -1062706097 - type: integer INFO: [Synth 8-256] done synthesizing module 'nibble_data' (1#1) [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/nibble_data.vhd:47] INFO: [Synth 8-3491] module 'add_seq_num' declared at 'C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/add_seq_num.vhd:13' bound to instance 'i_add_seq_num' of component 'add_seq_num' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/ethernet_test.vhd:205] INFO: [Synth 8-638] synthesizing module 'add_seq_num' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/add_seq_num.vhd:23] INFO: [Synth 8-4471] merging register 'data_enable_in_last_reg' into 'data_enable_out_reg' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/add_seq_num.vhd:35] INFO: [Synth 8-256] done synthesizing module 'add_seq_num' (2#1) [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/add_seq_num.vhd:23] INFO: [Synth 8-3491] module 'add_crc32' declared at 'C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/add_crc32 is.vhd:14' bound to instance 'i_add_crc32' of component 'add_crc32' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/ethernet_test.vhd:214] INFO: [Synth 8-638] synthesizing module 'add_crc32' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/add_crc32 is.vhd:22] INFO: [Synth 8-256] done synthesizing module 'add_crc32' (3#1) [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/add_crc32 is.vhd:22] INFO: [Synth 8-3491] module 'add_preamble' declared at 'C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/add_preamble.vhd:13' bound to instance 'i_add_preamble' of component 'add_preamble' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/ethernet_test.vhd:221] INFO: [Synth 8-638] synthesizing module 'add_preamble' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/add_preamble.vhd:21] INFO: [Synth 8-256] done synthesizing module 'add_preamble' (4#1) [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/add_preamble.vhd:21] Parameter DDR_CLK_EDGE bound to: SAME_EDGE - type: string Parameter INIT bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D1_INVERTED bound to: 1'b0 Parameter IS_D2_INVERTED bound to: 1'b0 Parameter SRTYPE bound to: SYNC - type: string INFO: [Synth 8-113] binding component instance 'clock_fwd_ddr' to cell 'ODDR' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/ethernet_test.vhd:270] INFO: [Synth 8-113] binding component instance 'i_bufg' to cell 'BUFG' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/ethernet_test.vhd:286] Parameter BANDWIDTH bound to: OPTIMIZED - type: string Parameter CLKFBOUT_MULT bound to: 8 - type: integer Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: float Parameter CLKIN1_PERIOD bound to: 10.000000 - type: float Parameter CLKOUT0_DIVIDE bound to: 32 - type: integer Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT0_PHASE bound to: 0.000000 - type: float Parameter CLKOUT1_DIVIDE bound to: 16 - type: integer Parameter CLKOUT1_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT1_PHASE bound to: 0.000000 - type: float Parameter CLKOUT2_DIVIDE bound to: 16 - type: integer Parameter CLKOUT2_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT2_PHASE bound to: 0.000000 - type: float Parameter CLKOUT3_DIVIDE bound to: 16 - type: integer Parameter CLKOUT3_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT3_PHASE bound to: 0.000000 - type: float Parameter CLKOUT4_DIVIDE bound to: 16 - type: integer Parameter CLKOUT4_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT4_PHASE bound to: 0.000000 - type: float Parameter CLKOUT5_DIVIDE bound to: 16 - type: integer Parameter CLKOUT5_DUTY_CYCLE bound to: 0.500000 - type: float Parameter CLKOUT5_PHASE bound to: 0.000000 - type: float Parameter DIVCLK_DIVIDE bound to: 1 - type: integer Parameter REF_JITTER1 bound to: 0.000000 - type: float Parameter STARTUP_WAIT bound to: FALSE - type: string INFO: [Synth 8-113] binding component instance 'clocking' to cell 'PLLE2_BASE' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/ethernet_test.vhd:287] INFO: [Synth 8-256] done synthesizing module 'ethernet_test' (5#1) [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/ethernet_test.vhd:54] Parameter DATA_WIDTH bound to: 24 - type: integer Parameter BITPERFRAME bound to: 64 - type: integer INFO: [Synth 8-3491] module 'i2s_interface' declared at 'C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/i2s.vhd:4' bound to instance 'MyI2S' of component 'i2s_interface' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/clk_ip_arty.vhd:259] INFO: [Synth 8-638] synthesizing module 'i2s_interface' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/i2s.vhd:40] Parameter DATA_WIDTH bound to: 24 - type: integer Parameter BITPERFRAME bound to: 64 - type: integer INFO: [Synth 8-256] done synthesizing module 'i2s_interface' (6#1) [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/i2s.vhd:40] WARNING: [Synth 8-614] signal 'clk6144' is read in the process but is not in the sensitivity list [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/clk_ip_arty.vhd:290] WARNING: [Synth 8-614] signal 'clk6144' is read in the process but is not in the sensitivity list [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/clk_ip_arty.vhd:304] WARNING: [Synth 8-3848] Net shift_data_out_test in module/entity clk_ip_arty does not have driver. [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/clk_ip_arty.vhd:53] WARNING: [Synth 8-3848] Net data_out_test_eth in module/entity clk_ip_arty does not have driver. [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/clk_ip_arty.vhd:54] INFO: [Synth 8-256] done synthesizing module 'clk_ip_arty' (7#1) [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/clk_ip_arty.vhd:87] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][23] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][22] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][21] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][20] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][19] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][18] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][17] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][16] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][15] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][14] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][13] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][12] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][11] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][10] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][9] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][8] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][7] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][6] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][5] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][4] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][3] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][2] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][1] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[336][0] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][23] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][22] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][21] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][20] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][19] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][18] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][17] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][16] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][15] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][14] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][13] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][12] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][11] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][10] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][9] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][8] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][7] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][6] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][5] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][4] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][3] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][2] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][1] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[337][0] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][23] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][22] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][21] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][20] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][19] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][18] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][17] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][16] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][15] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][14] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][13] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][12] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][11] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][10] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][9] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][8] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][7] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][6] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][5] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][4] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][3] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][2] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][1] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[338][0] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][23] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][22] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][21] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][20] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][19] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][18] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][17] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][16] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][15] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][14] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][13] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][12] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][11] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][10] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][9] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][8] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][7] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][6] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][5] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][4] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][3] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][2] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][1] WARNING: [Synth 8-3331] design nibble_data has unconnected port v1_nib[339][0] WARNING: [Synth 8-3331] design ethernet_test has unconnected port eth_mdio WARNING: [Synth 8-3331] design ethernet_test has unconnected port eth_rx_d[3] WARNING: [Synth 8-3331] design ethernet_test has unconnected port eth_rx_d[2] WARNING: [Synth 8-3331] design ethernet_test has unconnected port eth_rx_d[1] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:10 ; elapsed = 00:00:11 . Memory (MB): peak = 453.938 ; gain = 244.609 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:13 . Memory (MB): peak = 453.938 ; gain = 244.609 --------------------------------------------------------------------------------- WARNING: [Project 1-486] Could not resolve non-primitive black box cell 'clk_wiz_0' instantiated as 'myclk' [C:/Users/test/Desktop/24BitAnLV/23.02LV.srcs/sources_1/new/clk_ip_arty.vhd:207] INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Device 21-403] Loading part xc7a35tcsg324-1 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [C:/Users/test/Desktop/24BitAnLV/23.02LV.runs/synth_1/.Xil/Vivado-11372-DESKTOP-V6B91O8/dcp/clk_wiz_0_in_context.xdc] for cell 'myclk' Finished Parsing XDC File [C:/Users/test/Desktop/24BitAnLV/23.02LV.runs/synth_1/.Xil/Vivado-11372-DESKTOP-V6B91O8/dcp/clk_wiz_0_in_context.xdc] for cell 'myclk' Parsing XDC File [C:/Users/test/Desktop/newtryhzdata/constraints-arty.xdc] Finished Parsing XDC File [C:/Users/test/Desktop/newtryhzdata/constraints-arty.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [C:/Users/test/Desktop/newtryhzdata/constraints-arty.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_ip_arty_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/clk_ip_arty_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. INFO: [Timing 38-2] Deriving generated clocks Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: A total of 1 instances were transformed. PLLE2_BASE => PLLE2_ADV: 1 instances Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.013 . Memory (MB): peak = 789.250 ; gain = 0.000 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 789.250 ; gain = 579.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a35tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 789.250 ; gain = 579.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property IO_BUFFER_TYPE = NONE for clk100. (constraint file C:/Users/test/Desktop/24BitAnLV/23.02LV.runs/synth_1/.Xil/Vivado-11372-DESKTOP-V6B91O8/dcp/clk_wiz_0_in_context.xdc, line 3). Applied set_property CLOCK_BUFFER_TYPE = NONE for clk100. (constraint file C:/Users/test/Desktop/24BitAnLV/23.02LV.runs/synth_1/.Xil/Vivado-11372-DESKTOP-V6B91O8/dcp/clk_wiz_0_in_context.xdc, line 4). --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 789.250 ; gain = 579.922 --------------------------------------------------------------------------------- INFO: [Synth 8-5546] ROM "new_sample" won't be mapped to RAM because it is too sparse INFO: [Synth 8-5545] ROM "memory_top_reg[0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[0]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[1]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[2]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[3]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[4]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[5]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[6]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[7]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[8]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[8]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[8]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[8]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[9]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[9]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[9]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[9]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[10]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[10]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[10]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[10]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[11]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[11]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[11]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[11]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[12]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[12]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[12]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[12]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[13]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[13]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[13]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[13]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[14]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[14]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[14]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[14]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[15]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[15]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[15]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[15]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[16]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[16]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[16]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[16]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[17]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[17]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[17]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[17]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[18]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[18]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[18]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[18]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[19]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[19]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[19]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[19]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[20]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[20]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[20]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[20]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[21]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[21]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[21]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[21]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[22]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[22]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[22]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[22]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[23]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[23]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[23]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[23]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[24]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[24]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[24]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Synth 8-5545] ROM "memory_top_reg[24]" won't be mapped to RAM because address size (32) is larger than maximum supported(25) INFO: [Common 17-14] Message 'Synth 8-5545' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:40 ; elapsed = 00:00:41 . Memory (MB): peak = 789.250 ; gain = 579.922 --------------------------------------------------------------------------------- Report RTL Partitions: +------+-----------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------+------------+----------+ |1 |clk_ip_arty__GB0 | 1| 36791| |2 |clk_ip_arty__GB1 | 1| 11175| |3 |clk_ip_arty__GB2 | 1| 17829| |4 |clk_ip_arty__GB3 | 1| 18315| |5 |clk_ip_arty__GB4 | 1| 19291| |6 |clk_ip_arty__GB5 | 1| 22947| |7 |clk_ip_arty__GB6 | 1| 28350| |8 |clk_ip_arty__GB7 | 1| 34941| +------+-----------------+------------+----------+ --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 3 2 Input 12 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 5 Bit Adders := 1 2 Input 3 Bit Adders := 1 +---XORs : 2 Input 32 Bit XORs := 4 +---Registers : 64 Bit Registers := 1 32 Bit Registers := 1 25 Bit Registers := 1 24 Bit Registers := 1020 16 Bit Registers := 1 12 Bit Registers := 5 8 Bit Registers := 1 7 Bit Registers := 1 5 Bit Registers := 1 4 Bit Registers := 4 3 Bit Registers := 1 1 Bit Registers := 27 +---ROMs : ROMs := 1 +---Muxes : 2 Input 32 Bit Muxes := 5 2 Input 24 Bit Muxes := 1020 2111 Input 12 Bit Muxes := 1 2 Input 5 Bit Muxes := 2 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 8 2 Input 3 Bit Muxes := 1 2111 Input 1 Bit Muxes := 1 2 Input 1 Bit Muxes := 7 4 Input 1 Bit Muxes := 1 5 Input 1 Bit Muxes := 340 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module clk_ip_arty Detailed RTL Component Info : +---Adders : 2 Input 32 Bit Adders := 3 2 Input 7 Bit Adders := 1 +---Registers : 24 Bit Registers := 680 7 Bit Registers := 1 1 Bit Registers := 3 +---Muxes : 2 Input 24 Bit Muxes := 1020 5 Input 1 Bit Muxes := 340 Module nibble_data Detailed RTL Component Info : +---Adders : 2 Input 12 Bit Adders := 1 +---Registers : 24 Bit Registers := 336 12 Bit Registers := 5 4 Bit Registers := 1 1 Bit Registers := 3 +---ROMs : ROMs := 1 +---Muxes : 2111 Input 12 Bit Muxes := 1 2111 Input 1 Bit Muxes := 1 Module add_seq_num Detailed RTL Component Info : +---Adders : 2 Input 3 Bit Adders := 1 +---Registers : 4 Bit Registers := 1 3 Bit Registers := 1 1 Bit Registers := 2 +---Muxes : 4 Input 4 Bit Muxes := 1 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 2 4 Input 1 Bit Muxes := 1 Module add_crc32 Detailed RTL Component Info : +---XORs : 2 Input 32 Bit XORs := 4 +---Registers : 32 Bit Registers := 1 8 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 32 Bit Muxes := 5 2 Input 4 Bit Muxes := 2 2 Input 1 Bit Muxes := 1 Module add_preamble Detailed RTL Component Info : +---Registers : 64 Bit Registers := 1 16 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 1 +---Muxes : 2 Input 4 Bit Muxes := 4 2 Input 3 Bit Muxes := 1 2 Input 1 Bit Muxes := 1 Module ethernet_test Detailed RTL Component Info : +---Registers : 25 Bit Registers := 1 1 Bit Registers := 6 Module i2s_interface Detailed RTL Component Info : +---Adders : 2 Input 5 Bit Adders := 1 +---Registers : 24 Bit Registers := 4 5 Bit Registers := 1 1 Bit Registers := 11 +---Muxes : 2 Input 5 Bit Muxes := 2 2 Input 1 Bit Muxes := 3 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 90 (col length:60) BRAMs: 100 (col length: RAMB18 60 RAMB36 30) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- INFO: [Synth 8-5580] Multithreading enabled for synth_design using a maximum of 2 processes. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. INFO: [Synth 8-3333] propagating constant 0 across sequential element (MyEthernet/data/user_data_reg) INFO: [Synth 8-3886] merging instance 'MyEthernet/max_count_reg[22]' (FD) to 'MyEthernet/max_count_reg[24]' WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[11]) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[10]) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[9]) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[8]) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[7]) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[6]) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[5]) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[4]) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[3]) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[2]) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[1]) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[0]) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (busy_reg) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[11]__0) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[10]__0) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[9]__0) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[8]__0) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[7]__0) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[6]__0) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[5]__0) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[4]__0) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[3]__0) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[2]__0) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[1]__0) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (counter_reg_rep[0]__0) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (user_data_reg) is unused and will be removed from module nibble_data. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/user_data_counter_reg[2]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/user_data_counter_reg[1]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/user_data_counter_reg[0]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[0]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[1]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[2]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[3]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[4]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[5]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[6]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[7]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[8]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[9]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[10]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[11]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[12]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[13]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[14]) is unused and will be removed from module ethernet_test. WARNING: [Synth 8-3332] Sequential element (i_add_seq_num/sequence_num_reg[15]) is unused and will be removed from module ethernet_test. INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\counter1_top_reg[0] ) INFO: [Synth 8-3333] propagating constant 0 across sequential element (i_0/\counter1_top_reg[1] ) --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:13 ; elapsed = 00:01:28 . Memory (MB): peak = 789.250 ; gain = 579.922 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- ROM: +------------+----------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +------------+----------------+---------------+----------------+ |nibble_data | busy | 4096x1 | LUT | |nibble_data | user_data | 4096x1 | LUT | |nibble_data | data_valid | 4096x1 | LUT | |nibble_data | data_valid_reg | 4096x1 | Block RAM | +------------+----------------+---------------+----------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Report RTL Partitions: +------+-----------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------+------------+----------+ |1 |clk_ip_arty__GB0 | 1| 29986| |2 |clk_ip_arty__GB1 | 1| 9725| |3 |clk_ip_arty__GB2 | 1| 16145| |4 |clk_ip_arty__GB3 | 1| 16062| |5 |clk_ip_arty__GB4 | 1| 1274| |6 |clk_ip_arty__GB5 | 1| 1078| |7 |clk_ip_arty__GB6 | 1| 1111| |8 |clk_ip_arty__GB7 | 1| 479| +------+-----------------+------------+----------+ --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- INFO: [Synth 8-5578] Moved timing constraint from pin 'myclk/clk_out1' to pin 'myclk/bbstub_clk_out1/O' WARNING: [Synth 8-565] redefining clock 'clk100' INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:23 ; elapsed = 00:01:39 . Memory (MB): peak = 796.293 ; gain = 586.965 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:31 ; elapsed = 00:01:46 . Memory (MB): peak = 830.918 ; gain = 621.590 --------------------------------------------------------------------------------- Report RTL Partitions: +------+-----------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------+------------+----------+ |1 |clk_ip_arty__GB0 | 1| 28835| |2 |clk_ip_arty__GB1 | 1| 7426| |3 |clk_ip_arty__GB2 | 1| 12750| |4 |clk_ip_arty__GB3 | 1| 12317| |5 |clk_ip_arty__GB4 | 1| 951| |6 |clk_ip_arty__GB5 | 1| 871| |7 |clk_ip_arty__GB6 | 1| 995| |8 |clk_ip_arty__GB7 | 1| 469| +------+-----------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- INFO: [Synth 8-4480] The timing for the instance i_0/MyEthernet/data/data_valid_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:01:44 ; elapsed = 00:01:59 . Memory (MB): peak = 843.227 ; gain = 633.898 --------------------------------------------------------------------------------- Report RTL Partitions: +------+-----------------+------------+----------+ | |RTL Partition |Replication |Instances | +------+-----------------+------------+----------+ |1 |clk_ip_arty__GB0 | 1| 21770| |2 |clk_ip_arty__GB2 | 1| 7147| |3 |clk_ip_arty__GB3 | 1| 7320| +------+-----------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- INFO: [Synth 8-4480] The timing for the instance MyEthernet/data/data_valid_reg (implemented as a block RAM) might be sub-optimal as no optional output register could be merged into the block ram. Providing additional output register may help in improving timing. --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:01:56 ; elapsed = 00:02:11 . Memory (MB): peak = 843.227 ; gain = 633.898 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:01:56 ; elapsed = 00:02:12 . Memory (MB): peak = 843.227 ; gain = 633.898 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:02:01 ; elapsed = 00:02:17 . Memory (MB): peak = 843.227 ; gain = 633.898 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:02:02 ; elapsed = 00:02:17 . Memory (MB): peak = 843.227 ; gain = 633.898 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:02:05 ; elapsed = 00:02:20 . Memory (MB): peak = 843.227 ; gain = 633.898 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:02:05 ; elapsed = 00:02:20 . Memory (MB): peak = 843.227 ; gain = 633.898 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- Static Shift Register Report: +------------+-----------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |Module Name | RTL Name | Length | Width | Reset Signal | Pull out first Reg | Pull out last Reg | SRL16E | SRLC32E | +------------+-----------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ |clk_ip_arty | MyEthernet/i_add_preamble/delay_data_enable_reg[14] | 15 | 1 | NO | NO | YES | 1 | 0 | |clk_ip_arty | MyEthernet/i_add_preamble/delay_data_reg[63] | 17 | 4 | NO | NO | YES | 4 | 0 | |clk_ip_arty | valid_top_syn_reg | 3 | 1 | NO | NO | YES | 1 | 0 | +------------+-----------------------------------------------------+--------+-------+--------------+--------------------+-------------------+--------+---------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP and Shift Register Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +------+--------------+----------+ | |BlackBox name |Instances | +------+--------------+----------+ |1 |clk_wiz_0 | 1| +------+--------------+----------+ Report Cell Usage: +------+---------------+------+ | |Cell |Count | +------+---------------+------+ |1 |clk_wiz_0_bbox | 1| |2 |BUFG | 2| |3 |CARRY4 | 2336| |4 |LUT1 | 354| |5 |LUT2 | 894| |6 |LUT3 | 12200| |7 |LUT4 | 189| |8 |LUT5 | 4418| |9 |LUT6 | 4557| |10 |MUXF7 | 1072| |11 |MUXF8 | 532| |12 |ODDR | 1| |13 |PLLE2_BASE | 1| |14 |RAMB18E1 | 1| |15 |SRL16E | 6| |16 |FDRE | 24608| |17 |FDSE | 8| |18 |IBUF | 9| |19 |OBUF | 10| |20 |OBUFT | 2| +------+---------------+------+ Report Instance Areas: +------+-------------------+--------------+------+ | |Instance |Module |Cells | +------+-------------------+--------------+------+ |1 |top | | 51201| |2 | MyEthernet |ethernet_test | 12227| |3 | data |nibble_data | 11929| |4 | i_add_crc32 |add_crc32 | 57| |5 | i_add_preamble |add_preamble | 23| |6 | i_add_seq_num |add_seq_num | 27| |7 | MyI2S |i2s_interface | 11911| +------+-------------------+--------------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:02:05 ; elapsed = 00:02:20 . Memory (MB): peak = 843.227 ; gain = 633.898 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 148 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:01:43 ; elapsed = 00:02:07 . Memory (MB): peak = 843.227 ; gain = 293.207 Synthesis Optimization Complete : Time (s): cpu = 00:02:05 ; elapsed = 00:02:21 . Memory (MB): peak = 843.227 ; gain = 633.898 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 2348 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-140] Inserted 1 IBUFs to IO ports without IO buffers. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: A total of 1 instances were transformed. PLLE2_BASE => PLLE2_ADV: 1 instances INFO: [Common 17-83] Releasing license: Synthesis 163 Infos, 152 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:02:16 ; elapsed = 00:02:30 . Memory (MB): peak = 843.227 ; gain = 632.297 INFO: [Common 17-1381] The checkpoint 'C:/Users/test/Desktop/24BitAnLV/23.02LV.runs/synth_1/clk_ip_arty.dcp' has been generated. write_checkpoint: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 843.227 ; gain = 0.000 report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.306 . Memory (MB): peak = 843.227 ; gain = 0.000 INFO: [Common 17-206] Exiting Vivado at Wed Mar 08 12:23:28 2017...