library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity spi_master is Generic( F_CLK : integer := 50000000; F_SPICLK : integer := 12500000; CPOL : std_logic := '0' ); Port ( isl_clk : in STD_LOGIC; osl_ss : out STD_LOGIC; osl_sclk : out std_logic; isl_tx_en : in STD_LOGIC ; isl_dummy : in std_logic ); end spi_master; architecture Behavioral of spi_master is signal sl_sclk :std_logic := CPOL; signal i_bit_counter : integer range 0 to 7 := 0; type t_spi_states is (idle, sample, shift, spi_wait); signal spi_state : t_spi_states := idle; signal slv_dummy_sr : std_logic_vector(3 downto 0) := "0000"; begin DUMMY_PROCESS : process begin wait until rising_edge(isl_clk); slv_dummy_sr <= slv_dummy_sr(2 downto 0) & isl_dummy; end process DUMMY_PROCESS; osl_sclk <= sl_sclk; spi : process begin wait until rising_edge(isl_clk); case spi_state is when idle => i_bit_counter <= 0; osl_ss <= '1'; if( isl_tx_en = '1' ) then --muss nicht synchronisiert werden, weil es irgendwo aus der Taktdomände des fpga kommt? osl_ss <= '0'; spi_state <= sample; end if; when sample => sl_sclk <= not sl_sclk; spi_state <= shift; when shift => sl_sclk <= not sl_sclk; if( i_bit_counter < 7 ) then i_bit_counter <= i_bit_counter + 1; spi_state <= sample; else spi_state <= spi_wait; end if; when spi_wait => osl_ss <= '1'; --ein Takt später nötig? if( isl_tx_en = '0' ) then spi_state <= idle; end if; end case; end process spi; end Behavioral;