library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sram_modul is
	port(
			clk : in std_logic;
			clk_led: inout std_logic;			
						
			sram_data_led : inout std_logic_vector(0 to 4)
						
		 );
end sram_modul;





architecture Behavioral of sram_modul is
signal status: std_logic_vector(0 to 2) := "000" ;
signal write_counter: std_logic_vector(0 to 7):= "00000000" ;
signal we_oe_change : std_logic_vector(0 to 2):= "000";

begin
	process(clk)
	begin
		if clk='1' and clk'event then
			clk_led <= not clk_led;
						
			
			case we_oe_change is
			
			when "000" => 					
				if write_counter < "00001100" then
					write_counter <= write_counter + 1;  
					sram_data_led <= "00000";					
				else
					we_oe_change <= "011";
				end if;
				
			when  "001" =>
				sram_data_led <= "01010";
				
			when others =>
				sram_data_led <= "01110";	
				
			end case;
			
		end if;
	end process;
end Behavioral;