library IEEE;
use IEEE.STD_LOGIC_1164.ALL;



entity top is
 
    Generic     (
                width : integer := 32
                );
 
    Port        ( 
                SEL : in STD_LOGIC_VECTOR(width-1 downto 0);
                MMU : in STD_LOGIC_VECTOR(width-1 downto 0);
                MR : in STD_LOGIC_VECTOR(width-1 downto 0);
                MW : in STD_LOGIC_VECTOR(width-1 downto 0);
                SR : out STD_LOGIC_VECTOR(width-1 downto 0);
                SW : out STD_LOGIC_VECTOR(width-1 downto 0)
                );          
end top;

architecture STRUCTURE of top is

    component ADDREN_READ_WRITE is
    
    port        (   
                SEL:     in std_logic;
                MMU:       in std_logic;
                MR:        in std_logic;
                MW:       in std_logic;
                SR:         out std_logic;
                SW:        out std_logic
                
                
                );
    end component ADDREN_READ_WRITE;

type slv32_t is array (natural range <>) of std_logic_vector(31 downto 0);
signal MR   : slv32_t(1 to 32); 


begin



GEN:
for i in 1 to 32 generate

    proc_read_write: component ADDREN_READ_WRITE
    
    port map    (
                SEL => SEL(i), 
                MMU => MMU(i), 
                MR => MR(i),
                MW => MW(i),
                SR => SR(i),
                SW => SW(i)
                );
end generate;

end STRUCTURE;


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ADDREN_READ_WRITE is

    port        (   
                SEL: in std_logic;
                MMU: in std_logic;
                MR: in std_logic;
                MW: in std_logic;
                SR: out std_logic;
                SW: out std_logic
                );
    end;
    
architecture behavior of ADDREN_READ_WRITE is
begin

    SR <= (MMU and (not SEL)) or (MR and SEL);
    SW <= (MMU and (not SEL)) or (MW and SEL);

end behavior;