library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;



---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity sram_modul is
	port(
			clk : in std_logic;
			clk_led: out std_logic;			
			
			sram_data_led : out std_logic_vector(0 to 4)
						
		 );
end sram_modul;





architecture Behavioral of sram_modul is

signal write_counter: unsigned (7 downto 0);
signal we_oe_change : unsigned (2 downto 0);

signal sig_clk_led: std_logic;

begin
	process(clk)
	begin
		if clk='1' and clk'event then
		
			if sig_clk_led = '0' then
				sig_clk_led  <= '1';
			else
				sig_clk_led  <= '0';
			end if;
			

			
			case we_oe_change is
				
				when "000" => 					
					if write_counter < 6 then
						write_counter <= write_counter + 1;  
						sram_data_led <= "00000";					
					else
						we_oe_change <= "011";
					end if;
					
				when  "001" =>
					sram_data_led <= "01010";
					
				when others =>
					sram_data_led <= "01110";	
				
			end case;
			
		end if;
	end process;
	clk_led <= sig_clk_led;	
end Behavioral;



WARNING:Xst:646 - Signal <write_counter> is assigned but never used.
WARNING:Cpld:310 - Cannot apply TIMESPEC TS1000 = PERIOD:PERIOD_clk:0.000 nS
WARNING:Cpld:2 - Cannot apply TIMESPEC AUTO_TS_F2F =