LIBRARY ieee; USE ieee.std_logic_1164.ALL; --unterstuetzt Typcasting use ieee.NUMERIC_STD.ALL; --liefert Vektortyp signed use ieee.std_logic_signed.all; entity IIR is generic ( B0 : integer := 131319; -- Q22 B1 : integer := 262638; -- Q22 B2 : integer := 131319; -- Q22 A1 : integer := -6191086; -- Q22 A2 : integer := 3336695 -- Q22 ); port ( iCLK : in std_logic; iRESET_N : in std_logic; inewValue : in std_logic; -- indicates a new input value iIIR_RX : in std_logic_vector (47 downto 0); -- singed is expected oDone : out std_logic; oIIR_TX : out std_logic_vector (47 downto 0) ); end entity IIR; architecture BEH_FixCoefficientIIR of IIR is constant cA1 : signed(23 downto 0) := to_signed(A1,24);-- A1 Signed + Guard + Q22 constant cA2 : signed(22 downto 0) := to_signed(A2,23);-- A2 Signed + Q22 constant cB0 : signed(22 downto 0) := to_signed(B0,23);-- B0 Signed + Q22 constant cB1 : signed(22 downto 0) := to_signed(B1,23);-- B1 Signed + Q22 constant cB2 : signed(22 downto 0) := to_signed(B2,23);-- B2 Signed + Q22 signal X_B0, X_B1, X_B2 : signed(70 downto 0) := (others => '0'); -- Input Width + Coeff-Width signal X, YFB : signed(47 downto 0) := (others => '0'); -- Input Width signal Y_A1 : signed(71 downto 0) := (others => '0'); -- Input Width + Coeff-Width signal Y_A2 : signed(70 downto 0) := (others => '0'); -- Input Width + Coeff-Width signal Z2, Z1 : signed(52 downto 0) := (others => '0'); -- Input Width + 5 Guard Bits signal SUMB1_Z1, SUMB0_Z1 : signed(52 downto 0) := (others => '0'); -- Input Width + 5 Guard Bits begin X <= signed(iIIR_RX); SYNC_RD: process(iCLK) begin if (rising_edge(iCLK)) then if iRESET_N = '0' then oDone <= '0'; else oDone <= inewValue; end if; end if; end process SYNC_RD; X_B0 <= cB0 * X; X_B1 <= cB1 * X; X_B2 <= cB2 * X; Y_A1 <= cA1 * YFB; Y_A2 <= cA2 * YFB; SUMB1_Z1 <= X_B1(70 downto 18) + Z2; SUMB0_Z1 <= X_B0(70 downto 18) + Z1; YFB <= SUMB0_Z1(51 downto 4); STAGES: process(iCLK,iRESET_N) begin if (rising_edge(iCLK)) then if iRESET_N = '0' then Z2 <= (others=> '0'); Z1 <= (others=> '0'); oIIR_TX <= (others=> '0'); elsif iNewValue = '1' then Z2 <= X_B2(70 downto 18) - Y_A2(70 downto 18); -- Save Multiplikation in Z2 Z1 <= SUMB1_Z1 - Y_A1(70 downto 18); -- Save Multiplikation in Z1 oIIR_TX <= std_logic_vector(SUMB0_Z1(51 downto 4)); end if; end if; end process STAGES; end architecture BEH_FixCoefficientIIR;