Open On-Chip Debugger 0.10.0-dev-00004-gcef2a8c-dirty (2017-08-31-14:07) Licensed under GNU GPL v2 For bug reports, read http://openocd.org/doc/doxygen/bugs.html User : 13 0 command.c:546 command_print(): debug_level: 3 Debug: 14 0 configuration.c:44 add_script_search_dir(): adding C:/Users/juza/Desktop/New Folder12/Lucon_V2_Master Debug: 15 0 configuration.c:44 add_script_search_dir(): adding C:/Ac6/SystemWorkbench/plugins/fr.ac6.mcu.debug_2.1.1.201708311556/resources/openocd/st_scripts Debug: 16 0 options.c:98 add_default_dirs(): bindir=/src/staging/openocd/win32/bin Debug: 17 0 options.c:99 add_default_dirs(): pkgdatadir=/src/staging/openocd/win32/share/openocd Debug: 18 0 options.c:100 add_default_dirs(): run_prefix=C:/Ac6/SystemWorkbench/plugins/fr.ac6.mcu.externaltools.openocd.win32_1.16.0.201708311556/tools/openocd/bin Debug: 19 0 configuration.c:44 add_script_search_dir(): adding C:\Users\juza\AppData\Roaming/OpenOCD Debug: 20 0 configuration.c:44 add_script_search_dir(): adding C:/Ac6/SystemWorkbench/plugins/fr.ac6.mcu.externaltools.openocd.win32_1.16.0.201708311556/tools/openocd/bin/src/staging/openocd/win32/share/openocd/site Debug: 21 0 configuration.c:44 add_script_search_dir(): adding C:/Ac6/SystemWorkbench/plugins/fr.ac6.mcu.externaltools.openocd.win32_1.16.0.201708311556/tools/openocd/bin/src/staging/openocd/win32/share/openocd/scripts Debug: 22 16 configuration.c:84 find_file(): found Lucon_v2_Master Run.cfg Debug: 23 16 configuration.c:84 find_file(): found C:/Ac6/SystemWorkbench/plugins/fr.ac6.mcu.debug_2.1.1.201708311556/resources/openocd/st_scripts/interface/stlink.cfg Debug: 24 16 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_interface hla Debug: 25 16 command.c:145 script_debug(): command - interface ocd_interface hla Debug: 27 16 command.c:366 register_command_handler(): registering 'ocd_hla_device_desc'... Debug: 28 16 command.c:366 register_command_handler(): registering 'ocd_hla_serial'... Debug: 29 16 command.c:366 register_command_handler(): registering 'ocd_hla_layout'... Debug: 30 31 command.c:366 register_command_handler(): registering 'ocd_hla_vid_pid'... Debug: 31 31 command.c:366 register_command_handler(): registering 'ocd_hla_command'... Debug: 32 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_hla_layout stlink Debug: 33 31 command.c:145 script_debug(): command - hla_layout ocd_hla_layout stlink Debug: 35 31 hla_interface.c:241 hl_interface_handle_layout_command(): hl_interface_handle_layout_command Debug: 36 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_hla_device_desc ST-LINK/V2-1 Debug: 37 31 command.c:145 script_debug(): command - hla_device_desc ocd_hla_device_desc ST-LINK/V2-1 Debug: 39 31 hla_interface.c:215 hl_interface_handle_device_desc_command(): hl_interface_handle_device_desc_command Debug: 40 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_hla_vid_pid 0x0483 0x374b Debug: 41 31 command.c:145 script_debug(): command - hla_vid_pid ocd_hla_vid_pid 0x0483 0x374b Debug: 43 31 hla_interface.c:269 hl_interface_handle_vid_pid_command(): hl_interface_handle_vid_pid_command Debug: 44 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select hla_swd Debug: 45 31 command.c:145 script_debug(): command - ocd_transport ocd_transport select hla_swd Debug: 46 31 hla_transport.c:193 hl_transport_select(): hl_transport_select Debug: 47 31 command.c:366 register_command_handler(): registering 'ocd_hla'... Debug: 48 31 command.c:366 register_command_handler(): registering 'ocd_jtag'... Debug: 49 31 command.c:366 register_command_handler(): registering 'ocd_jtag'... Debug: 50 31 command.c:366 register_command_handler(): registering 'ocd_jtag'... Debug: 51 31 command.c:366 register_command_handler(): registering 'ocd_jtag'... Debug: 52 31 command.c:366 register_command_handler(): registering 'ocd_jtag'... Debug: 53 31 command.c:366 register_command_handler(): registering 'ocd_jtag'... Debug: 54 31 command.c:366 register_command_handler(): registering 'ocd_jtag'... Debug: 55 31 command.c:366 register_command_handler(): registering 'ocd_jtag'... Debug: 56 31 command.c:366 register_command_handler(): registering 'ocd_jtag'... Debug: 57 31 command.c:366 register_command_handler(): registering 'ocd_jtag_ntrst_delay'... Debug: 58 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_reset_config srst_only srst_nogate connect_assert_srst Debug: 59 31 command.c:145 script_debug(): command - reset_config ocd_reset_config srst_only srst_nogate connect_assert_srst User : 61 31 command.c:546 command_print(): srst_only separate srst_nogate srst_open_drain connect_assert_srst Debug: 62 31 configuration.c:84 find_file(): found C:/Ac6/SystemWorkbench/plugins/fr.ac6.mcu.debug_2.1.1.201708311556/resources/openocd/st_scripts/target/stm32f1x.cfg Debug: 63 31 configuration.c:84 find_file(): found C:/Ac6/SystemWorkbench/plugins/fr.ac6.mcu.debug_2.1.1.201708311556/resources/openocd/st_scripts/target/swj-dp.tcl Debug: 64 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 65 31 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 66 31 configuration.c:84 find_file(): found C:/Ac6/SystemWorkbench/plugins/fr.ac6.mcu.debug_2.1.1.201708311556/resources/openocd/st_scripts/mem_helper.tcl Debug: 67 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_add_usage_text mrw address Debug: 68 31 command.c:145 script_debug(): command - add_usage_text ocd_add_usage_text mrw address Debug: 70 31 command.c:1100 help_add_command(): added 'mrw' help text Debug: 71 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_add_help_text mrw Returns value of word in memory. Debug: 72 31 command.c:145 script_debug(): command - add_help_text ocd_add_help_text mrw Returns value of word in memory. Debug: 74 31 command.c:1113 help_add_command(): added 'mrw' help text Debug: 75 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_add_usage_text mmw address setbits clearbits Debug: 76 31 command.c:145 script_debug(): command - add_usage_text ocd_add_usage_text mmw address setbits clearbits Debug: 78 31 command.c:1100 help_add_command(): added 'mmw' help text Debug: 79 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_add_help_text mmw Modify word in memory. new_val = (old_val & ~clearbits) | setbits; Debug: 80 31 command.c:145 script_debug(): command - add_help_text ocd_add_help_text mmw Modify word in memory. new_val = (old_val & ~clearbits) | setbits; Debug: 82 31 command.c:1113 help_add_command(): added 'mmw' help text Debug: 83 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 84 31 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 85 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 86 31 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 87 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 88 31 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 89 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 90 31 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 91 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_hla newtap STM32F107VCTx cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x1ba01477 Debug: 92 31 command.c:145 script_debug(): command - ocd_hla ocd_hla newtap STM32F107VCTx cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id 0x1ba01477 Debug: 93 31 hla_tcl.c:118 jim_hl_newtap_cmd(): Creating New Tap, Chip: STM32F107VCTx, Tap: cpu, Dotted: STM32F107VCTx.cpu, 8 params Debug: 94 31 hla_tcl.c:128 jim_hl_newtap_cmd(): Processing option: -irlen Debug: 95 31 hla_tcl.c:128 jim_hl_newtap_cmd(): Processing option: -ircapture Debug: 96 31 hla_tcl.c:128 jim_hl_newtap_cmd(): Processing option: -irmask Debug: 97 31 hla_tcl.c:128 jim_hl_newtap_cmd(): Processing option: -expected-id Debug: 98 31 core.c:1306 jtag_tap_init(): Created Tap: STM32F107VCTx.cpu @ abs position 0, irlen 0, capture: 0x0 mask: 0x0 Debug: 99 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 100 31 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 101 31 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target create STM32F107VCTx.cpu cortex_m -endian little -chain-position STM32F107VCTx.cpu Debug: 102 31 command.c:145 script_debug(): command - ocd_target ocd_target create STM32F107VCTx.cpu cortex_m -endian little -chain-position STM32F107VCTx.cpu Info : 103 31 target.c:5223 target_create(): The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD Debug: 104 31 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas Debug: 105 47 command.c:366 register_command_handler(): registering 'ocd_arm'... Debug: 106 47 command.c:366 register_command_handler(): registering 'ocd_arm'... Debug: 107 47 command.c:366 register_command_handler(): registering 'ocd_arm'... Debug: 108 47 command.c:366 register_command_handler(): registering 'ocd_arm'... Debug: 109 47 command.c:366 register_command_handler(): registering 'ocd_arm'... Debug: 110 47 command.c:366 register_command_handler(): registering 'ocd_arm'... Debug: 111 47 command.c:366 register_command_handler(): registering 'ocd_tpiu'... Debug: 112 47 command.c:366 register_command_handler(): registering 'ocd_itm'... Debug: 113 47 command.c:366 register_command_handler(): registering 'ocd_itm'... Debug: 114 47 hla_target.c:353 adapter_target_create(): adapter_target_create Debug: 115 47 hla_target.c:324 adapter_init_arch_info(): adapter_init_arch_info Debug: 116 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 117 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 118 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 119 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 120 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 121 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 122 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 123 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 124 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 125 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 126 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 127 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 128 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 129 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 130 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 131 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 132 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 133 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 134 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 135 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 136 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 137 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 138 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 139 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 140 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 141 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 142 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 143 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 144 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 145 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 146 47 command.c:366 register_command_handler(): registering 'ocd_STM32F107VCTx.cpu'... Debug: 147 47 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu configure -work-area-phys 0x20000000 -work-area-size 0x8000 -work-area-backup 0 Debug: 148 47 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu configure -work-area-phys 0x20000000 -work-area-size 0x8000 -work-area-backup 0 Debug: 149 47 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas Debug: 150 47 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas Debug: 151 47 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas Debug: 152 47 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_flash bank STM32F107VCTx.flash stm32f1x 0x08000000 0 0 0 STM32F107VCTx.cpu Debug: 153 47 command.c:145 script_debug(): command - ocd_flash ocd_flash bank STM32F107VCTx.flash stm32f1x 0x08000000 0 0 0 STM32F107VCTx.cpu Debug: 155 47 command.c:366 register_command_handler(): registering 'ocd_stm32f1x'... Debug: 156 47 command.c:366 register_command_handler(): registering 'ocd_stm32f1x'... Debug: 157 47 command.c:366 register_command_handler(): registering 'ocd_stm32f1x'... Debug: 158 47 command.c:366 register_command_handler(): registering 'ocd_stm32f1x'... Debug: 159 47 command.c:366 register_command_handler(): registering 'ocd_stm32f1x'... Debug: 160 47 tcl.c:1031 handle_flash_bank_command(): 'stm32f1x' driver usage field missing Debug: 161 47 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 950 Debug: 162 47 command.c:145 script_debug(): command - adapter_khz ocd_adapter_khz 950 Debug: 164 47 core.c:1633 jtag_config_khz(): handle jtag khz Debug: 165 47 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 166 47 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value User : 167 47 command.c:546 command_print(): adapter speed: 950 kHz Debug: 168 47 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_adapter_nsrst_delay 100 Debug: 169 47 command.c:145 script_debug(): command - adapter_nsrst_delay ocd_adapter_nsrst_delay 100 User : 171 47 command.c:546 command_print(): adapter_nsrst_delay: 100 Debug: 172 47 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 173 63 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 174 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 175 63 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 176 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu configure -event reset-start adapter_khz 950 Debug: 177 63 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu configure -event reset-start adapter_khz 950 Debug: 178 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu configure -event reset-init global _CLOCK_FREQ adapter_khz $_CLOCK_FREQ Debug: 179 63 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu configure -event reset-init global _CLOCK_FREQ adapter_khz $_CLOCK_FREQ Debug: 180 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu configure -event examine-end global ENABLE_LOW_POWER global STOP_WATCHDOG if { [expr ($ENABLE_LOW_POWER == 1)] } { # Enable debug during low power modes (uses more power) # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP mmw 0xE0042004 0x00000007 0 } if { [expr ($ENABLE_LOW_POWER == 0)] } { # Disable debug during low power modes # DBGMCU_CR |= ~(DBG_STANDBY | DBG_STOP | DBG_SLEEP) mmw 0xE0042004 0 0x00000007 } if { [expr ($STOP_WATCHDOG == 1)] } { # Stop watchdog counters during halt # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP mmw 0xE0042004 0x00000300 0 } if { [expr ($STOP_WATCHDOG == 0)] } { # Don't stop watchdog counters during halt # DBGMCU_CR |= ~(DBG_WWDG_STOP | DBG_IWDG_STOP) mmw 0xE0042004 0 0x00000300 } Debug: 181 63 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu configure -event examine-end global ENABLE_LOW_POWER global STOP_WATCHDOG if { [expr ($ENABLE_LOW_POWER == 1)] } { # Enable debug during low power modes (uses more power) # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP mmw 0xE0042004 0x00000007 0 } if { [expr ($ENABLE_LOW_POWER == 0)] } { # Disable debug during low power modes # DBGMCU_CR |= ~(DBG_STANDBY | DBG_STOP | DBG_SLEEP) mmw 0xE0042004 0 0x00000007 } if { [expr ($STOP_WATCHDOG == 1)] } { # Stop watchdog counters during halt # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP mmw 0xE0042004 0x00000300 0 } if { [expr ($STOP_WATCHDOG == 0)] } { # Don't stop watchdog counters during halt # DBGMCU_CR |= ~(DBG_WWDG_STOP | DBG_IWDG_STOP) mmw 0xE0042004 0 0x00000300 } Debug: 182 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu configure -event gdb-attach global CONNECT_UNDER_RESET # Needed to be able to use the connect_assert_srst in reset_config # otherwise, wrong value when reading device flash size register if { [expr ($CONNECT_UNDER_RESET == 1)] } { reset init } Debug: 183 63 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu configure -event gdb-attach global CONNECT_UNDER_RESET # Needed to be able to use the connect_assert_srst in reset_config # otherwise, wrong value when reading device flash size register if { [expr ($CONNECT_UNDER_RESET == 1)] } { reset init } Debug: 184 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu configure -event trace-config # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 Debug: 185 63 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu configure -event trace-config # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync # change this value accordingly to configure trace pins # assignment mmw 0xE0042004 0x00000020 0 Debug: 186 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_init Debug: 187 63 command.c:145 script_debug(): command - init ocd_init Debug: 189 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target init Debug: 190 63 command.c:145 script_debug(): command - ocd_target ocd_target init Debug: 192 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target names Debug: 193 63 command.c:145 script_debug(): command - ocd_target ocd_target names Debug: 194 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu cget -event gdb-flash-erase-start Debug: 195 63 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu cget -event gdb-flash-erase-start Debug: 196 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu configure -event gdb-flash-erase-start reset init Debug: 197 63 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu configure -event gdb-flash-erase-start reset init Debug: 198 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu cget -event gdb-flash-write-end Debug: 199 63 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu cget -event gdb-flash-write-end Debug: 200 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu configure -event gdb-flash-write-end reset halt Debug: 201 63 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu configure -event gdb-flash-write-end reset halt Debug: 202 63 target.c:1308 handle_target_init_command(): Initializing targets... Debug: 203 63 hla_target.c:343 adapter_init_target(): adapter_init_target Debug: 204 63 command.c:366 register_command_handler(): registering 'ocd_target_request'... Debug: 205 63 command.c:366 register_command_handler(): registering 'ocd_trace'... Debug: 206 63 command.c:366 register_command_handler(): registering 'ocd_trace'... Debug: 207 63 command.c:366 register_command_handler(): registering 'ocd_fast_load_image'... Debug: 208 63 command.c:366 register_command_handler(): registering 'ocd_fast_load'... Debug: 209 63 command.c:366 register_command_handler(): registering 'ocd_profile'... Debug: 210 63 command.c:366 register_command_handler(): registering 'ocd_virt2phys'... Debug: 211 63 command.c:366 register_command_handler(): registering 'ocd_reg'... Debug: 212 63 command.c:366 register_command_handler(): registering 'ocd_poll'... Debug: 213 63 command.c:366 register_command_handler(): registering 'ocd_wait_halt'... Debug: 214 63 command.c:366 register_command_handler(): registering 'ocd_halt'... Debug: 215 63 command.c:366 register_command_handler(): registering 'ocd_resume'... Debug: 216 63 command.c:366 register_command_handler(): registering 'ocd_reset'... Debug: 217 63 command.c:366 register_command_handler(): registering 'ocd_soft_reset_halt'... Debug: 218 63 command.c:366 register_command_handler(): registering 'ocd_step'... Debug: 219 63 command.c:366 register_command_handler(): registering 'ocd_mdw'... Debug: 220 63 command.c:366 register_command_handler(): registering 'ocd_mdh'... Debug: 221 63 command.c:366 register_command_handler(): registering 'ocd_mdb'... Debug: 222 63 command.c:366 register_command_handler(): registering 'ocd_mww'... Debug: 223 63 command.c:366 register_command_handler(): registering 'ocd_mwh'... Debug: 224 63 command.c:366 register_command_handler(): registering 'ocd_mwb'... Debug: 225 63 command.c:366 register_command_handler(): registering 'ocd_bp'... Debug: 226 63 command.c:366 register_command_handler(): registering 'ocd_rbp'... Debug: 227 63 command.c:366 register_command_handler(): registering 'ocd_wp'... Debug: 228 63 command.c:366 register_command_handler(): registering 'ocd_rwp'... Debug: 229 63 command.c:366 register_command_handler(): registering 'ocd_load_image'... Debug: 230 63 command.c:366 register_command_handler(): registering 'ocd_dump_image'... Debug: 231 63 command.c:366 register_command_handler(): registering 'ocd_verify_image'... Debug: 232 63 command.c:366 register_command_handler(): registering 'ocd_test_image'... Debug: 233 63 command.c:366 register_command_handler(): registering 'ocd_reset_nag'... Debug: 234 63 command.c:366 register_command_handler(): registering 'ocd_ps'... Debug: 235 63 command.c:366 register_command_handler(): registering 'ocd_test_mem_access'... Debug: 236 63 hla_interface.c:111 hl_interface_init(): hl_interface_init Debug: 237 63 hla_layout.c:91 hl_layout_init(): hl_layout_init Debug: 238 63 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 239 63 core.c:1603 adapter_khz_to_speed(): have interface set up Debug: 240 63 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 241 63 core.c:1603 adapter_khz_to_speed(): have interface set up Info : 242 63 core.c:1388 adapter_init(): clock speed 950 kHz Debug: 243 63 openocd.c:137 handle_init_command(): Debug Adapter init complete Debug: 244 63 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport init Debug: 245 63 command.c:145 script_debug(): command - ocd_transport ocd_transport init Debug: 247 63 transport.c:240 handle_transport_init(): handle_transport_init Debug: 248 63 hla_transport.c:154 hl_transport_init(): hl_transport_init Debug: 249 63 hla_transport.c:171 hl_transport_init(): current transport hla_swd Debug: 250 63 hla_interface.c:44 hl_interface_open(): hl_interface_open Debug: 251 63 hla_layout.c:42 hl_layout_open(): hl_layout_open Debug: 252 63 stlink_usb.c:1788 stlink_usb_open(): stlink_usb_open Debug: 253 63 stlink_usb.c:1804 stlink_usb_open(): transport: 1 vid: 0x0483 pid: 0x374b serial: Info : 254 94 stlink_usb.c:636 stlink_usb_version(): STLINK v2 JTAG v27 API v2 M v15 VID 0x0483 PID 0x374B Info : 255 94 stlink_usb.c:1922 stlink_usb_open(): using stlink api v2 Debug: 256 94 stlink_usb.c:860 stlink_usb_init_mode(): MODE: 0x02 Info : 257 94 stlink_usb.c:668 stlink_usb_check_voltage(): Target voltage: 3.252071 Debug: 258 94 stlink_usb.c:915 stlink_usb_init_mode(): MODE: 0x01 Debug: 259 94 stlink_usb.c:941 stlink_usb_init_mode(): MODE: 0x02 Debug: 260 94 stlink_usb.c:1949 stlink_usb_open(): Supported SWD clock speeds are: Debug: 261 94 stlink_usb.c:1952 stlink_usb_open(): 4000 kHz Debug: 262 94 stlink_usb.c:1952 stlink_usb_open(): 1800 kHz Debug: 263 94 stlink_usb.c:1952 stlink_usb_open(): 1200 kHz Debug: 264 94 stlink_usb.c:1952 stlink_usb_open(): 950 kHz Debug: 265 94 stlink_usb.c:1952 stlink_usb_open(): 480 kHz Debug: 266 94 stlink_usb.c:1952 stlink_usb_open(): 240 kHz Debug: 267 94 stlink_usb.c:1952 stlink_usb_open(): 125 kHz Debug: 268 94 stlink_usb.c:1952 stlink_usb_open(): 100 kHz Debug: 269 94 stlink_usb.c:1952 stlink_usb_open(): 50 kHz Debug: 270 94 stlink_usb.c:1952 stlink_usb_open(): 25 kHz Debug: 271 94 stlink_usb.c:1952 stlink_usb_open(): 15 kHz Debug: 272 94 stlink_usb.c:1952 stlink_usb_open(): 5 kHz Info : 273 94 stlink_usb.c:1759 stlink_speed(): Stlink adapter speed set to 950 kHz Debug: 274 94 stlink_usb.c:1973 stlink_usb_open(): Using TAR autoincrement: 4096 Debug: 275 94 hla_interface.c:129 hl_interface_execute_queue(): hl_interface_execute_queue: ignored Debug: 276 94 core.c:727 jtag_add_reset(): SRST line asserted Debug: 277 94 core.c:755 jtag_add_reset(): TRST line released Debug: 278 94 core.c:329 jtag_call_event_callbacks(): jtag event: TAP reset Debug: 279 94 hla_interface.c:69 hl_interface_init_target(): hl_interface_init_target Debug: 280 94 stlink_usb.c:966 stlink_usb_idcode(): IDCODE: 0x1BA01477 Debug: 281 94 openocd.c:150 handle_init_command(): Examining targets... Debug: 282 94 target.c:1501 target_call_event_callbacks(): target event 21 (examine-start) Debug: 283 94 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000ed00 4 1 Debug: 284 94 target.c:2226 target_read_u32(): address: 0xe000ed00, value: 0x411fc231 Debug: 285 94 cortex_m.c:1933 cortex_m_examine(): Cortex-M3 r1p1 processor detected Debug: 286 94 cortex_m.c:1941 cortex_m_examine(): cpuid: 0x411fc231 Debug: 287 94 target.c:2314 target_write_u32(): address: 0xe000edfc, value: 0x01000000 Debug: 288 94 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edfc 4 1 Debug: 289 94 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0002000 4 1 Debug: 290 109 target.c:2226 target_read_u32(): address: 0xe0002000, value: 0x00000260 Debug: 291 109 target.c:2314 target_write_u32(): address: 0xe0002008, value: 0x00000000 Debug: 292 109 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002008 4 1 Debug: 293 109 target.c:2314 target_write_u32(): address: 0xe000200c, value: 0x00000000 Debug: 294 109 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000200c 4 1 Debug: 295 109 target.c:2314 target_write_u32(): address: 0xe0002010, value: 0x00000000 Debug: 296 109 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002010 4 1 Debug: 297 109 target.c:2314 target_write_u32(): address: 0xe0002014, value: 0x00000000 Debug: 298 109 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002014 4 1 Debug: 299 109 target.c:2314 target_write_u32(): address: 0xe0002018, value: 0x00000000 Debug: 300 109 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002018 4 1 Debug: 301 109 target.c:2314 target_write_u32(): address: 0xe000201c, value: 0x00000000 Debug: 302 109 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000201c 4 1 Debug: 303 109 target.c:2314 target_write_u32(): address: 0xe0002020, value: 0x00000000 Debug: 304 109 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002020 4 1 Debug: 305 109 target.c:2314 target_write_u32(): address: 0xe0002024, value: 0x00000000 Debug: 306 109 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0002024 4 1 Debug: 307 109 cortex_m.c:2032 cortex_m_examine(): FPB fpcr 0x260, numcode 6, numlit 2 Debug: 308 109 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0001000 4 1 Debug: 309 109 target.c:2226 target_read_u32(): address: 0xe0001000, value: 0x40000000 Debug: 310 109 target.c:2314 target_write_u32(): address: 0xe0001028, value: 0x00000000 Debug: 311 109 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0001028 4 1 Debug: 312 109 target.c:2314 target_write_u32(): address: 0xe0001038, value: 0x00000000 Debug: 313 109 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0001038 4 1 Debug: 314 109 target.c:2314 target_write_u32(): address: 0xe0001048, value: 0x00000000 Debug: 315 109 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0001048 4 1 Debug: 316 109 target.c:2314 target_write_u32(): address: 0xe0001058, value: 0x00000000 Debug: 317 109 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0001058 4 1 Debug: 318 125 cortex_m.c:1847 cortex_m_dwt_setup(): DWT dwtcr 0x40000000, comp 4, watch/trigger Info : 319 125 cortex_m.c:2042 cortex_m_examine(): STM32F107VCTx.cpu: hardware has 6 breakpoints, 4 watchpoints Debug: 320 125 target.c:1501 target_call_event_callbacks(): target event 22 (examine-end) Debug: 321 125 target.c:4256 target_handle_event(): target: (0) STM32F107VCTx.cpu (hla_target) event: 22 (examine-end) action: global ENABLE_LOW_POWER global STOP_WATCHDOG if { [expr ($ENABLE_LOW_POWER == 1)] } { # Enable debug during low power modes (uses more power) # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP mmw 0xE0042004 0x00000007 0 } if { [expr ($ENABLE_LOW_POWER == 0)] } { # Disable debug during low power modes # DBGMCU_CR |= ~(DBG_STANDBY | DBG_STOP | DBG_SLEEP) mmw 0xE0042004 0 0x00000007 } if { [expr ($STOP_WATCHDOG == 1)] } { # Stop watchdog counters during halt # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP mmw 0xE0042004 0x00000300 0 } if { [expr ($STOP_WATCHDOG == 0)] } { # Don't stop watchdog counters during halt # DBGMCU_CR |= ~(DBG_WWDG_STOP | DBG_IWDG_STOP) mmw 0xE0042004 0 0x00000300 } Debug: 322 125 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1 Debug: 323 125 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 775 Debug: 324 125 command.c:145 script_debug(): command - mww ocd_mww 0xE0042004 775 Debug: 326 125 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1 Debug: 327 125 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1 Debug: 328 125 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 775 Debug: 329 125 command.c:145 script_debug(): command - mww ocd_mww 0xE0042004 775 Debug: 331 125 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1 Debug: 332 125 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_flash init Debug: 333 125 command.c:145 script_debug(): command - ocd_flash ocd_flash init Debug: 335 125 tcl.c:1097 handle_flash_init_command(): Initializing flash devices... Debug: 336 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 337 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 338 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 339 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 340 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 341 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 342 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 343 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 344 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 345 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 346 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 347 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 348 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 349 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 350 125 command.c:366 register_command_handler(): registering 'ocd_flash'... Debug: 351 125 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mflash init Debug: 352 125 command.c:145 script_debug(): command - ocd_mflash ocd_mflash init Debug: 354 125 mflash.c:1379 handle_mflash_init_command(): Initializing mflash devices... Debug: 355 125 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_nand init Debug: 356 125 command.c:145 script_debug(): command - ocd_nand ocd_nand init Debug: 358 125 tcl.c:497 handle_nand_init_command(): Initializing NAND devices... Debug: 359 125 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_pld init Debug: 360 125 command.c:145 script_debug(): command - ocd_pld ocd_pld init Debug: 362 125 pld.c:207 handle_pld_init_command(): Initializing PLDs... Debug: 363 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_reset init Debug: 364 141 command.c:145 script_debug(): command - reset ocd_reset init Debug: 366 141 target.c:1519 target_call_reset_callbacks(): target reset 3 (init) Debug: 367 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target names Debug: 368 141 command.c:145 script_debug(): command - ocd_target ocd_target names Debug: 369 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event reset-start Debug: 370 141 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event reset-start Debug: 371 141 target.c:4256 target_handle_event(): target: (0) STM32F107VCTx.cpu (hla_target) event: 7 (reset-start) action: adapter_khz 950 Debug: 372 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 950 Debug: 373 141 command.c:145 script_debug(): command - adapter_khz ocd_adapter_khz 950 Debug: 375 141 core.c:1633 jtag_config_khz(): handle jtag khz Debug: 376 141 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 377 141 core.c:1603 adapter_khz_to_speed(): have interface set up Info : 378 141 stlink_usb.c:1759 stlink_speed(): Stlink adapter speed set to 950 kHz Debug: 379 141 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 380 141 core.c:1603 adapter_khz_to_speed(): have interface set up User : 381 141 command.c:546 command_print(): adapter speed: 950 kHz Debug: 382 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 383 141 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 384 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 385 141 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 386 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event examine-start Debug: 387 141 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event examine-start Debug: 388 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu arp_examine Debug: 389 141 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu arp_examine Debug: 390 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event examine-end Debug: 391 141 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event examine-end Debug: 392 141 target.c:4256 target_handle_event(): target: (0) STM32F107VCTx.cpu (hla_target) event: 22 (examine-end) action: global ENABLE_LOW_POWER global STOP_WATCHDOG if { [expr ($ENABLE_LOW_POWER == 1)] } { # Enable debug during low power modes (uses more power) # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP mmw 0xE0042004 0x00000007 0 } if { [expr ($ENABLE_LOW_POWER == 0)] } { # Disable debug during low power modes # DBGMCU_CR |= ~(DBG_STANDBY | DBG_STOP | DBG_SLEEP) mmw 0xE0042004 0 0x00000007 } if { [expr ($STOP_WATCHDOG == 1)] } { # Stop watchdog counters during halt # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP mmw 0xE0042004 0x00000300 0 } if { [expr ($STOP_WATCHDOG == 0)] } { # Don't stop watchdog counters during halt # DBGMCU_CR |= ~(DBG_WWDG_STOP | DBG_IWDG_STOP) mmw 0xE0042004 0 0x00000300 } Debug: 393 141 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1 Debug: 394 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 775 Debug: 395 141 command.c:145 script_debug(): command - mww ocd_mww 0xE0042004 775 Debug: 397 141 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1 Debug: 398 141 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1 Debug: 399 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 775 Debug: 400 141 command.c:145 script_debug(): command - mww ocd_mww 0xE0042004 775 Debug: 402 141 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1 Debug: 403 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event reset-assert-pre Debug: 404 141 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event reset-assert-pre Debug: 405 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 406 141 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 407 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu arp_reset assert 1 Debug: 408 141 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu arp_reset assert 1 Debug: 409 141 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas Debug: 410 141 hla_target.c:485 adapter_assert_reset(): adapter_assert_reset Debug: 411 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event reset-assert-post Debug: 412 141 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event reset-assert-post Debug: 413 141 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event reset-deassert-pre Debug: 414 141 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event reset-deassert-pre Debug: 415 156 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 416 156 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 417 156 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu arp_reset deassert 1 Debug: 418 156 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu arp_reset deassert 1 Debug: 419 156 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas Debug: 420 156 hla_target.c:548 adapter_deassert_reset(): adapter_deassert_reset Debug: 421 156 hla_interface.c:129 hl_interface_execute_queue(): hl_interface_execute_queue: ignored Debug: 422 156 core.c:731 jtag_add_reset(): SRST line released Debug: 423 156 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event reset-deassert-post Debug: 424 156 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event reset-deassert-post Debug: 425 156 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 426 156 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 427 156 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu arp_waitstate halted 1000 Debug: 428 156 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu arp_waitstate halted 1000 Debug: 429 156 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1 Debug: 430 156 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000 Debug: 431 156 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 432 156 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 0 value 0x7142 Debug: 433 156 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 434 156 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 1 value 0x2ae Debug: 435 156 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 436 156 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 2 value 0x0 Debug: 437 156 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 438 156 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 3 value 0x20000540 Debug: 439 156 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 440 156 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 4 value 0x10c Debug: 441 156 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 442 156 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 5 value 0x8 Debug: 443 156 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 444 156 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 6 value 0x4c11db7 Debug: 445 156 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 446 156 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 7 value 0x2000ffd8 Debug: 447 156 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 448 156 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 8 value 0x123ea827 Debug: 449 156 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 450 156 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 9 value 0x61607841 Debug: 451 156 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 452 156 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 10 value 0x8b3c5302 Debug: 453 156 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 454 172 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 11 value 0x7c086011 Debug: 455 172 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 456 172 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 12 value 0x72040075 Debug: 457 172 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 458 172 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 13 value 0x20010000 Debug: 459 172 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 460 172 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 14 value 0xffffffff Debug: 461 172 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 462 172 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 15 value 0x8000274 Debug: 463 172 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 464 172 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 16 value 0x1000000 Debug: 465 172 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 466 172 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 17 value 0x20010000 Debug: 467 172 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 468 172 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 18 value 0x8344c42c Debug: 469 172 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 470 172 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 19 value 0x0 Debug: 471 172 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 472 172 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 20 value 0x0 Debug: 473 172 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 474 172 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 21 value 0x0 Debug: 475 172 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 476 172 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 22 value 0x0 Debug: 477 172 hla_target.c:433 adapter_debug_entry(): entered debug state in core mode: Thread at PC 0x08000274, target->state: halted Debug: 478 172 target.c:1501 target_call_event_callbacks(): target event 0 (gdb-halt) Debug: 479 172 target.c:1501 target_call_event_callbacks(): target event 1 (halted) User : 480 172 target.c:1936 target_arch_state(): STM32F107VCTx.cpu: target state: halted User : 481 172 armv7m.c:553 armv7m_arch_state(): target halted due to debug-request, current mode: Thread xPSR: 0x01000000 pc: 0x08000274 msp: 0x20010000 Debug: 482 172 hla_target.c:472 adapter_poll(): halted: PC: 0x08000274 Debug: 483 172 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu curstate Debug: 484 172 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu curstate Debug: 485 172 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 486 172 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 487 172 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu arp_waitstate halted 5000 Debug: 488 172 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu arp_waitstate halted 5000 Debug: 489 172 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event reset-init Debug: 490 172 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event reset-init Debug: 491 172 target.c:4256 target_handle_event(): target: (0) STM32F107VCTx.cpu (hla_target) event: 17 (reset-init) action: global _CLOCK_FREQ adapter_khz $_CLOCK_FREQ Debug: 492 172 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 4000 Debug: 493 172 command.c:145 script_debug(): command - adapter_khz ocd_adapter_khz 4000 Debug: 495 172 core.c:1633 jtag_config_khz(): handle jtag khz Debug: 496 172 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 497 172 core.c:1603 adapter_khz_to_speed(): have interface set up Info : 498 172 stlink_usb.c:1759 stlink_speed(): Stlink adapter speed set to 4000 kHz Debug: 499 172 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 500 172 core.c:1603 adapter_khz_to_speed(): have interface set up User : 501 172 command.c:546 command_print(): adapter speed: 4000 kHz Debug: 502 187 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event reset-end Debug: 503 187 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event reset-end Debug: 504 187 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_echo ** Programming Started ** Debug: 505 187 command.c:145 script_debug(): command - echo ocd_echo ** Programming Started ** User : 507 187 command.c:764 jim_echo(): ** Programming Started ** Debug: 508 187 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_flash write_image erase Debug/Lucon_V2_Master.elf Debug: 509 187 command.c:145 script_debug(): command - ocd_flash ocd_flash write_image erase Debug/Lucon_V2_Master.elf User : 511 187 command.c:546 command_print(): auto erase enabled Debug: 512 187 configuration.c:84 find_file(): found Debug/Lucon_V2_Master.elf Debug: 513 187 image.c:71 autodetect_image_type(): ELF image detected. Debug: 514 187 configuration.c:84 find_file(): found Debug/Lucon_V2_Master.elf Debug: 515 187 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000ed00 4 1 Debug: 516 187 target.c:2226 target_read_u32(): address: 0xe000ed00, value: 0x411fc231 Debug: 517 187 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0042000 4 1 Debug: 518 187 target.c:2226 target_read_u32(): address: 0xe0042000, value: 0x10016418 Info : 519 187 stm32f1x.c:866 stm32x_probe(): device id = 0x10016418 Debug: 520 187 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000ed00 4 1 Debug: 521 187 target.c:2226 target_read_u32(): address: 0xe000ed00, value: 0x411fc231 Debug: 522 187 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x1ffff7e0 2 1 Debug: 523 187 target.c:2250 target_read_u16(): address: 0x1ffff7e0, value: 0x0100 Info : 524 187 stm32f1x.c:1008 stm32x_probe(): flash size = 256kbytes Debug: 525 187 core.c:712 flash_write_unlock(): image_read_section: section = 0, t_section_num = 0, section_offset = 0, buffer_size = 0, size_read = 5940 Debug: 526 187 image.c:480 image_elf_read_section(): load segment 0 at 0x0 (sz = 0x1734) Debug: 527 187 image.c:487 image_elf_read_section(): read elf: size = 0x5940 at 0x10000 Debug: 528 187 core.c:712 flash_write_unlock(): image_read_section: section = 1, t_section_num = 1, section_offset = 0, buffer_size = 5940, size_read = 4 Debug: 529 187 image.c:480 image_elf_read_section(): load segment 1 at 0x0 (sz = 0x4) Debug: 530 187 image.c:487 image_elf_read_section(): read elf: size = 0x4 at 0x20000 Debug: 531 187 target.c:2314 target_write_u32(): address: 0x40022004, value: 0x45670123 Debug: 532 187 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022004 4 1 Debug: 533 187 target.c:2314 target_write_u32(): address: 0x40022004, value: 0xcdef89ab Debug: 534 187 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022004 4 1 Debug: 535 187 target.c:2314 target_write_u32(): address: 0x40022010, value: 0x00000002 Debug: 536 187 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022010 4 1 Debug: 537 187 target.c:2314 target_write_u32(): address: 0x40022014, value: 0x08000000 Debug: 538 187 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022014 4 1 Debug: 539 187 target.c:2314 target_write_u32(): address: 0x40022010, value: 0x00000042 Debug: 540 187 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022010 4 1 Debug: 541 187 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x4002200c 4 1 Debug: 542 187 target.c:2226 target_read_u32(): address: 0x4002200c, value: 0x00000003 Debug: 543 187 stm32f1x.c:177 stm32x_wait_status_busy(): status: 0x3 Debug: 544 203 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x4002200c 4 1 Debug: 545 203 target.c:2226 target_read_u32(): address: 0x4002200c, value: 0x00000003 Debug: 546 203 stm32f1x.c:177 stm32x_wait_status_busy(): status: 0x3 Debug: 547 219 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x4002200c 4 1 Debug: 548 219 target.c:2226 target_read_u32(): address: 0x4002200c, value: 0x00000003 Debug: 549 219 stm32f1x.c:177 stm32x_wait_status_busy(): status: 0x3 Debug: 550 234 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x4002200c 4 1 Debug: 551 234 target.c:2226 target_read_u32(): address: 0x4002200c, value: 0x00000020 Debug: 552 234 stm32f1x.c:177 stm32x_wait_status_busy(): status: 0x20 Debug: 553 234 target.c:2314 target_write_u32(): address: 0x40022010, value: 0x00000002 Debug: 554 234 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022010 4 1 Debug: 555 234 target.c:2314 target_write_u32(): address: 0x40022014, value: 0x08000800 Debug: 556 234 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022014 4 1 Debug: 557 234 target.c:2314 target_write_u32(): address: 0x40022010, value: 0x00000042 Debug: 558 234 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022010 4 1 Debug: 559 234 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x4002200c 4 1 Debug: 560 250 target.c:2226 target_read_u32(): address: 0x4002200c, value: 0x00000023 Debug: 561 250 stm32f1x.c:177 stm32x_wait_status_busy(): status: 0x23 Debug: 562 265 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x4002200c 4 1 Debug: 563 265 target.c:2226 target_read_u32(): address: 0x4002200c, value: 0x00000020 Debug: 564 265 stm32f1x.c:177 stm32x_wait_status_busy(): status: 0x20 Debug: 565 265 target.c:2314 target_write_u32(): address: 0x40022010, value: 0x00000002 Debug: 566 265 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022010 4 1 Debug: 567 265 target.c:2314 target_write_u32(): address: 0x40022014, value: 0x08001000 Debug: 568 265 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022014 4 1 Debug: 569 265 target.c:2314 target_write_u32(): address: 0x40022010, value: 0x00000042 Debug: 570 265 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022010 4 1 Debug: 571 265 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x4002200c 4 1 Debug: 572 265 target.c:2226 target_read_u32(): address: 0x4002200c, value: 0x00000023 Debug: 573 265 stm32f1x.c:177 stm32x_wait_status_busy(): status: 0x23 Debug: 574 281 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x4002200c 4 1 Debug: 575 281 target.c:2226 target_read_u32(): address: 0x4002200c, value: 0x00000023 Debug: 576 281 stm32f1x.c:177 stm32x_wait_status_busy(): status: 0x23 Debug: 577 297 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x4002200c 4 1 Debug: 578 297 target.c:2226 target_read_u32(): address: 0x4002200c, value: 0x00000020 Debug: 579 297 stm32f1x.c:177 stm32x_wait_status_busy(): status: 0x20 Debug: 580 297 target.c:2314 target_write_u32(): address: 0x40022010, value: 0x00000080 Debug: 581 297 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022010 4 1 Debug: 582 297 target.c:2314 target_write_u32(): address: 0x40022004, value: 0x45670123 Debug: 583 297 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022004 4 1 Debug: 584 297 target.c:2314 target_write_u32(): address: 0x40022004, value: 0xcdef89ab Debug: 585 297 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022004 4 1 Debug: 586 297 target.c:2314 target_write_u32(): address: 0x40022010, value: 0x00000001 Debug: 587 297 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022010 4 1 Debug: 588 312 target.c:1708 target_alloc_working_area_try(): MMU disabled, using physical address for working memory 0x20000000 Debug: 589 312 target.c:1761 target_alloc_working_area_try(): allocated new working area of 60 bytes at address 0x20000000 Debug: 590 312 target.c:1624 print_wa_layout(): * 0x20000000-0x2000003b (60 bytes) Debug: 591 312 target.c:1624 print_wa_layout(): 0x2000003c-0x20007fff (32708 bytes) Debug: 592 312 target.c:2017 target_write_buffer(): writing buffer of 60 byte at 0x20000000 Debug: 593 312 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x20000000 4 15 Debug: 594 312 target.c:1761 target_alloc_working_area_try(): allocated new working area of 16384 bytes at address 0x2000003c Debug: 595 312 target.c:1624 print_wa_layout(): * 0x20000000-0x2000003b (60 bytes) Debug: 596 312 target.c:1624 print_wa_layout(): * 0x2000003c-0x2000403b (16384 bytes) Debug: 597 312 target.c:1624 print_wa_layout(): 0x2000403c-0x20007fff (16324 bytes) Debug: 598 312 target.c:2314 target_write_u32(): address: 0x2000003c, value: 0x20000044 Debug: 599 312 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x2000003c 4 1 Debug: 600 312 target.c:2314 target_write_u32(): address: 0x20000040, value: 0x20000044 Debug: 601 312 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x20000040 4 1 Debug: 602 312 target.c:1501 target_call_event_callbacks(): target event 3 (resume-start) Debug: 603 312 hla_target.c:600 adapter_resume(): adapter_resume 0 0x20000000 1 1 Debug: 604 312 target.c:2314 target_write_u32(): address: 0xe000edfc, value: 0x01000000 Debug: 605 312 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edfc 4 1 Debug: 606 312 armv7m.c:146 armv7m_restore_context(): Debug: 607 312 armv7m.c:278 armv7m_write_core_reg(): write core reg 15 value 0x20000000 Debug: 608 312 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 609 312 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 15 value 0x20000000 Debug: 610 328 armv7m.c:278 armv7m_write_core_reg(): write core reg 4 value 0x8000000 Debug: 611 328 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 612 328 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 4 value 0x8000000 Debug: 613 328 armv7m.c:278 armv7m_write_core_reg(): write core reg 3 value 0x2000403c Debug: 614 328 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 615 328 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 3 value 0x2000403c Debug: 616 328 armv7m.c:278 armv7m_write_core_reg(): write core reg 2 value 0x2000003c Debug: 617 328 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 618 328 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 2 value 0x2000003c Debug: 619 328 armv7m.c:278 armv7m_write_core_reg(): write core reg 1 value 0xc00 Debug: 620 328 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 621 328 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 1 value 0xc00 Debug: 622 328 armv7m.c:278 armv7m_write_core_reg(): write core reg 0 value 0x40022000 Debug: 623 328 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 624 328 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 0 value 0x40022000 Debug: 625 328 target.c:2314 target_write_u32(): address: 0xe000edf8, value: 0x00000000 Debug: 626 328 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf8 4 1 Debug: 627 343 target.c:1501 target_call_event_callbacks(): target event 20 (debug-resumed) Debug: 628 343 target.c:1501 target_call_event_callbacks(): target event 4 (resume-end) Debug: 629 343 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x20000040 4 1 Debug: 630 343 target.c:2226 target_read_u32(): address: 0x20000040, value: 0x20000044 Debug: 631 343 target.c:936 target_run_flash_async_algorithm(): offs 0x0 count 0xc00 wp 0x20000044 rp 0x20000044 Debug: 632 343 target.c:2017 target_write_buffer(): writing buffer of 6144 byte at 0x20000044 Debug: 633 343 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x20000044 4 1536 Debug: 634 375 target.c:2314 target_write_u32(): address: 0x2000003c, value: 0x20001844 Debug: 635 375 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x2000003c 4 1 Debug: 636 390 target.c:2788 target_wait_state(): waiting for target halted... Debug: 637 562 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1 Debug: 638 562 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000 Debug: 639 562 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 640 562 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 0 value 0x20 Debug: 641 562 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 642 562 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 1 value 0x0 Debug: 643 562 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 644 562 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 2 value 0x2000003c Debug: 645 562 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 646 562 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 3 value 0x2000403c Debug: 647 562 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 648 562 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 4 value 0x8001800 Debug: 649 562 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 650 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 5 value 0x20001844 Debug: 651 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 652 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 6 value 0x20 Debug: 653 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 654 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 7 value 0x14 Debug: 655 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 656 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 8 value 0x123ea827 Debug: 657 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 658 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 9 value 0x61607841 Debug: 659 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 660 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 10 value 0x8b3c5302 Debug: 661 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 662 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 11 value 0x7c086011 Debug: 663 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 664 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 12 value 0x72040075 Debug: 665 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 666 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 13 value 0x20010000 Debug: 667 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 668 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 14 value 0xffffffff Debug: 669 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 670 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 15 value 0x2000003a Debug: 671 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 672 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 16 value 0x61000000 Debug: 673 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 674 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 17 value 0x20010000 Debug: 675 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 676 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 18 value 0x8344c42c Debug: 677 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 678 577 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 19 value 0x0 Debug: 679 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 680 577 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 20 value 0x0 Debug: 681 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 682 577 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 21 value 0x0 Debug: 683 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 684 577 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 22 value 0x0 Debug: 685 577 hla_target.c:433 adapter_debug_entry(): entered debug state in core mode: Thread at PC 0x2000003a, target->state: halted Debug: 686 577 target.c:1501 target_call_event_callbacks(): target event 0 (gdb-halt) Debug: 687 577 target.c:1501 target_call_event_callbacks(): target event 1 (halted) User : 688 577 target.c:1936 target_arch_state(): STM32F107VCTx.cpu: target state: halted User : 689 577 armv7m.c:553 armv7m_arch_state(): target halted due to breakpoint, current mode: Thread xPSR: 0x61000000 pc: 0x2000003a msp: 0x20010000 Debug: 690 577 hla_target.c:472 adapter_poll(): halted: PC: 0x2000003a Debug: 691 577 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 692 577 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 15 value 0x2000003a Debug: 693 577 armv7m.c:512 armv7m_wait_algorithm(): restoring register xPSR with value 0x01000000 Debug: 694 577 armv7m.c:512 armv7m_wait_algorithm(): restoring register pc with value 0x08000274 Debug: 695 577 armv7m.c:512 armv7m_wait_algorithm(): restoring register r7 with value 0x2000ffd8 Debug: 696 577 armv7m.c:512 armv7m_wait_algorithm(): restoring register r6 with value 0x04c11db7 Debug: 697 577 armv7m.c:512 armv7m_wait_algorithm(): restoring register r5 with value 0x00000008 Debug: 698 577 armv7m.c:512 armv7m_wait_algorithm(): restoring register r4 with value 0x0000010c Debug: 699 577 armv7m.c:512 armv7m_wait_algorithm(): restoring register r3 with value 0x20000540 Debug: 700 577 armv7m.c:512 armv7m_wait_algorithm(): restoring register r2 with value 0x00000000 Debug: 701 577 armv7m.c:512 armv7m_wait_algorithm(): restoring register r1 with value 0x000002ae Debug: 702 577 armv7m.c:512 armv7m_wait_algorithm(): restoring register r0 with value 0x00007142 Debug: 703 577 target.c:1830 target_free_working_area_restore(): freed 16384 bytes of working area at address 0x2000003c Debug: 704 577 target.c:1624 print_wa_layout(): * 0x20000000-0x2000003b (60 bytes) Debug: 705 577 target.c:1624 print_wa_layout(): 0x2000003c-0x20007fff (32708 bytes) Debug: 706 577 target.c:1830 target_free_working_area_restore(): freed 60 bytes of working area at address 0x20000000 Debug: 707 577 target.c:1624 print_wa_layout(): 0x20000000-0x20007fff (32768 bytes) Debug: 708 577 target.c:2314 target_write_u32(): address: 0x40022010, value: 0x00000080 Debug: 709 577 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x40022010 4 1 User : 710 593 command.c:546 command_print(): wrote 6144 bytes from file Debug/Lucon_V2_Master.elf in 0.405585s (14.793 KiB/s) Debug: 711 593 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_echo ** Programming Finished ** Debug: 712 593 command.c:145 script_debug(): command - echo ocd_echo ** Programming Finished ** User : 715 609 command.c:764 jim_echo(): ** Programming Finished ** Debug: 716 609 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_echo ** Verify Started ** Debug: 717 609 command.c:145 script_debug(): command - echo ocd_echo ** Verify Started ** User : 719 609 command.c:764 jim_echo(): ** Verify Started ** Debug: 720 609 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_verify_image Debug/Lucon_V2_Master.elf Debug: 721 609 command.c:145 script_debug(): command - verify_image ocd_verify_image Debug/Lucon_V2_Master.elf Debug: 723 609 configuration.c:84 find_file(): found Debug/Lucon_V2_Master.elf Debug: 724 609 image.c:71 autodetect_image_type(): ELF image detected. Debug: 725 609 configuration.c:84 find_file(): found Debug/Lucon_V2_Master.elf Debug: 726 609 image.c:480 image_elf_read_section(): load segment 0 at 0x0 (sz = 0x1734) Debug: 727 609 image.c:487 image_elf_read_section(): read elf: size = 0x5940 at 0x10000 Debug: 728 609 image.c:1011 image_calculate_checksum(): Calculating checksum Debug: 729 609 image.c:1042 image_calculate_checksum(): Calculating checksum done Debug: 730 609 target.c:1761 target_alloc_working_area_try(): allocated new working area of 52 bytes at address 0x20000000 Debug: 731 609 target.c:1624 print_wa_layout(): * 0x20000000-0x20000033 (52 bytes) Debug: 732 609 target.c:1624 print_wa_layout(): 0x20000034-0x20007fff (32716 bytes) Debug: 733 609 target.c:2017 target_write_buffer(): writing buffer of 52 byte at 0x20000000 Debug: 734 609 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x20000000 4 13 Debug: 735 609 target.c:1501 target_call_event_callbacks(): target event 3 (resume-start) Debug: 736 609 hla_target.c:600 adapter_resume(): adapter_resume 0 0x20000000 1 1 Debug: 737 609 target.c:2314 target_write_u32(): address: 0xe000edfc, value: 0x01000000 Debug: 738 609 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edfc 4 1 Debug: 739 609 armv7m.c:146 armv7m_restore_context(): Debug: 740 609 armv7m.c:278 armv7m_write_core_reg(): write core reg 16 value 0x1000000 Debug: 741 609 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 742 609 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 16 value 0x1000000 Debug: 743 609 armv7m.c:278 armv7m_write_core_reg(): write core reg 15 value 0x20000000 Debug: 744 609 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 745 609 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 15 value 0x20000000 Debug: 746 609 armv7m.c:278 armv7m_write_core_reg(): write core reg 7 value 0x2000ffd8 Debug: 747 609 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 748 609 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 7 value 0x2000ffd8 Debug: 749 609 armv7m.c:278 armv7m_write_core_reg(): write core reg 6 value 0x4c11db7 Debug: 750 609 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 751 609 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 6 value 0x4c11db7 Debug: 752 609 armv7m.c:278 armv7m_write_core_reg(): write core reg 5 value 0x8 Debug: 753 609 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 754 624 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 5 value 0x8 Debug: 755 624 armv7m.c:278 armv7m_write_core_reg(): write core reg 4 value 0x10c Debug: 756 624 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 757 624 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 4 value 0x10c Debug: 758 624 armv7m.c:278 armv7m_write_core_reg(): write core reg 3 value 0x20000540 Debug: 759 624 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 760 624 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 3 value 0x20000540 Debug: 761 624 armv7m.c:278 armv7m_write_core_reg(): write core reg 2 value 0x0 Debug: 762 624 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 763 624 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 2 value 0x0 Debug: 764 624 armv7m.c:278 armv7m_write_core_reg(): write core reg 1 value 0x1734 Debug: 765 624 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 766 624 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 1 value 0x1734 Debug: 767 624 armv7m.c:278 armv7m_write_core_reg(): write core reg 0 value 0x8000000 Debug: 768 624 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 769 624 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 0 value 0x8000000 Debug: 770 624 target.c:2314 target_write_u32(): address: 0xe000edf8, value: 0x00000000 Debug: 771 624 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf8 4 1 Debug: 772 624 target.c:1501 target_call_event_callbacks(): target event 20 (debug-resumed) Debug: 773 624 target.c:1501 target_call_event_callbacks(): target event 4 (resume-end) Debug: 774 624 target.c:2788 target_wait_state(): waiting for target halted... Debug: 775 704 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1 Debug: 776 704 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000 Debug: 777 704 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 778 704 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 0 value 0xc23f1124 Debug: 779 704 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 780 704 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 1 value 0x8000000 Debug: 781 704 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 782 704 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 2 value 0x8000000 Debug: 783 704 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 784 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 3 value 0x1734 Debug: 785 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 786 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 4 value 0x1734 Debug: 787 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 788 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 5 value 0x8 Debug: 789 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 790 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 6 value 0x4c11db7 Debug: 791 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 792 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 7 value 0x2000ffd8 Debug: 793 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 794 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 8 value 0x123ea827 Debug: 795 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 796 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 9 value 0x61607841 Debug: 797 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 798 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 10 value 0x8b3c5302 Debug: 799 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 800 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 11 value 0x7c086011 Debug: 801 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 802 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 12 value 0x72040075 Debug: 803 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 804 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 13 value 0x20010000 Debug: 805 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 806 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 14 value 0xffffffff Debug: 807 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 808 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 15 value 0x2000002e Debug: 809 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 810 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 16 value 0x61000000 Debug: 811 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 812 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 17 value 0x20010000 Debug: 813 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 814 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 18 value 0x8344c42c Debug: 815 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 816 720 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 19 value 0x0 Debug: 817 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 818 720 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 20 value 0x0 Debug: 819 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 820 720 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 21 value 0x0 Debug: 821 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 822 720 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 22 value 0x0 Debug: 823 720 hla_target.c:433 adapter_debug_entry(): entered debug state in core mode: Thread at PC 0x2000002e, target->state: halted Debug: 824 720 target.c:1501 target_call_event_callbacks(): target event 0 (gdb-halt) Debug: 825 720 target.c:1501 target_call_event_callbacks(): target event 1 (halted) User : 826 720 target.c:1936 target_arch_state(): STM32F107VCTx.cpu: target state: halted User : 827 720 armv7m.c:553 armv7m_arch_state(): target halted due to breakpoint, current mode: Thread xPSR: 0x61000000 pc: 0x2000002e msp: 0x20010000 Debug: 828 720 hla_target.c:472 adapter_poll(): halted: PC: 0x2000002e Debug: 829 720 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 830 720 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 15 value 0x2000002e Debug: 831 720 armv7m.c:512 armv7m_wait_algorithm(): restoring register xPSR with value 0x01000000 Debug: 832 720 armv7m.c:512 armv7m_wait_algorithm(): restoring register pc with value 0x08000274 Debug: 833 720 armv7m.c:512 armv7m_wait_algorithm(): restoring register r4 with value 0x0000010c Debug: 834 720 armv7m.c:512 armv7m_wait_algorithm(): restoring register r3 with value 0x20000540 Debug: 835 720 armv7m.c:512 armv7m_wait_algorithm(): restoring register r2 with value 0x00000000 Debug: 836 720 armv7m.c:512 armv7m_wait_algorithm(): restoring register r1 with value 0x000002ae Debug: 837 720 armv7m.c:512 armv7m_wait_algorithm(): restoring register r0 with value 0x00007142 Debug: 838 720 target.c:1830 target_free_working_area_restore(): freed 52 bytes of working area at address 0x20000000 Debug: 839 720 target.c:1624 print_wa_layout(): 0x20000000-0x20007fff (32768 bytes) Debug: 840 720 image.c:480 image_elf_read_section(): load segment 1 at 0x0 (sz = 0x4) Debug: 841 720 image.c:487 image_elf_read_section(): read elf: size = 0x4 at 0x20000 Debug: 842 720 image.c:1011 image_calculate_checksum(): Calculating checksum Debug: 843 720 image.c:1042 image_calculate_checksum(): Calculating checksum done Debug: 844 720 target.c:1761 target_alloc_working_area_try(): allocated new working area of 52 bytes at address 0x20000000 Debug: 845 720 target.c:1624 print_wa_layout(): * 0x20000000-0x20000033 (52 bytes) Debug: 846 720 target.c:1624 print_wa_layout(): 0x20000034-0x20007fff (32716 bytes) Debug: 847 720 target.c:2017 target_write_buffer(): writing buffer of 52 byte at 0x20000000 Debug: 848 720 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0x20000000 4 13 Debug: 849 720 target.c:1501 target_call_event_callbacks(): target event 3 (resume-start) Debug: 850 720 hla_target.c:600 adapter_resume(): adapter_resume 0 0x20000000 1 1 Debug: 851 720 target.c:2314 target_write_u32(): address: 0xe000edfc, value: 0x01000000 Debug: 852 735 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edfc 4 1 Debug: 853 735 armv7m.c:146 armv7m_restore_context(): Debug: 854 735 armv7m.c:278 armv7m_write_core_reg(): write core reg 16 value 0x1000000 Debug: 855 735 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 856 735 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 16 value 0x1000000 Debug: 857 735 armv7m.c:278 armv7m_write_core_reg(): write core reg 15 value 0x20000000 Debug: 858 735 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 859 735 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 15 value 0x20000000 Debug: 860 735 armv7m.c:278 armv7m_write_core_reg(): write core reg 4 value 0x10c Debug: 861 735 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 862 735 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 4 value 0x10c Debug: 863 735 armv7m.c:278 armv7m_write_core_reg(): write core reg 3 value 0x20000540 Debug: 864 735 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 865 735 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 3 value 0x20000540 Debug: 866 735 armv7m.c:278 armv7m_write_core_reg(): write core reg 2 value 0x0 Debug: 867 735 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 868 735 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 2 value 0x0 Debug: 869 735 armv7m.c:278 armv7m_write_core_reg(): write core reg 1 value 0x4 Debug: 870 735 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 871 735 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 1 value 0x4 Debug: 872 735 armv7m.c:278 armv7m_write_core_reg(): write core reg 0 value 0x8001734 Debug: 873 735 hla_target.c:150 adapter_store_core_reg_u32(): adapter_store_core_reg_u32 Debug: 874 735 hla_target.c:168 adapter_store_core_reg_u32(): write core reg 0 value 0x8001734 Debug: 875 735 target.c:2314 target_write_u32(): address: 0xe000edf8, value: 0x00000000 Debug: 876 735 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edf8 4 1 Debug: 877 735 target.c:1501 target_call_event_callbacks(): target event 20 (debug-resumed) Debug: 878 735 target.c:1501 target_call_event_callbacks(): target event 4 (resume-end) Debug: 879 735 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe000edf8 4 1 Debug: 880 735 target.c:2226 target_read_u32(): address: 0xe000edf8, value: 0x00000000 Debug: 881 735 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 882 735 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 0 value 0x6b0e90d8 Debug: 883 735 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 884 735 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 1 value 0x4000000 Debug: 885 735 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 886 735 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 2 value 0x8001734 Debug: 887 735 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 888 735 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 3 value 0x4 Debug: 889 735 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 890 735 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 4 value 0x4 Debug: 891 735 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 892 735 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 5 value 0x8 Debug: 893 735 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 894 735 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 6 value 0x4c11db7 Debug: 895 735 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 896 735 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 7 value 0x2000ffd8 Debug: 897 735 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 898 735 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 8 value 0x123ea827 Debug: 899 735 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 900 735 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 9 value 0x61607841 Debug: 901 735 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 902 735 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 10 value 0x8b3c5302 Debug: 903 735 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 904 735 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 11 value 0x7c086011 Debug: 905 751 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 906 751 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 12 value 0x72040075 Debug: 907 751 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 908 751 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 13 value 0x20010000 Debug: 909 751 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 910 751 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 14 value 0xffffffff Debug: 911 751 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 912 751 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 15 value 0x2000002e Debug: 913 751 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 914 751 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 16 value 0x61000000 Debug: 915 751 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 916 751 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 17 value 0x20010000 Debug: 917 751 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 918 751 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 18 value 0x8344c42c Debug: 919 751 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 920 751 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 19 value 0x0 Debug: 921 751 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 922 751 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 20 value 0x0 Debug: 923 751 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 924 751 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 21 value 0x0 Debug: 925 751 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 926 751 hla_target.c:132 adapter_load_core_reg_u32(): load from special reg 22 value 0x0 Debug: 927 751 hla_target.c:433 adapter_debug_entry(): entered debug state in core mode: Thread at PC 0x2000002e, target->state: halted Debug: 928 751 target.c:1501 target_call_event_callbacks(): target event 19 (debug-halted) Debug: 929 751 hla_target.c:472 adapter_poll(): halted: PC: 0x2000002e Debug: 930 751 hla_target.c:60 adapter_load_core_reg_u32(): adapter_load_core_reg_u32 Debug: 931 751 hla_target.c:75 adapter_load_core_reg_u32(): load from core reg 15 value 0x2000002e Debug: 932 751 armv7m.c:512 armv7m_wait_algorithm(): restoring register xPSR with value 0x01000000 Debug: 933 751 armv7m.c:512 armv7m_wait_algorithm(): restoring register pc with value 0x08000274 Debug: 934 751 armv7m.c:512 armv7m_wait_algorithm(): restoring register r4 with value 0x0000010c Debug: 935 751 armv7m.c:512 armv7m_wait_algorithm(): restoring register r3 with value 0x20000540 Debug: 936 751 armv7m.c:512 armv7m_wait_algorithm(): restoring register r2 with value 0x00000000 Debug: 937 751 armv7m.c:512 armv7m_wait_algorithm(): restoring register r1 with value 0x000002ae Debug: 938 751 armv7m.c:512 armv7m_wait_algorithm(): restoring register r0 with value 0x00007142 Debug: 939 751 target.c:1830 target_free_working_area_restore(): freed 52 bytes of working area at address 0x20000000 Debug: 940 751 target.c:1624 print_wa_layout(): 0x20000000-0x20007fff (32768 bytes) User : 941 751 command.c:546 command_print(): verified 5944 bytes in 0.142395s (40.765 KiB/s) Debug: 942 751 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_echo ** Verified OK ** Debug: 943 751 command.c:145 script_debug(): command - echo ocd_echo ** Verified OK ** User : 945 751 command.c:764 jim_echo(): ** Verified OK ** Debug: 946 751 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_poll off Debug: 947 751 command.c:145 script_debug(): command - poll ocd_poll off Debug: 949 751 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_echo ** Resetting Target ** Debug: 950 751 command.c:145 script_debug(): command - echo ocd_echo ** Resetting Target ** User : 952 751 command.c:764 jim_echo(): ** Resetting Target ** Debug: 953 751 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_reset run Debug: 954 751 command.c:145 script_debug(): command - reset ocd_reset run Debug: 956 751 target.c:1519 target_call_reset_callbacks(): target reset 1 (run) Debug: 957 751 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_target names Debug: 958 751 command.c:145 script_debug(): command - ocd_target ocd_target names Debug: 959 751 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event reset-start Debug: 960 751 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event reset-start Debug: 961 751 target.c:4256 target_handle_event(): target: (0) STM32F107VCTx.cpu (hla_target) event: 7 (reset-start) action: adapter_khz 950 Debug: 962 751 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_adapter_khz 950 Debug: 963 751 command.c:145 script_debug(): command - adapter_khz ocd_adapter_khz 950 Debug: 965 751 core.c:1633 jtag_config_khz(): handle jtag khz Debug: 966 751 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 967 751 core.c:1603 adapter_khz_to_speed(): have interface set up Info : 968 751 stlink_usb.c:1759 stlink_speed(): Stlink adapter speed set to 950 kHz Debug: 969 751 core.c:1600 adapter_khz_to_speed(): convert khz to interface specific speed value Debug: 970 751 core.c:1603 adapter_khz_to_speed(): have interface set up User : 971 751 command.c:546 command_print(): adapter speed: 950 kHz Debug: 972 751 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 973 751 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 974 751 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 975 751 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 976 751 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event examine-start Debug: 977 751 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event examine-start Debug: 978 751 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu arp_examine Debug: 979 751 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu arp_examine Debug: 980 751 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event examine-end Debug: 981 751 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event examine-end Debug: 982 751 target.c:4256 target_handle_event(): target: (0) STM32F107VCTx.cpu (hla_target) event: 22 (examine-end) action: global ENABLE_LOW_POWER global STOP_WATCHDOG if { [expr ($ENABLE_LOW_POWER == 1)] } { # Enable debug during low power modes (uses more power) # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP mmw 0xE0042004 0x00000007 0 } if { [expr ($ENABLE_LOW_POWER == 0)] } { # Disable debug during low power modes # DBGMCU_CR |= ~(DBG_STANDBY | DBG_STOP | DBG_SLEEP) mmw 0xE0042004 0 0x00000007 } if { [expr ($STOP_WATCHDOG == 1)] } { # Stop watchdog counters during halt # DBGMCU_CR |= DBG_WWDG_STOP | DBG_IWDG_STOP mmw 0xE0042004 0x00000300 0 } if { [expr ($STOP_WATCHDOG == 0)] } { # Don't stop watchdog counters during halt # DBGMCU_CR |= ~(DBG_WWDG_STOP | DBG_IWDG_STOP) mmw 0xE0042004 0 0x00000300 } Debug: 983 767 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1 Debug: 984 767 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 775 Debug: 985 767 command.c:145 script_debug(): command - mww ocd_mww 0xE0042004 775 Debug: 987 767 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1 Debug: 988 767 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0xe0042004 4 1 Debug: 989 767 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_mww 0xE0042004 775 Debug: 990 767 command.c:145 script_debug(): command - mww ocd_mww 0xE0042004 775 Debug: 992 767 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe0042004 4 1 Debug: 993 767 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event reset-assert-pre Debug: 994 767 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event reset-assert-pre Debug: 995 767 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 996 767 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 997 767 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu arp_reset assert 0 Debug: 998 767 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu arp_reset assert 0 Debug: 999 767 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas Debug: 1000 767 target.c:1624 print_wa_layout(): 0x20000000-0x20007fff (32768 bytes) Debug: 1001 767 hla_target.c:485 adapter_assert_reset(): adapter_assert_reset Debug: 1002 767 hla_interface.c:129 hl_interface_execute_queue(): hl_interface_execute_queue: ignored Debug: 1003 767 core.c:727 jtag_add_reset(): SRST line asserted Debug: 1004 767 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event reset-assert-post Debug: 1005 767 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event reset-assert-post Debug: 1006 767 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu invoke-event reset-deassert-pre Debug: 1007 767 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu invoke-event reset-deassert-pre Debug: 1008 767 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_transport select Debug: 1009 767 command.c:145 script_debug(): command - ocd_transport ocd_transport select Debug: 1010 767 command.c:145 script_debug(): command - ocd_command ocd_command type ocd_STM32F107VCTx.cpu arp_reset deassert 0 Debug: 1011 767 command.c:145 script_debug(): command - ocd_STM32F107VCTx.cpu ocd_STM32F107VCTx.cpu arp_reset deassert 0 Debug: 1012 767 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas Debug: 1013 767 target.c:1624 print_wa_layout(): 0x20000000-0x20007fff (32768 bytes) Debug: 1014 767 hla_target.c:548 adapter_deassert_reset(): adapter_deassert_reset Debug: 1015 767 hla_interface.c:129 hl_interface_execute_queue(): hl_interface_execute_queue: ignored Debug: 1016 767 core.c:731 jtag_add_reset(): SRST line released Debug: 1017 767 target.c:1501 target_call_event_callbacks(): target event 3 (resume-start) Debug: 1018 767 hla_target.c:600 adapter_resume(): adapter_resume 1 0x00000000 0 0 Debug: 1019 767 target.c:1883 target_free_all_working_areas_restore(): freeing all working areas Debug: 1020 767 target.c:1624 print_wa_layout(): 0x20000000-0x20007fff (32768 bytes) Debug: 1021 767 hla_target.c:752 adapter_read_memory(): adapter_read_memory 0x08000274 2 1 Debug: 1022 782 stlink_usb.c:478 stlink_usb_error_check(): SWD_AP_ERROR Debug: 1023 782 target.c:2254 target_read_u16(): address: 0x08000274 failed Debug: 1024 782 target.c:2314 target_write_u32(): address: 0xe000edfc, value: 0x01000000 Debug: 1025 782 hla_target.c:766 adapter_write_memory(): adapter_write_memory 0xe000edfc 4 1 Debug: 1026 782 stlink_usb.c:478 stlink_usb_error_check(): SWD_AP_ERROR Debug: 1027 782 target.c:2319 target_write_u32(): failed: -4 User : 1028 782 command.c:546 command_print(): in procedure 'program' in procedure 'reset' called at file "embedded:startup.tcl", line 507 in procedure 'ocd_bouncer' Debug: 1029 782 command.c:628 run_command(): Command failed with error code -4 User : 1030 782 command.c:689 command_run_line(): Debug: 1031 782 hla_interface.c:119 hl_interface_quit(): hl_interface_quit