-- this top level vhd used the -- SAB0600_4BitPWM.vhd made by lothar MIller form Okt.2012 -- https://www.mikrocontroller.net/attachment/highlight/158318 library ieee; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --LIBRARY lattice; --USE lattice.components.all; entity top_MACHX02 is Port ( system_toneTrigger : in STD_LOGIC; system_pwmSpeaker : out STD_LOGIC; system_controlLed : out STD_LOGIC ); end entity; architecture Behaviour of top_MACHX02 is -- lattice oscillator OSCH primitive component OSCH generic ( NOM_FREQ: string ); port ( STDBY : IN STD_LOGIC; OSC : OUT STD_LOGIC; SEDSTDBY : OUT STD_LOGIC ); end component; component SAB0600 Port ( clk : in STD_LOGIC; start : in STD_LOGIC; speaker : out STD_LOGIC ); end component; signal system_clk : STD_LOGIC; signal toneStart : STD_LOGIC; begin -- lattice internal oscillator OSCH primitive OSC0: OSCH generic map ( NOM_FREQ => "53.20") -- 53.2 MHz syssysclk port map ( STDBY => '0', OSC => system_clk, SEDSTDBY => OPEN); SAB0600_4BitPWM0: SAB0600 port map ( clk => system_clk, start=>system_ToneTrigger, speaker => system_pwmSpeaker ); system_controlLed <= system_toneTrigger; -- just to see if the trigger input has a signal end architecture;