%% open model
run ADPLL_HDL;

%% Modelparameter
fs = 50e6;
phasewidth = 15;
M = 4; % Phase Frequency Detector acumulator depth
% calculated
Ts  = 1/fs; 

%% PLL variables
f_des = 70.000e3;
f_var = 72.000e3;
phi_var = pi;
N_o = 1;
N_i = 1;
freq_n = 1;
sigma = 0.707;

% calculated
omega_n = 2*pi*freq_n;
k0 = (2*pi)/(2^phasewidth); 
kd = 1/(2*pi); % PFD gain (reciprocal of PFD range, for ex. EXOR-PD = 2/pi, for JK-FlipFlop = 1/pi)

FTW_ref = ceil(f_des*2^phasewidth/fs);
FTW_var = ceil(f_var*2^phasewidth/fs);

PTW_var = ceil((phi_var*2^phasewidth)/(2*pi));

b0 = ((2*sigma+omega_n*Ts)*omega_n*N_o) / (k0 * kd);
b1 = -(2*sigma*omega_n*N_o)/(k0*kd);