(kicad_pcb (version 4) (host pcbnew 4.0.7)
  (general
    (links 0)
    (no_connects 0)
    (area 50.851999 22.3322 156.285001 164.794001)
    (thickness 1.6)
    (drawings 5)
    (tracks 0)
    (zones 0)
    (modules 2)
    (nets 1)
  )
  (page A4)
  (layers
    (0 F.Cu signal)
    (31 B.Cu signal)
    (32 B.Adhes user)
    (33 F.Adhes user)
    (34 B.Paste user)
    (35 F.Paste user)
    (36 B.SilkS user)
    (37 F.SilkS user)
    (38 B.Mask user)
    (39 F.Mask user)
    (40 Dwgs.User user)
    (41 Cmts.User user)
    (42 Eco1.User user)
    (43 Eco2.User user)
    (44 Edge.Cuts user)
    (45 Margin user)
    (46 B.CrtYd user)
    (47 F.CrtYd user)
    (48 B.Fab user)
    (49 F.Fab user)
  )
  (setup
    (last_trace_width 0.25)
    (trace_clearance 0.2)
    (zone_clearance 0.508)
    (zone_45_only no)
    (trace_min 0.2)
    (segment_width 0.2)
    (edge_width 0.15)
    (via_size 0.6)
    (via_drill 0.4)
    (via_min_size 0.4)
    (via_min_drill 0.3)
    (uvia_size 0.3)
    (uvia_drill 0.1)
    (uvias_allowed no)
    (uvia_min_size 0.2)
    (uvia_min_drill 0.1)
    (pcb_text_width 0.3)
    (pcb_text_size 1.5 1.5)
    (mod_edge_width 0.15)
    (mod_text_size 1 1)
    (mod_text_width 0.15)
    (pad_size 1.524 1.524)
    (pad_drill 0.762)
    (pad_to_mask_clearance 0.2)
    (aux_axis_origin 0 0)
    (visible_elements FFFFFF7F)
    (pcbplotparams
      (layerselection 0x00030_80000001)
      (usegerberextensions false)
      (excludeedgelayer true)
      (linewidth 0.300000)
      (plotframeref false)
      (viasonmask false)
      (mode 1)
      (useauxorigin false)
      (hpglpennumber 1)
      (hpglpenspeed 20)
      (hpglpendiameter 15)
      (hpglpenoverlay 2)
      (psnegative false)
      (psa4output false)
      (plotreference true)
      (plotvalue true)
      (plotinvisibletext false)
      (padsonsilk false)
      (subtractmaskfromsilk false)
      (outputformat 1)
      (mirror false)
      (drillshape 1)
      (scaleselection 1)
      (outputdirectory ""))
  )
  (net 0 "")
  (net_class Default "Dies ist die voreingestellte Netzklasse."
    (clearance 0.2)
    (trace_width 0.25)
    (via_dia 0.6)
    (via_drill 0.4)
    (uvia_dia 0.3)
    (uvia_drill 0.1)
  )
  (module Private_Lips_footprint:BBB (layer B.Cu) (tedit 0)
    (at 103.251 23.749)
    (fp_text reference G*** (at 0 0) (layer F.Cu) hide)
    (fp_text value LOGO (at 0.75 0) (layer F.Cu) hide)
  )
  (module Wire_Pads:SolderWirePad_single_0-8mmDrill (layer F.Cu) (tedit 0)
    (at 62.103 61.468)
    (fp_text reference REF** (at 0 -2.54) (layer F.SilkS))
    (fp_text value SolderWirePad_single_0-8mmDrill (at 0 2.54) (layer F.Fab))
    (pad 1 thru_hole circle (at 0 0) (size 1.99898 1.99898) (drill 0.8001) (layers *.Cu *.Mask))
  )
  (gr_line (start 52.451 42.799) (end 52.832 42.164) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 156.21 42.164) (end 52.705 42.164) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 155.829 164.719) (end 156.21 42.164) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 50.927 164.465) (end 155.829 164.719) (angle 90) (layer Edge.Cuts) (width 0.15))
  (gr_line (start 52.451 42.799) (end 50.927 164.465) (angle 90) (layer Edge.Cuts) (width 0.15))
)
