Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.10.0.111.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. Tue Oct 24 12:09:37 2017 Command Line: synthesis -f machxo2_blinking_led_machxo2_blinking_led_lattice.synproj -gui -msgset ./Programming/FPGA/Lattice/wrk/promote.xml Synthesis options: The -a option is MachXO2. The -s option is 4. The -t option is TQFP144. The -d option is LCMXO2-7000HE. Using package TQFP144. Using performance grade 4. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-7000HE ### Package : TQFP144 ### Speed : 4 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = blinking_led. Target frequency = 200.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p /usr/local/diamond/3.10_x64/ispfpga/xo2c00/data (searchpath added) -p ./Programming/FPGA/Lattice/wrk/machxo2_blinking_led (searchpath added) -p ./Programming/FPGA/Lattice/wrk (searchpath added) VHDL library = work VHDL design file = ./Programming/FPGA/Lattice/wrk/machxo2_blinking_led/source/blinking_led.vhd NGD file = machxo2_blinking_led_machxo2_blinking_led.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file /usr/local/diamond/3.10_x64/ispfpga/userware/unix/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin INFO - synthesis: The default VHDL library search path is now " ./Programming/FPGA/Lattice/wrk/machxo2_blinking_led". VHDL-1504 Analyzing VHDL file ./Programming/FPGA/Lattice/wrk/machxo2_blinking_led/source/blinking_led.vhd. VHDL-1481 INFO - synthesis: ./Programming/FPGA/Lattice/wrk/machxo2_blinking_led/source/blinking_led.vhd(32): analyzing entity blinking_led. VHDL-1012 INFO - synthesis: ./Programming/FPGA/Lattice/wrk/machxo2_blinking_led/source/blinking_led.vhd(37): analyzing architecture behavior. VHDL-1010 unit blinking_led is not yet analyzed. VHDL-1485 unit blinking_led is not yet analyzed. VHDL-1485 ./Programming/FPGA/Lattice/wrk/machxo2_blinking_led/source/blinking_led.vhd(32): executing blinking_led(behavior) WARNING - synthesis: ./Programming/FPGA/Lattice/wrk/machxo2_blinking_led/source/blinking_led.vhd(35): replacing existing netlist blinking_led(behavior). VHDL-1205 Top module name (VHDL): blinking_led Loading NGL library '/usr/local/diamond/3.10_x64/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library '/usr/local/diamond/3.10_x64/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.10_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.10_x64/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/3.10_x64/ispfpga. Package Status: Final Version 1.39. Top-level module name = blinking_led. GSR will not be inferred because no asynchronous signal was found in the netlist. Applying 200.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in blinking_led_drc.log. Loading NGL library '/usr/local/diamond/3.10_x64/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library '/usr/local/diamond/3.10_x64/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library '/usr/local/diamond/3.10_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library '/usr/local/diamond/3.10_x64/ispfpga/or5g00/data/orc5glib.ngl'... All blocks are expanded and NGD expansion is successful. Writing NGD file machxo2_blinking_led_machxo2_blinking_led.ngd. ################### Begin Area Report (blinking_led)###################### Number of register bits => 29 of 7209 (0 % ) CCU2D => 13 FD1S3AX => 4 FD1S3IX => 25 GSR => 1 LUT4 => 25 OB => 4 OSCH => 1 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 1 Net : clk, loads : 29 Clock Enable Nets Number of Clock Enables: 0 Top 0 highest fanout Clock Enables: Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : n243, loads : 26 Net : count_23, loads : 4 Net : count_22, loads : 4 Net : count_21, loads : 4 Net : count_20, loads : 4 Net : count_16, loads : 4 Net : count_15, loads : 4 Net : count_14, loads : 4 Net : count_13, loads : 4 Net : count_12, loads : 4 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 5.000000 -name | | | clk0 [get_nets clk] | 200.000 MHz| 76.185 MHz| 8 * | | | -------------------------------------------------------------------------------- 1 constraints not met. Peak Memory Usage: 206.035 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.666 secs --------------------------------------------------------------