library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity multiply is port ( sineWaveSignal : in signed( 15 downto 0); amplitude : in unsigned( 7 downto 0); mixerSum : out signed( 23 downto 0) ); end entity multiply; architecture rtl of multiply is signal amplitude_sgn : signed( 8 downto 0); signal result : signed( 24 downto 0); begin -- there is no uns * sgn defininition in VHDL! -- so convert uns --> sgn amplitude_sgn <= signed( resize( amplitude, amplitude_sgn'length)); result <= sineWaveSignal * amplitude_sgn; mixerSum <= resize( result, mixerSum'length); end architecture rtl;