// dac.h #pragma once #include typedef volatile struct /* dac_struct */ { // word access // 00 Control register (DAC_CR) uint32_t CR_EN1 : 1; // Chan.1 enable uint32_t CR_BOFF1 : 1; // Chan.1 output buffer disable uint32_t CR_TEN1 : 1; // Chan.1 trigger enable uint32_t CR_TSEL1 : 3; // Chan.1 trigger selection uint32_t CR_WAVE1 : 2; // Chan.1 noise/triangle wave generation enable uint32_t CR_MAMP1 : 4; // Chan.1 mask/amplitude selector uint32_t CR_DMAEN1 : 1; // Chan.1 DMA enable uint32_t CR_DMAUDRIE1 : 1; // Chan.1 DMA Underrun Interrupt enable uint32_t : 2; uint32_t CR_EN2 : 1; // Chan.2 enable uint32_t CR_BOFF2 : 1; // Chan.2 output buffer disable uint32_t CR_TEN2 : 1; // Chan.2 trigger enable uint32_t CR_TSEL2 : 3; // Chan.2 trigger selection uint32_t CR_WAVE2 : 2; // Chan.2 noise/triangle wave generation enable uint32_t CR_MAMP2 : 4; // Chan.2 mask/amplitude selector uint32_t CR_DMAEN2 : 1; // Chan.2 DMA enable uint32_t CR_DMAUDRIE2 : 1; // Chan.2 DMA underrun interrupt enable uint32_t : 2; // 04 Software trigger register (DAC_SWTRIGR) uint32_t SWTRIG_1 : 1; // Chan.1 software trigger uint32_t SWTRIG_2 : 1; // Chan.2 software trigger uint32_t : 30; // 08 Channel1 12-bit right-aligned data holding register (DAC_DHR12R1) uint32_t DHR12R1; // 0C Channel1 12-bit left aligned data holding register (DAC_DHR12L1) uint32_t rsvd_0C; // 10 Channel1 8-bit right aligned data holding register (DAC_DHR8R1) uint32_t rsvd_10; // 14 Channel2 12-bit right aligned data holding register (DAC_DHR12R2) uint32_t DHR12R2; // 18 Channel2 12-bit left aligned data holding register (DAC_DHR12L2) uint32_t rsvd_18; // 1C Channel2 8-bit right-aligned data holding register (DAC_DHR8R2) uint32_t rsvd_1C; // 20 DUAL DAC 12-bit right-aligned data holding register (DAC_DHR12RD) uint32_t DHR12RD; // 24 DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD) uint32_t rsvd_24; // 28 DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD) uint32_t rsvd_28; // 2C Channel1 data output register (DAC_DOR1) uint32_t DOR1; // 30 Channel2 data output register (DAC_DOR2) uint32_t DOR2; // 34 Status register (DAC_SR) uint32_t : 13; uint32_t SR_DMAUDR1 : 1; // Channel1 DMA underrun flag uint32_t : 2; uint32_t : 13; uint32_t SR_DMAUDR2 : 1; // Channel2 DMA underrun flag uint32_t : 2; } dac_struct; _Static_assert (sizeof(dac_struct) == 56, " dac_struct: bad size"); static dac_struct * const DAC = (dac_struct *)0x40007400;