Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version1733598
date_generatedSun Feb 11 17:17:32 2018 os_platformLIN64
product_versionVivado v2016.4 (64-bit) project_id083c9b71d2504beeada93b5857200043
project_iteration23 random_id331b1626dae157768df24a0e29ce60db
registration_id210727995_1777512417_210616669_940 route_designTRUE
target_devicexc7z010 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-4790K CPU @ 4.00GHz cpu_speed3999.892 MHz
os_nameUbuntu os_releaseUbuntu 14.04.5 LTS
system_ram11.000 GB total_processors1

vivado_usage
java_command_handlers
addsources=6 autoconnectport=8 autoconnecttarget=19 closedesign=20
closeproject=1 coreview=1 createblockdesign=2 createhardwaredashboards=1
createtophdl=2 customizecore=1 customizersbblock=11 debugwizardcmdhandler=1
editdelete=7 editpaste=2 fliptoviewtaskimplementation=1 generateoutputforbdfile=1
launchprogramfpga=20 managecompositetargets=3 newhardwaredashboard=1 newproject=1
openblockdesign=10 openhardwaremanager=23 openrecenttarget=10 projectsettingscmdhandler=11
reporttimingsummary=2 resetlayout=1 runbitgen=35 runimplementation=1
runpowerestimation=1 runschematic=1 runsynthesis=5 savedesign=3
savefileproxyhandler=10 saversbdesign=7 settopnode=5 showpowerestimation=1
showproductguide=2 showview=19 simulationbreak=1 simulationclose=1
simulationrelaunch=107 simulationrestart=232 simulationrun=113 simulationrunall=2
simulationrunfortime=233 simulationstep=1 tclfind=1 timingconstraintswizard=1
unselectallcmdhandler=2 viewinsttempl=6 viewlayoutcmd=4 viewtaskimplementation=1
viewtaskprojectmanager=47 viewtasksimulation=1 viewtasksynthesis=6 waveformopenconfiguration=2
waveformsaveconfiguration=43 waveformsaveconfigurationas=3
other_data
guimode=17
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=5 export_simulation_ies=5
export_simulation_modelsim=5 export_simulation_questa=5 export_simulation_riviera=5 export_simulation_vcs=5
export_simulation_xsim=5 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=442 simulator_language=Mixed srcsetcount=6 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=2 carry4=16 fdce=59 fdpe=2
gnd=4 ibuf=2 ldce=33 lut1=65
lut2=3 lut3=4 lut4=9 lut5=43
lut6=36 mmcme2_adv=1 muxf7=2 muxf8=1
obuf=5 vcc=5
pre_unisim_transformation
bufg=2 carry4=16 fdce=59 fdpe=2
gnd=4 ibuf=2 ldce=33 lut1=65
lut2=3 lut3=4 lut4=9 lut5=43
lut6=36 mmcme2_adv=1 muxf7=2 muxf8=1
obuf=5 vcc=5

ip_statistics
IP_Integrator/1
bdsource=USER core_container=NA iptotal=1 maxhierdepth=0
numblks=1 numhdlrefblks=0 numhierblks=0 numhlsblks=0
numnonxlnxblks=0 numpkgbdblks=0 numreposblks=1 numsysgenblks=0
synth_mode=OOC_per_IP x_iplanguage=VHDL x_iplibrary=BlockDiagram x_ipname=ClockManager
x_ipvendor=xilinx.com x_ipversion=1.00.a
clk_wiz_v5_3_3_0/1
clkin1_period=10.0 clkin2_period=10.0 clock_mgr_type=NA component_name=ClockManager_clk_wiz_0_0
core_container=NA enable_axi=0 feedback_source=FDBK_AUTO feedback_type=SINGLE
iptotal=1 manual_override=false num_out_clk=1 primitive=MMCM
use_dyn_phase_shift=false use_dyn_reconfig=false use_inclk_stopped=false use_inclk_switchover=false
use_locked=true use_max_i_jitter=false use_min_o_jitter=false use_phase_alignment=true
use_power_down=false use_reset=true

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified]
results
pdrc-153=1 zps7-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
results
timing-17=26 timing-18=2 timing-20=33 timing-6=2

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") clocks=0.000499 confidence_level_clock_activity=Low
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=High
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=0.103330
die=xc7z010clg400-1 dsp_output_toggle=12.500000 dynamic=0.002185 effective_thetaja=11.5
enable_probability=0.990000 family=zynq ff_toggle=12.500000 flow_state=routed
heatsink=none i/o=0.001871 input_toggle=12.500000 junction_temp=26.2 (C)
logic=0.000043 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000 mgtvccaux_total_current=0.000000
mgtvccaux_voltage=1.800000 mmcm=0.000000 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=0.105515 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=clg400 pct_clock_constrained=0.280000 pct_inputs_defined=100 platform=lin64
process=typical ram_enable=50.000000 ram_write=50.000000 read_saif=False
set/reset_probability=0.000000 signal_rate=False signals=0.000021 simulation_file=None
speedgrade=-1 static_prob=False temp_grade=commercial thetajb=9.3 (C/W)
thetasa=0.0 (C/W) toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=11.5
user_junc_temp=26.2 (C) user_thetajb=9.3 (C/W) user_thetasa=0.0 (C/W) vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.000066
vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000
vccaux_static_current=0.011023 vccaux_total_current=0.011089 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000
vccbram_static_current=0.000212 vccbram_total_current=0.000212 vccbram_voltage=1.000000 vccint_dynamic_current=0.000394
vccint_static_current=0.003695 vccint_total_current=0.004089 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000
vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.000507
vcco33_static_current=0.001000 vcco33_total_current=0.001507 vcco33_voltage=3.300000 vcco_ddr_dynamic_current=0.000000
vcco_ddr_static_current=0.000000 vcco_ddr_total_current=0.000000 vcco_ddr_voltage=1.500000 vcco_mio0_dynamic_current=0.000000
vcco_mio0_static_current=0.000000 vcco_mio0_total_current=0.000000 vcco_mio0_voltage=1.800000 vcco_mio1_dynamic_current=0.000000
vcco_mio1_static_current=0.000000 vcco_mio1_total_current=0.000000 vcco_mio1_voltage=1.800000 vccpaux_dynamic_current=0.000000
vccpaux_static_current=0.010330 vccpaux_total_current=0.010330 vccpaux_voltage=1.800000 vccpint_dynamic_current=0.000000
vccpint_static_current=0.016287 vccpint_total_current=0.016287 vccpint_voltage=1.000000 vccpll_dynamic_current=0.000000
vccpll_static_current=0.003000 vccpll_total_current=0.003000 vccpll_voltage=1.800000 version=2016.4

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=2 bufgctrl_util_percentage=6.25
bufhce_available=48 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=8 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=4 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=8 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=2 mmcme2_adv_fixed=0 mmcme2_adv_used=1 mmcme2_adv_util_percentage=50.00
plle2_adv_available=2 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=80 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=60 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=120 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=60 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=2 carry4_functional_category=CarryLogic carry4_used=16
fdce_functional_category=Flop & Latch fdce_used=59 fdpe_functional_category=Flop & Latch fdpe_used=2
ibuf_functional_category=IO ibuf_used=2 ldce_functional_category=Flop & Latch ldce_used=33
lut1_functional_category=LUT lut1_used=33 lut2_functional_category=LUT lut2_used=3
lut3_functional_category=LUT lut3_used=4 lut4_functional_category=LUT lut4_used=9
lut5_functional_category=LUT lut5_used=43 lut6_functional_category=LUT lut6_used=36
mmcme2_adv_functional_category=Clock mmcme2_adv_used=1 muxf7_functional_category=MuxFx muxf7_used=2
muxf8_functional_category=MuxFx muxf8_used=1 obuf_functional_category=IO obuf_used=5
slice_logic
f7_muxes_available=8800 f7_muxes_fixed=0 f7_muxes_used=2 f7_muxes_util_percentage=0.02
f8_muxes_available=4400 f8_muxes_fixed=0 f8_muxes_used=1 f8_muxes_util_percentage=0.02
lut_as_logic_available=17600 lut_as_logic_fixed=0 lut_as_logic_used=123 lut_as_logic_util_percentage=0.70
lut_as_memory_available=6000 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=35200 register_as_flip_flop_fixed=0 register_as_flip_flop_used=61 register_as_flip_flop_util_percentage=0.17
register_as_latch_available=35200 register_as_latch_fixed=0 register_as_latch_used=33 register_as_latch_util_percentage=0.09
slice_luts_available=17600 slice_luts_fixed=0 slice_luts_used=123 slice_luts_util_percentage=0.70
slice_registers_available=35200 slice_registers_fixed=0 slice_registers_used=94 slice_registers_util_percentage=0.27
fully_used_lut_ff_pairs_fixed=0.27 fully_used_lut_ff_pairs_used=4 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=17600 lut_as_logic_fixed=0 lut_as_logic_used=123 lut_as_logic_util_percentage=0.70
lut_as_memory_available=6000 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=62
lut_ff_pairs_with_one_unused_lut_output_fixed=62 lut_ff_pairs_with_one_unused_lut_output_used=61 lut_flip_flop_pairs_available=17600 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=66 lut_flip_flop_pairs_util_percentage=0.38 slice_available=4400 slice_fixed=0
slice_used=50 slice_util_percentage=1.14 slicel_fixed=0 slicel_used=40
slicem_fixed=0 slicem_used=10 unique_control_sets_used=5 using_o5_and_o6_fixed=5
using_o5_and_o6_used=5 using_o5_output_only_fixed=5 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=118
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=296146 bogomips=7999 bram18=0 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=5
dsp=0 effort=2 estimated_expansions=111486 ff=94
global_clocks=2 high_fanout_nets=0 iob=7 lut=124
movable_instances=260 nets=324 pins=1512 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=4 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7z010clg400-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -shreg_min_size=default::3 -top=Top
-verilog_define=default::[not_specified]
usage
elapsed=00:00:18s hls_ip=0 memory_gain=422.961MB memory_peak=1448.371MB

xsim
command_line_options
-sim_mode=default::behavioral -sim_type=default::