---------------------------------------------------------------------------------- -- Company: www.kampis-elektroecke.de -- Engineer: Daniel Kampert -- -- Create Date: 27.05.2016 18:13:09 -- Design Name: -- Module Name: Sine_ROM - Sine_ROM_Arch -- Project Name: -- Target Devices: XC7Z010CLG400-1 -- Tool Versions: Vivado 2016.4 -- Description: Simple ROM with 16-bit sine wave data. -- This ROM contains the data for a single channel. -- -- Dependencies: -- -- Revision: -- Revision 0.01 27.05.2016 File Created -- -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Sine_ROM is Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; Address : in STD_LOGIC_VECTOR(6 downto 0); Data_Out: out STD_LOGIC_VECTOR(15 downto 0) ); end Sine_ROM; architecture Sine_ROM_Arch of Sine_ROM is signal Read_Address : STD_LOGIC_VECTOR(Address'range); type ROMData_t is array (0 to 99) of STD_LOGIC_VECTOR(15 downto 0); constant Sinus : ROMData_t := ( x"0000", x"0805", x"1002", x"17ee", x"1fc3", x"2777", x"2f04", x"3662", x"3d89", x"4472", x"4b16", x"516f", x"5776", x"5d25", x"6276", x"6764", x"6bea", x"7004", x"73ad", x"76e1", x"799e", x"7be1", x"7da7", x"7eef", x"7fb7", x"7fff", x"7fc6", x"7f0c", x"7dd3", x"7c1b", x"79e6", x"7737", x"7410", x"7074", x"6c67", x"67ed", x"630a", x"5dc4", x"5820", x"5222", x"4bd3", x"4537", x"3e55", x"3735", x"2fdd", x"2855", x"20a5", x"18d3", x"10e9", x"08ee", x"00e9", x"f8e4", x"f0e6", x"e8f7", x"e120", x"d967", x"d1d5", x"ca72", x"c344", x"bc54", x"b5a7", x"af46", x"a935", x"a37c", x"9e20", x"9926", x"9494", x"906e", x"8cb8", x"8976", x"86ab", x"845a", x"8286", x"8130", x"8059", x"8003", x"802d", x"80d8", x"8203", x"83ad", x"85d3", x"8875", x"8b8f", x"8f1d", x"931e", x"978c", x"9c63", x"a19e", x"a738", x"ad2b", x"b372", x"ba05", x"c0df", x"c7f9", x"cf4b", x"d6ce", x"de7a", x"e648", x"ee30", x"f629" ); begin process(Clock, Reset) is begin if(Reset = '1') then Read_Address <= (others => '0'); elsif(rising_edge(Clock)) then Read_Address <= Address; end if; end process; -- Set output to high impedance if reset is active Data_Out <= Sinus(to_integer(unsigned(Read_Address))) when (Reset = '0') else (others => 'X'); end Sine_ROM_Arch;