entity HW1Bsp2 is end HW1Bsp2; architecture abgabe of HW1Bsp2 is begin P1: process ---------------------------- Deklarationen ---------------------------------- subtype aBVector is bit_vector (8 to 23); -- Vektoren fuer Shift-Operationen variable vVec,vRes0,vRes: aBVector; subtype ashamt is integer range 0 to aBVector'high-aBVector'low+1; -- erlaubte Shift Amounts variable vShamt : ashamt; -- ================== Ab hier editieren ===================================== --------- SLL --------------------------------------------------------------- procedure my_sll (vector: in aBVector; shamt: in ashamt; result: out aBVector) is begin result(result'low to (result'high - shamt)) := vector((vector'low + shamt) to vector'high); result((result'high - shamt + 1) to result'high) := ((result'high - shamt + 1) to result'high => '0'); end procedure my_sll; --------- SRL --------------------------------------------------------------- procedure my_srl (vector: in aBVector; shamt: in ashamt; result: out aBVector) is begin result((result'low + shamt) to result'high) := vector(vector'low to (vector'high - shamt)); result(result'low to (result'low + shamt - 1)) := (result'low to (result'low + shamt - 1) => '0'); end procedure my_srl; --------- SRA --------------------------------------------------------------- procedure my_sra (vector: in aBVector; shamt: in ashamt; result: out aBVector) is begin result((result'low + shamt) to result'high) := vector(vector'low to (vector'high - shamt)); -- in case vector is negative left bit is true --> 2 complement fill with '1' if vector(vector'left) = '1' then result(result'low to (result'low + shamt - 1)) := (result'low to (result'low + shamt - 1) => '1'); else result(result'low to (result'low + shamt - 1)) := (result'low to (result'low + shamt - 1) => '0'); end if; end procedure my_sra; --------- ROR --------------------------------------------------------------- procedure my_ror (vector: in aBVector; shamt: in ashamt; result: out aBVector) is begin -- shift right result((result'low + shamt) to result'high) := vector(vector'low to (vector'high - shamt)); -- rotate shifted bits to left side of vector result(result'low to (result'low + shamt - 1)) := vector((vector'high - shamt + 1) to vector'high); end procedure my_ror; -- ================== Ende des zu editierenden Bereiches ==================== --------------------------------------------------------------------------- -- process P1: Sequential Statemants: Run Test Cases --------------------------------------------------------------------------- begin -- Test1 : sll 4 -------------- vVec := x"AAAF"; vShamt := 4; vRes0 := vVec sll vShamt; my_sll(vVec,vShamt,vRes); wait for 20 ns; -- Test 2: sll 12 -------------- vShamt := 12; vRes0 := vVec sll vShamt; my_sll(vVec,vShamt,vRes); wait for 20 ns; -- Test 3: srl 8 -------------- vshamt := 8; vRes0 := vVec srl vShamt; my_srl(vVec,vShamt,vRes); wait for 20 ns; -- Test 4: sra 4 -------------- vVec := x"AAAF"; vShamt := 4; vRes0 := vVec sra vShamt; my_sra(vVec,vShamt,vRes); wait for 20 ns; -- Test 5: sra 4 -------------- vVec := x"6AAF"; vShamt := 4; vRes0 := vVec sra vShamt; my_sra(vVec,vShamt,vRes); wait for 20 ns; -- Test 6: ror 12 -------------- vVec := x"A06A"; vShamt := 12; vRes0 := vVec ror vShamt; my_ror(vVec,vShamt,vRes); wait for 20 ns; report "Process P1 finished"; wait; end process P1; end architecture abgabe;