library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity Primzahlen is Port ( clk, reset: in STD_LOGIC; Zehner, Einer : out STD_LOGIC_VECTOR (6 downto 0)); -- 7->Zehner Segmente b+c, 6..0->Einer Segmente abcdefg end Primzahlen; architecture Behavioral of Primzahlen is type Rom8x8 is array (0 to 7) of std_logic_vector (7 downto 0); -- 2 3 5 7 11 13 17 19 constant Segmente : Rom8x8 := ("01101101", "01111001", "01101101", "01110000", "10110000", "11101101", "11110000", "11110011"); signal cnt : unsigned(2 downto 0) := "000"; begin cnt <= "000" when reset='1' else cnt+1 when rising_edge(clk); Zehner <= '0' & Segmente(to_integer(cnt))(7) & Segmente(to_integer(cnt))(7) & "0000"; Einer <= Segmente(to_integer(cnt))(6 downto 0); end Behavioral;