* OPA197 - Rev. B * Created by Ian Williams; August 29, 2017 * Created with Green-Williams-Lis Op Amp Macro-model Architecture * Copyright 2017 by Texas Instruments Corporation ****************************************************** * MACRO-MODEL SIMULATED PARAMETERS: ****************************************************** * OPEN-LOOP GAIN AND PHASE VS. FREQUENCY WITH RL, CL EFFECTS (Aol) * UNITY GAIN BANDWIDTH (GBW) * INPUT COMMON-MODE REJECTION RATIO VS. FREQUENCY (CMRR) * POWER SUPPLY REJECTION RATIO VS. FREQUENCY (PSRR) * DIFFERENTIAL INPUT IMPEDANCE (Zid) * COMMON-MODE INPUT IMPEDANCE (Zic) * OPEN-LOOP OUTPUT IMPEDANCE VS. FREQUENCY (Zo) * OUTPUT CURRENT THROUGH THE SUPPLY (Iout) * INPUT VOLTAGE NOISE DENSITY VS. FREQUENCY (en) * INPUT CURRENT NOISE DENSITY VS. FREQUENCY (in) * OUTPUT VOLTAGE SWING vs. OUTPUT CURRENT (Vo) * SHORT-CIRCUIT OUTPUT CURRENT (Isc) * QUIESCENT CURRENT (Iq) * SETTLING TIME VS. CAPACITIVE LOAD (ts) * SLEW RATE (SR) * SMALL SIGNAL OVERSHOOT VS. CAPACITIVE LOAD * LARGE SIGNAL RESPONSE * OVERLOAD RECOVERY TIME (tor) * INPUT BIAS CURRENT (Ib) * INPUT OFFSET CURRENT (Ios) * INPUT OFFSET VOLTAGE (Vos) * INPUT COMMON-MODE VOLTAGE RANGE (Vcm) * INPUT OFFSET VOLTAGE VS. INPUT COMMON-MODE VOLTAGE (Vos vs. Vcm) * INPUT/OUTPUT ESD CELLS (ESDin, ESDout) ****************************************************** .subckt OPA197 IN+ IN- VCC VEE OUT ****************************************************** * MODEL DEFINITIONS: .model ESD_SW VSWITCH(Ron=50 Roff=1e12 Von=700e-3 Voff=100e-3) .model OL_SW VSWITCH(Ron=1e-3 Roff=1e9 Von=900e-3 Voff=800e-3) .model OR_SW VSWITCH(Ron=10e-3 Roff=1e9 Von=10e-3 Voff=0) .model R_NOISELESS RES(T_ABS=-273.15) ****************************************************** V_OS N035 N041 17.12e-6 R1 N038 N036 R_NOISELESS 1e-3 R2 N047 ESDn R_NOISELESS 1e-3 R3 N059 0 R_NOISELESS 1e12 C1 N059 0 1 R4 VCC_B N058 R_NOISELESS 1e-3 C2 N058 0 1e-15 C3 N060 0 1e-15 R5 N060 VEE_B R_NOISELESS 1e-3 G1 N038 N039 N007 N006 1e-3 R6 MID N045 R_NOISELESS 1e12 VCM_MIN N046 VEE_B -0.1 R7 N046 MID R_NOISELESS 1e12 VCM_MAX N045 VCC_B 0.1 XVCM_CLAMP N039 MID N042 MID N045 N046 VCCS_EXT_LIM R8 N042 MID R_NOISELESS 1 C4 N043 MID 1e-15 R9 N042 N043 R_NOISELESS 1e-3 V4 N056 OUT 0 R10 MID N048 R_NOISELESS 1e12 R11 MID N049 R_NOISELESS 1e12 XIQp VIMON MID VCC MID VCCS_LIM_IQ XIQn MID VIMON MID VEE VCCS_LIM_IQ R12 VCC_B N012 R_NOISELESS 1e3 R13 N025 VEE_B R_NOISELESS 1e3 XCLAWp VIMON MID N012 VCC_B VCCS_LIM_CLAWp XCLAWn MID VIMON VEE_B N025 VCCS_LIM_CLAWn R14 VEE_CLP MID R_NOISELESS 1e3 R15 MID VCC_CLP R_NOISELESS 1e3 R16 N013 N012 R_NOISELESS 1e-3 R17 N026 N025 R_NOISELESS 1e-3 C5 MID N013 1e-15 C6 N026 MID 1e-15 R18 VOUT_S N049 R_NOISELESS 100 C7 VOUT_S MID 1e-12 G2 MID VCC_CLP N013 MID 1e-3 G3 MID VEE_CLP N026 MID 1e-3 XCL_AMP N010 N037 VIMON MID N016 N023 CLAMP_AMP_LO V_ISCp N010 MID 65 V_ISCn N037 MID -65 XOL_SENSE MID N063 N062 N065 OL_SENSE R19 N037 MID R_NOISELESS 1e12 R20 N023 MID R_NOISELESS 1 C8 N024 MID 1e-15 R21 MID N016 R_NOISELESS 1 R22 MID N010 R_NOISELESS 1e12 C9 MID N017 1e-15 XCLAW_AMP VCC_CLP VEE_CLP VOUT_S MID N014 N021 CLAMP_AMP_LO R23 VEE_CLP MID R_NOISELESS 1e12 R24 N021 MID R_NOISELESS 1 C10 N022 MID 1e-15 R25 MID N014 R_NOISELESS 1 R26 MID VCC_CLP R_NOISELESS 1e12 C11 MID N015 1e-15 XCL_SRC N017 N024 CL_CLAMP MID VCCS_LIM_4 XCLAW_SRC N015 N022 CLAW_CLAMP MID VCCS_LIM_3 R27 N014 N015 R_NOISELESS 1e-3 R28 N022 N021 R_NOISELESS 1e-3 R29 N016 N017 R_NOISELESS 1e-3 R30 N024 N023 R_NOISELESS 1e-3 R31 N063 MID R_NOISELESS 1 R32 N063 SW_OL R_NOISELESS 100 C12 SW_OL MID 1e-12 R33 VIMON N048 R_NOISELESS 100 C13 VIMON MID 1e-12 C_DIFF ESDp ESDn 1.6e-12 C_CMn ESDn MID 6.4e-12 C_CMp MID ESDp 6.4e-12 I_Q VCC VEE 1e-3 I_B N041 MID 5e-12 I_OS ESDn MID 3e-12 R34 IN+ ESDp R_NOISELESS 100 R35 IN- ESDn R_NOISELESS 100 R36 N033 MID R_NOISELESS 1 R37 N040 MID R_NOISELESS 1e12 R38 MID N019 R_NOISELESS 1 R39 MID N011 R_NOISELESS 1e12 XGR_AMP N011 N040 N018 MID N019 N033 CLAMP_AMP_HI XGR_SRC N020 N034 CLAMP MID VCCS_LIM_GR C17 MID N020 1e-15 C18 N034 MID 1e-15 V_GRn N040 MID -251 V_GRp N011 MID 251 R40 N019 N020 R_NOISELESS 1e-3 R41 N034 N033 R_NOISELESS 1e-3 R42 VSENSE N018 R_NOISELESS 1e-3 C19 MID N018 1e-15 R43 MID VSENSE R_NOISELESS 1e3 G5 N035 N036 N009 MID 1e-3 G8 MID CLAW_CLAMP N050 MID 1e-3 R45 MID CLAW_CLAMP R_NOISELESS 1e3 G9 MID CL_CLAMP CLAW_CLAMP MID 1e-3 R46 MID CL_CLAMP R_NOISELESS 1e3 R47 N057 VCLP R_NOISELESS 100 C24 MID VCLP 1e-12 E4 N057 MID CL_CLAMP MID 1 E5 N049 MID OUT MID 1 H1 N048 MID V4 1e3 S1 N052 N051 SW_OL MID OL_SW R52 MID ESDp R_NOISELESS 1e12 R53 ESDn MID R_NOISELESS 1e12 R58 N036 N035 R_NOISELESS 1e3 R59 N058 N059 R_NOISELESS 1e6 R60 N059 N060 R_NOISELESS 1e6 R67 N039 N038 R_NOISELESS 1e3 G15 MID VSENSE CLAMP MID 1e-3 V_ORp N032 VCLP 4 V_ORn N027 VCLP -4 V11 N029 N028 0 V12 N030 N031 0 H2 N061 MID V11 -1 H3 N064 MID V12 1 S2 VCC ESDn ESDn VCC ESD_SW S3 VCC ESDp ESDp VCC ESD_SW S4 ESDn VEE VEE ESDn ESD_SW S5 ESDp VEE VEE ESDp ESD_SW S6 VCC OUT OUT VCC ESD_SW S7 OUT VEE VEE OUT ESD_SW E1 MID 0 N059 0 1 G16 0 VCC_B VCC 0 1 G17 0 VEE_B VEE 0 1 R88 VCC_B 0 R_NOISELESS 1 R89 VEE_B 0 R_NOISELESS 1 S8 N030 CLAMP CLAMP N030 OR_SW S9 CLAMP N029 N029 CLAMP OR_SW Xe_n ESDp N041 VNSE Xi_nn ESDn MID FEMT Xi_np N041 MID FEMT XVCCS_LIMIT_1 N043 N047 MID N044 VCCS_LIM_1 XVCCS_LIMIT_2 N044 MID MID CLAMP VCCS_LIM_2 R44 N044 MID R_NOISELESS 1e6 R68 CLAMP MID R_NOISELESS 1e6 G7 MID N050 VSENSE MID 1e-6 R69 N050 MID R_NOISELESS 1e6 R72 N062 N061 R_NOISELESS 100 R75 N064 N065 R_NOISELESS 100 C27 N062 MID 1e-9 C28 N065 MID 1e-9 XVCCS_LIM_ZO N054 MID MID N055 VCCS_LIM_ZO C15 N007 N008 4.97e-10 R54 N007 MID R_NOISELESS 320 R55 N007 N008 R_NOISELESS 1e8 G13 MID N008 VCC_B MID 68.4e-3 Rsrc4 N008 MID R_NOISELESS 1 C16 N006 N005 4.97e-10 R56 N006 MID R_NOISELESS 320 R57 N006 N005 R_NOISELESS 1e8 G14 MID N005 VEE_B MID 68.4e-3 Rsrc2 N005 MID R_NOISELESS 1 Rx N056 N055 R_NOISELESS 3.25e5 Rdummy N056 MID R_NOISELESS 3.25e4 G4 MID N051 CL_CLAMP N056 90.91 Rdc1 N051 MID R_NOISELESS 1 R51 N051 N052 R_NOISELESS 1e4 R64 N052 MID R_NOISELESS 1184.21 G6 MID N053 N052 MID 9.44 C23 N052 N051 1.77e-5 R65 N053 N054 R_NOISELESS 1e4 R66 N054 MID R_NOISELESS 0.15 C26 N054 N053 1.06e-11 R70 N055 MID R_NOISELESS 1 R71 N053 MID R_NOISELESS 1 C21 CLAMP MID 1.13e-7 C29 N050 MID 7e-15 C20 N002 N001 7.234e-10 R50 N002 MID R_NOISELESS 2.2 R61 N002 N001 R_NOISELESS 1e4 G_adjust1 MID N001 ESDp MID 454e-6 Rsrc3 N001 MID R_NOISELESS 1 G18 MID N003 MID N002 1 Rsrc5 N003 MID R_NOISELESS 1 C22 N004 N003 7.234e-10 R62 N004 N003 R_NOISELESS 1e4 R63 N004 MID R_NOISELESS 2.2 G19 MID N009 MID N004 4545.45 Rsrc6 N009 MID R_NOISELESS 1 G10 MID N028 N027 MID 1 G11 MID N031 N032 MID 1 R48 N028 MID R_NOISELESS 1 R49 N031 MID R_NOISELESS 1 .ends OPA197 * .subckt CLAMP_AMP_HI VC+ VC- VIN COM VO+ VO- .param G=10 GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)} GVo- COM Vo- Value = {IF(V(VIN,COM)10e-3 | V(4,1)>10e-3),1,0)} .ends OL_SENSE * .subckt FEMT 1 2 .param FLWF=1e-3 .param GLFF=231e-6 .param RNVF=2.718 .model DVNF D KF={PWR(FLWF,0.5)/1e11} IS=1.0e-16 I1 0 7 10e-3 I2 0 8 10e-3 D1 7 0 DVNF D2 8 0 DVNF E1 3 6 7 8 {GLFF} R1 3 0 1e9 R2 3 0 1e9 R3 3 6 1e9 E2 6 4 5 0 10 R4 5 0 {RNVF} R5 5 0 {RNVF} R6 3 4 1e9 R7 4 0 1e9 G1 1 2 3 4 1e-6 .ends FEMT * .subckt VCCS_EXT_LIM VIN+ VIN- IOUT- IOUT+ VP+ VP- .param Gain = 1 G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VIN+,VIN-),V(VP-,VIN-), V(VP+,VIN-))} .ends VCCS_EXT_LIM * .subckt VCCS_LIM_3 VC+ VC- IOUT+ IOUT- .param Gain = 1 .param Ipos = 0.522 .param Ineg = -0.522 G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)} .ends VCCS_LIM_3 * .subckt VCCS_LIM_4 VC+ VC- IOUT+ IOUT- .param Gain = 1 .param Ipos = 1.044 .param Ineg = -1.044 G1 IOUT+ IOUT- VALUE={LIMIT(Gain*V(VC+,VC-),Ineg,Ipos)} .ends VCCS_LIM_4 * .subckt VCCS_LIM_CLAWp VC+ VC- IOUT+ IOUT- G1 IOUT+ IOUT- TABLE {abs(V(VC+,VC-))} = +(0, 1e-5) +(31.9, 1.41e-3) +(44.7, 2.13e-3) +(57.1, 3.04e-3) +(63.8, 3.76e-3) +(66.5, 4.23e-3) +(67.7, 4.54e-3) +(68.9, 1.77e-2) .ends VCCS_LIM_CLAWp * .subckt VCCS_LIM_CLAWn VC+ VC- IOUT+ IOUT- G1 IOUT+ IOUT- TABLE {abs(V(VC+,VC-))} = +(0, 2.4e-4) +(15.9, 6.9e-4) +(63.8, 3.18e-3) +(67.7, 3.54e-3) +(68.9, 1.8e-2) .ends VCCS_LIM_CLAWn * .subckt VCCS_LIM_IQ VC+ VC- IOUT+ IOUT- .param Gain = 1e-3 G1 IOUT+ IOUT- VALUE={IF( (V(VC+,VC-)<=0),0,Gain*V(VC+,VC-) )} .ends VCCS_LIM_IQ * .subckt VNSE 1 2 .param FLW=0.1 .param GLF=0.1352 .param RNV=35.8 .model DVN D KF={PWR(FLW,0.5)/1E11} IS=1.0E-16 I1 0 7 10E-3 I2 0 8 10E-3 D1 7 0 DVN D2 8 0 DVN E1 3 6 7 8 {GLF} R1 3 0 1E9 R2 3 0 1E9 R3 3 6 1E9 E2 6 4 5 0 10 R4 5 0 {RNV} R5 5 0 {RNV} R6 3 4 1E9 R7 4 0 1E9 E3 1 2 3 4 1 .ends VNSE * .subckt CLAMP_AMP_LO VC+ VC- VIN COM VO+ VO- .param G=1 GVo+ COM Vo+ Value = {IF(V(VIN,COM)>V(VC+,COM),((V(VIN,COM)-V(VC+,COM))*G),0)} GVo- COM Vo- Value = {IF(V(VIN,COM)