library IEEE;
use IEEE.std_logic_1164.all; 
library lpm; -- required for all lpm functions 
use lpm.lpm_components.all; 

entity io_ram is 


port(  address : in std_logic_vector(3 downto 0); 
         data : inout std_logic_vector(7 downto 0); 
         write_enable : in std_logic; 
         clk : in std_logic; 
         outputen : in std_logic  
); 
end io_ram; 


architecture test of io_ram is 


-- component declaration for lpm_ram_io 


COMPONENT lpm_ram_io 


GENERIC (   LPM_WIDTH: POSITIVE; 
                      LPM_TYPE: STRING := "LPM_RAM_IO"; 
                      LPM_WIDTHAD: POSITIVE; 
                      LPM_NUMWORDS: NATURAL := 0; 
                      LPM_FILE: STRING := "UNUSED"; 
                      LPM_INDATA: STRING := "REGISTERED"; 
                      LPM_ADDRESS_CONTROL: STRING := "REGISTERED"; 
                      LPM_OUTDATA: STRING := "REGISTERED"; 
                      LPM_HINT: STRING := "UNUSED"); 


PORT (        address: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);  
                    we: IN STD_LOGIC; 
                    inclock: IN STD_LOGIC := '0';  
                   outclock: IN STD_LOGIC := '0';  
                   outenab: IN STD_LOGIC := '1'; 
                   memenab: IN STD_LOGIC := '1';  
                   dio: INOUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)); 


END COMPONENT; 


Begin 


ram_instance: COMPONENTlpm_ram_io  


GENERIC MAP(  LPM_WIDTH => 8,  
                              LPM_WIDTHAD => 4 
                           ) 


PORT MAP ( address => address,  
                       we => write_enable, 
                       inclock => clk,  
                       outclock => clk, 
                       outenab => outputen, 
                       dio => data 
); 


end test;