-- Title: Binary-to-BCD Converter library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity DUAL2BCD is port ( RESET: in std_logic; CLK: in std_logic; START: in std_logic; BINARY: in std_logic_vector(15 downto 0); READY: out std_logic; DECIMAL: out std_logic_vector(18 downto 0) ); end DUAL2BCD; architecture behavior of DUAL2BCD is signal z: std_logic_vector(34 downto 0); TYPE state IS (start_state, state_working0, state_working1, state_working2, state_working3, state_working4); signal current_state : state; signal zaehler: std_logic_vector(3 downto 0); begin process (RESET, CLK) begin if RESET = '1' then z <= (others => '0'); DECIMAL <= (others => '0'); READY <= '0'; zaehler <= "0000"; current_state <= start_state; elsif CLK'event and CLK = '1' then case current_state is when start_state => if START = '1' then z(18 downto 3) <= BINARY; current_state <= state_working0; READY <= '0'; end if; when state_working0 => if z(19 downto 16) > 4 then z(19 downto 16) <= z(19 downto 16) + 3; end if; current_state <= state_working1; when state_working1 => if z(23 downto 20) > 4 then z(23 downto 20) <= z(23 downto 20) + 3; end if; current_state <= state_working2; when state_working2 => if z(27 downto 24) > 4 then z(27 downto 24) <= z(27 downto 24) + 3; end if; current_state <= state_working3; when state_working3 => if z(31 downto 28) > 4 then z(31 downto 28) <= z(31 downto 28) + 3; end if; current_state <= state_working4; when state_working4 => z(34 downto 1) <= z(33 downto 0); if zaehler = 12 then zaehler <= "0000"; current_state <= start_state; DECIMAL <= z(34 downto 16); READY <= '1'; else zaehler <= zaehler + 1; current_state <= state_working0; end if; end case; end if; end process; end behavior;