-------------------------------------------------------------------------------- -- Engineer: Lothar Miller -- -- Create Date: 11:56:39 08/18/2008 -- Design Name: CheckVect -------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY tb_CheckVect_vhd IS END tb_CheckVect_vhd; ARCHITECTURE behavior OF tb_CheckVect_vhd IS SIGNAL sig : std_logic_vector(7 downto 0) := (others=>'0'); --====================================================================-- procedure CheckValid (vect : std_logic_vector) is variable flag : boolean; begin wait for 0 ps; -- Signal zuweisen flag := is_X (vect); assert (flag=false) report "Metavalue in Vector" severity FAILURE; end CheckValid; --====================================================================-- BEGIN tb : PROCESS BEGIN sig <= x"44"; CheckValid (sig); wait for 100 ns; sig <= x"55"; CheckValid (sig); wait for 100 ns; sig <= "101UX101"; CheckValid (sig); wait for 100 ns; wait; -- will wait forever END PROCESS; END;