library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use ieee.math_real.all; entity FT2232H_minimal_C is Port( clk100: in std_logic; -- FT2232H D: out std_logic_vector(7 downto 0); RXF: in std_logic; TXE: in std_logic; RD: out std_logic; WR: out std_logic; SIWU: out std_logic; CLKOUT: in std_logic; --60MHz FTDI OE: out std_logic; PWRSAV: out std_logic); end FT2232H_minimal_C; architecture Behavioral of FT2232H_minimal_C is component fifo_generator_0 IS PORT( rst : IN STD_LOGIC; wr_clk : IN STD_LOGIC; rd_clk : IN STD_LOGIC; din : IN STD_LOGIC_VECTOR(7 DOWNTO 0); wr_en : IN STD_LOGIC; rd_en : IN STD_LOGIC; dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); full : OUT STD_LOGIC; wr_ack : OUT STD_LOGIC; overflow : OUT STD_LOGIC; empty : OUT STD_LOGIC; valid : OUT STD_LOGIC; underflow : OUT STD_LOGIC; prog_full : OUT STD_LOGIC); end component; --------------------- FIFO & FT2232H------------------------------------------------- signal counter: unsigned(8 downto 0):=(others => '0'); signal new_burst: std_logic:='0'; signal fifo_miss: unsigned(3 downto 0):=(others => '0'); type fsm_fifo_type is(fifo_reset, fifo_check, fifo_write, fifo_wait); signal fsm_fifo: fsm_fifo_type:=fifo_reset; signal ft2232h_write: std_logic:='0'; signal fifo_wr_counter: integer range 0 to 255:=0; signal txe_buff: std_logic:='0'; signal fifo_rst_init_counter: unsigned(7 downto 0):=(others => '0'); signal fifo_rst: std_logic:='0'; signal fifo_wr_en: std_logic:='0'; signal fifo_rd_en: std_logic:='0'; signal fifo_din: std_logic_vector(7 downto 0):=(others => '0'); signal fifo_do: std_logic_vector(7 downto 0):=(others => '0'); signal fifo_full: std_logic:='0'; signal fifo_wr_ack: std_logic:='0'; signal fifo_prog_full: std_logic:='0'; signal fifo_empty: std_logic:='0'; signal fifo_overflow: std_logic:='0'; signal fifo_valid: std_logic:='0'; signal fifo_underflow: std_logic:='0'; begin fifo0: fifo_generator_0 PORT MAP( rst => fifo_rst, wr_clk => clk100, rd_clk => not CLKOUT, din => fifo_din, wr_en => fifo_wr_en, rd_en => fifo_rd_en, dout => D, full => fifo_full, wr_ack => fifo_wr_ack, overflow => fifo_overflow, empty => fifo_empty, valid => fifo_valid, underflow => fifo_underflow, prog_full => fifo_prog_full); process begin wait until rising_edge(clk100); counter <= counter +1; new_burst <= '0'; if counter = 0 then new_burst <= '1'; end if; --------- write to FIFO ----------------------------------------------------------------- fifo_wr_en <= '0'; if fsm_fifo = fifo_reset then fifo_rst_init_counter <= fifo_rst_init_counter +1; if fifo_rst_init_counter < 32 then fifo_rst <= '1'; end if; if fifo_rst_init_counter = 32 then fifo_rst <= '0'; end if; if fifo_rst_init_counter = 255 then fifo_rst <= '0'; fsm_fifo <= fifo_wait; end if; elsif fsm_fifo = fifo_wait then if new_burst = '1' then fsm_fifo <= fifo_check; fifo_wr_counter <= 0; end if; elsif fsm_fifo = fifo_check then if fifo_prog_full = '0' then fsm_fifo <= fifo_write; end if; elsif fsm_fifo = fifo_write then fifo_wr_en <= '1'; fifo_din <= std_logic_vector(to_unsigned(fifo_wr_counter,8)); if fifo_wr_counter < 255 then fifo_wr_counter <= fifo_wr_counter +1; end if; if fifo_wr_counter = 255 then fsm_fifo <= fifo_wait; end if; end if; end process; ------------ FT232H sync FIFO--------------------------------------------- RD <= '1'; SIWU <= '1'; OE <= '1'; PWRSAV <= 'Z'; process begin wait until rising_edge(CLKOUT); TXE_buff <= TXE; WR <= '1'; fifo_rd_en <= '0'; if TXE = '0' then if TXE_buff = '0' and fifo_empty = '0' then fifo_rd_en <= '1'; WR <= '0'; ft2232h_write <= '1'; end if; if TXE_buff = '1' and ft2232h_write <= '1' then WR <= '0'; ft2232h_write <= '0'; end if; else WR <= '1'; end if; TXE_buff <= TXE; end process; end Behavioral;