WARNING:Simulator:434 - Module uart does not have a `timescale directive but previous modules do. WARNING:Simulator:13 - For instance /system_tb/dut/ddr0/, width 3 of formal port ddr_clk is not equal to width 1 of actual signal ddr_clk. WARNING:Simulator:13 - For instance /system_tb/dut/ddr0/, width 3 of formal port ddr_clk_n is not equal to width 1 of actual signal ddr_clk_n. WARNING:Simulator:13 - For instance /system_tb/dut/ddr0/, width 2 of formal port ddr_cke is not equal to width 1 of actual signal ddr_cke. WARNING:Simulator:13 - For instance /system_tb/dut/ddr0/, width 2 of formal port ddr_cs_n is not equal to width 1 of actual signal ddr_cs_n. WARNING:Simulator:13 - For instance /system_tb/dut/ddr0/, width 8 of formal port probe_sel is not equal to width 32 of actual constant. WARNING:Simulator:12 - Port DSSEN of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_fx/ is left unconnected. WARNING:Simulator:12 - Port CLK0 of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_fx/ is left unconnected. WARNING:Simulator:12 - Port CLK180 of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_fx/ is left unconnected. WARNING:Simulator:12 - Port CLK270 of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_fx/ is left unconnected. WARNING:Simulator:12 - Port CLK2X of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_fx/ is left unconnected. WARNING:Simulator:12 - Port CLK2X180 of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_fx/ is left unconnected. WARNING:Simulator:12 - Port CLK90 of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_fx/ is left unconnected. WARNING:Simulator:12 - Port CLKDV of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_fx/ is left unconnected. WARNING:Simulator:12 - Port CLKFX180 of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_fx/ is left unconnected. WARNING:Simulator:12 - Port PSDONE of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_fx/ is left unconnected. WARNING:Simulator:12 - Port STATUS of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_fx/ is left unconnected. WARNING:Simulator:12 - Port CLKFB of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_fx/ is left unconnected. WARNING:Simulator:12 - Port DSSEN of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_phase/ is left unconnected. WARNING:Simulator:12 - Port CLK2X of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_phase/ is left unconnected. WARNING:Simulator:12 - Port CLK2X180 of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_phase/ is left unconnected. WARNING:Simulator:12 - Port CLKDV of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_phase/ is left unconnected. WARNING:Simulator:12 - Port CLKFX of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_phase/ is left unconnected. WARNING:Simulator:12 - Port CLKFX180 of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_phase/ is left unconnected. WARNING:Simulator:12 - Port STATUS of module DCM in instance /system_tb/dut/ddr0/ctrl0/clkgen/dcm_phase/ is left unconnected. This is a Lite version of ISE Simulator. Simulator is doing circuit initialization process. Finished circuit initialization process. WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Cas_n:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Ras_n:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( We_n:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Addr:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Ba:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) WARNING:Simulator:29 - at 565.488 ns: Warning: Timing violation in /system_tb/mt46v16m16/ $setuphold( Ba:565.388 ns, Clk:565.488 ns,750.000 ps,750.000 ps) run all Reading from UART: rx_data=2a Reading from UART: rx_data=2a Reading from UART: rx_data=73 Reading from UART: rx_data=6f Reading from UART: rx_data=63 Reading from UART: rx_data=2d Reading from UART: rx_data=6c Reading from UART: rx_data=6d Reading from UART: rx_data=33 Reading from UART: rx_data=32 Reading from UART: rx_data=2f Reading from UART: rx_data=62 Reading from UART: rx_data=6f Reading from UART: rx_data=6f Reading from UART: rx_data=74 Reading from UART: rx_data=6c Reading from UART: rx_data=6f Reading from UART: rx_data=61 Reading from UART: rx_data=64 Reading from UART: rx_data=65 Reading from UART: rx_data=72 Reading from UART: rx_data=2a Reading from UART: rx_data=2a Reading from UART: rx_data=20 Reading from UART: rx_data=3e Reading from UART: rx_data=20 Reading from UART: rx_data=0d Reading from UART: rx_data=0a At time 406886.000 ns PRE : Addr[10] = 1, Bank = 00 At time 406909.000 ns PRE : Addr[10] = 1, Bank = 00 At time 406932.000 ns EMR : Extended Mode Register At time 406932.000 ns EMR : Enable DLL At time 406955.000 ns LMR : Load Mode Register At time 406955.000 ns LMR : Burst Length = 8 At time 406955.000 ns LMR : CAS Latency = 2.5 At time 406978.000 ns PRE : Addr[10] = 1, Bank = 00 At time 407001.000 ns AREF : Auto Refresh At time 407117.000 ns AREF : Auto Refresh At time 407117.000 ns ERROR: tRFC violation during Auto Refresh system_tb.mt46v16m16: at time 407117.000 ns MEMORY: Power Up and Initialization Sequence is complete At time 407232.000 ns LMR : Load Mode Register At time 407232.000 ns ERROR: tRFC violation during Load Mode Register At time 407232.000 ns LMR : Burst Length = 8 At time 407232.000 ns LMR : CAS Latency = 2.5 At time 407255.000 ns PRE : Addr[10] = 1, Bank = 00 At time 407278.000 ns AREF : Auto Refresh Writing to UART: tx_data=64 At time 422463.000 ns PRE : Addr[10] = 1, Bank = 00 At time 422486.000 ns AREF : Auto Refresh Writing to UART: done. Writing to UART: tx_data=00 Writing to UART: done. Writing to UART: tx_data=00 At time 438086.000 ns PRE : Addr[10] = 1, Bank = 00 At time 438109.000 ns AREF : Auto Refresh Writing to UART: done. Writing to UART: tx_data=00 Writing to UART: done. Writing to UART: tx_data=08 At time 453701.000 ns PRE : Addr[10] = 1, Bank = 00 At time 453724.000 ns AREF : Auto Refresh Writing to UART: done. Writing to UART: done. Writing to UART: tx_data=00 Writing to UART: done. Writing to UART: tx_data=00 Writing to UART: done. Writing to UART: tx_data=00 At time 469324.000 ns PRE : Addr[10] = 1, Bank = 00 At time 469347.000 ns AREF : Auto Refresh Writing to UART: done. Writing to UART: tx_data=04 At time 484947.000 ns PRE : Addr[10] = 1, Bank = 00 At time 484970.000 ns AREF : Auto Refresh Reading from UART: rx_data=78 Reading from UART: rx_data=01 At time 500563.000 ns PRE : Addr[10] = 1, Bank = 00 At time 500586.000 ns AREF : Auto Refresh Reading from UART: rx_data=00 Reading from UART: rx_data=00 At time 516186.000 ns PRE : Addr[10] = 1, Bank = 00 At time 516209.000 ns AREF : Auto Refresh At time 531801.000 ns PRE : Addr[10] = 1, Bank = 00 At time 531824.000 ns AREF : Auto Refresh At time 547424.000 ns PRE : Addr[10] = 1, Bank = 00 At time 547447.000 ns AREF : Auto Refresh At time 563047.000 ns PRE : Addr[10] = 1, Bank = 00 At time 563070.000 ns AREF : Auto Refresh Writing to UART: tx_data=64 At time 578663.000 ns PRE : Addr[10] = 1, Bank = 00 At time 578686.000 ns AREF : Auto Refresh Writing to UART: done. Writing to UART: tx_data=04 Writing to UART: done. Writing to UART: tx_data=00 At time 594286.000 ns PRE : Addr[10] = 1, Bank = 00 At time 594309.000 ns AREF : Auto Refresh Writing to UART: done. Writing to UART: tx_data=00 Writing to UART: done. Writing to UART: tx_data=08 At time 609901.000 ns PRE : Addr[10] = 1, Bank = 00 At time 609924.000 ns AREF : Auto Refresh Writing to UART: done. Writing to UART: done. Writing to UART: tx_data=00 Writing to UART: done. Writing to UART: tx_data=00 Writing to UART: done. Writing to UART: tx_data=00 At time 625524.000 ns PRE : Addr[10] = 1, Bank = 00 At time 625547.000 ns AREF : Auto Refresh Writing to UART: done. Writing to UART: tx_data=04 At time 641147.000 ns PRE : Addr[10] = 1, Bank = 00 At time 641170.000 ns AREF : Auto Refresh At time 656763.000 ns PRE : Addr[10] = 1, Bank = 00 At time 656786.000 ns AREF : Auto Refresh At time 672386.000 ns PRE : Addr[10] = 1, Bank = 00 At time 672409.000 ns AREF : Auto Refresh At time 688001.000 ns PRE : Addr[10] = 1, Bank = 00 At time 688024.000 ns AREF : Auto Refresh At time 703624.000 ns PRE : Addr[10] = 1, Bank = 00 At time 703647.000 ns AREF : Auto Refresh At time 719247.000 ns PRE : Addr[10] = 1, Bank = 00 At time 719270.000 ns AREF : Auto Refresh At time 734863.000 ns PRE : Addr[10] = 1, Bank = 00 At time 734886.000 ns AREF : Auto Refresh At time 750486.000 ns PRE : Addr[10] = 1, Bank = 00 At time 750509.000 ns AREF : Auto Refresh At time 766101.000 ns PRE : Addr[10] = 1, Bank = 00 At time 766124.000 ns AREF : Auto Refresh At time 781724.000 ns PRE : Addr[10] = 1, Bank = 00 At time 781747.000 ns AREF : Auto Refresh At time 797347.000 ns PRE : Addr[10] = 1, Bank = 00 At time 797370.000 ns AREF : Auto Refresh At time 812963.000 ns PRE : Addr[10] = 1, Bank = 00 At time 812986.000 ns AREF : Auto Refresh At time 828586.000 ns PRE : Addr[10] = 1, Bank = 00 At time 828609.000 ns AREF : Auto Refresh At time 844201.000 ns PRE : Addr[10] = 1, Bank = 00 At time 844224.000 ns AREF : Auto Refresh At time 859824.000 ns PRE : Addr[10] = 1, Bank = 00 At time 859847.000 ns AREF : Auto Refresh At time 875447.000 ns PRE : Addr[10] = 1, Bank = 00 At time 875470.000 ns AREF : Auto Refresh At time 891063.000 ns PRE : Addr[10] = 1, Bank = 00 At time 891086.000 ns AREF : Auto Refresh At time 906686.000 ns PRE : Addr[10] = 1, Bank = 00 At time 906709.000 ns AREF : Auto Refresh At time 922301.000 ns PRE : Addr[10] = 1, Bank = 00 At time 922324.000 ns AREF : Auto Refresh At time 937924.000 ns PRE : Addr[10] = 1, Bank = 00 At time 937947.000 ns AREF : Auto Refresh At time 953547.000 ns PRE : Addr[10] = 1, Bank = 00 At time 953570.000 ns AREF : Auto Refresh At time 969163.000 ns PRE : Addr[10] = 1, Bank = 00 At time 969186.000 ns AREF : Auto Refresh At time 984786.000 ns PRE : Addr[10] = 1, Bank = 00 At time 984809.000 ns AREF : Auto Refresh At time 1000401.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1000424.000 ns AREF : Auto Refresh At time 1016024.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1016047.000 ns AREF : Auto Refresh At time 1031647.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1031670.000 ns AREF : Auto Refresh At time 1047263.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1047286.000 ns AREF : Auto Refresh At time 1062886.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1062909.000 ns AREF : Auto Refresh At time 1078501.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1078524.000 ns AREF : Auto Refresh At time 1094124.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1094147.000 ns AREF : Auto Refresh At time 1109747.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1109770.000 ns AREF : Auto Refresh At time 1125363.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1125386.000 ns AREF : Auto Refresh At time 1140986.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1141009.000 ns AREF : Auto Refresh At time 1156601.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1156624.000 ns AREF : Auto Refresh At time 1172224.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1172247.000 ns AREF : Auto Refresh At time 1187847.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1187870.000 ns AREF : Auto Refresh At time 1203463.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1203486.000 ns AREF : Auto Refresh At time 1219086.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1219109.000 ns AREF : Auto Refresh At time 1234701.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1234724.000 ns AREF : Auto Refresh At time 1250324.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1250347.000 ns AREF : Auto Refresh At time 1265947.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1265970.000 ns AREF : Auto Refresh At time 1281563.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1281586.000 ns AREF : Auto Refresh At time 1297186.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1297209.000 ns AREF : Auto Refresh At time 1312801.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1312824.000 ns AREF : Auto Refresh At time 1328424.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1328447.000 ns AREF : Auto Refresh At time 1344047.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1344070.000 ns AREF : Auto Refresh At time 1359663.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1359686.000 ns AREF : Auto Refresh At time 1375286.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1375309.000 ns AREF : Auto Refresh At time 1390901.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1390924.000 ns AREF : Auto Refresh At time 1406524.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1406547.000 ns AREF : Auto Refresh At time 1422147.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1422170.000 ns AREF : Auto Refresh At time 1437763.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1437786.000 ns AREF : Auto Refresh At time 1453386.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1453409.000 ns AREF : Auto Refresh At time 1469001.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1469024.000 ns AREF : Auto Refresh At time 1484624.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1484647.000 ns AREF : Auto Refresh At time 1500247.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1500270.000 ns AREF : Auto Refresh At time 1515863.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1515886.000 ns AREF : Auto Refresh At time 1531486.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1531509.000 ns AREF : Auto Refresh At time 1547101.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1547124.000 ns AREF : Auto Refresh At time 1562724.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1562747.000 ns AREF : Auto Refresh At time 1578347.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1578370.000 ns AREF : Auto Refresh At time 1593963.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1593986.000 ns AREF : Auto Refresh At time 1609586.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1609609.000 ns AREF : Auto Refresh At time 1625201.000 ns PRE : Addr[10] = 1, Bank = 00 At time 1625224.000 ns AREF : Auto Refresh Stopped at time : 1.631600 ms : File "C:/Projects/soc-lm32-s3e/system_tb.v" Line 265 Stopped at line=265 file name=C:/Projects/soc-lm32-s3e/system_tb.v %