Design Name | top_level |
Device, Speed (SpeedFile Version) | XC9572, -15 (3.0) |
Date Created | Fri Sep 12 14:07:44 2008 |
Created By | Timing Report Generator: version J.40 |
Copyright | Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. |
Performance Summary | |
---|---|
Min. Clock Period | 62.500 ns. |
Max. Clock Frequency (fSYSTEM) | 16.000 MHz. |
Limited by Cycle Time for CLK | |
Clock to Setup (tCYC) | 62.500 ns. |
Pad to Pad Delay (tPD) | 16.000 ns. |
Setup to Clock at the Pad (tSU) | 29.000 ns. |
Clock Pad to Output Pad Delay (tCO) | 25.000 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS_CLK | 33.0 | 62.5 | 254 | 82 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
Data_OUT<0>.Q to Data_IN<7>.D | 33.000 | 62.500 | -29.500 |
Data_OUT<2>.Q to Data_IN<7>.D | 33.000 | 62.500 | -29.500 |
Data_OUT<1>.Q to Data_IN<7>.D | 33.000 | 61.500 | -28.500 |
Clock | fEXT (MHz) | Reason |
---|---|---|
CLK | 16.000 | Limited by Cycle Time for CLK |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
Data_IN<0> | 29.000 | 0.000 |
Data_IN<1> | 29.000 | 0.000 |
Data_IN<2> | 29.000 | 0.000 |
Data_IN<3> | 29.000 | 0.000 |
Data_IN<4> | 29.000 | 0.000 |
Data_IN<5> | 10.000 | 0.000 |
Data_IN<6> | 29.000 | 0.000 |
Data_IN<7> | 29.000 | 0.000 |
RXF | 29.000 | 0.000 |
TXE | 9.000 | 0.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
WR | 25.000 |
Data_IN<0> | 24.000 |
Data_IN<1> | 24.000 |
Data_IN<2> | 24.000 |
Data_IN<3> | 24.000 |
Data_IN<4> | 24.000 |
Data_IN<5> | 24.000 |
Data_IN<6> | 24.000 |
Data_IN<7> | 24.000 |
FQ_UD | 18.500 |
RESET | 17.500 |
Data_OUT<0> | 8.000 |
Data_OUT<1> | 8.000 |
Data_OUT<2> | 8.000 |
Data_OUT<3> | 8.000 |
Data_OUT<4> | 8.000 |
Data_OUT<5> | 8.000 |
Data_OUT<6> | 8.000 |
Data_OUT<7> | 8.000 |
RD | 8.000 |
W_CLK<0> | 8.000 |
W_CLK<1> | 8.000 |
W_CLK<2> | 8.000 |
W_CLK<3> | 8.000 |
Source | Destination | Delay |
---|---|---|
Data_OUT<0>.Q | Data_IN<7>.D | 62.500 |
Data_OUT<2>.Q | Data_IN<7>.D | 62.500 |
Data_OUT<1>.Q | Data_IN<7>.D | 61.500 |
Data_IN<0>.Q | Data_IN<7>.D | 57.000 |
Data_IN<1>.Q | Data_IN<7>.D | 57.000 |
Data_IN<2>.Q | Data_IN<7>.D | 57.000 |
Data_OUT<0>.Q | Data_IN<5>.D | 52.000 |
Data_OUT<0>.Q | Data_IN<6>.D | 52.000 |
Data_OUT<2>.Q | Data_IN<5>.D | 52.000 |
Data_OUT<2>.Q | Data_IN<6>.D | 52.000 |
Data_OUT<1>.Q | Data_IN<5>.D | 51.000 |
Data_OUT<1>.Q | Data_IN<6>.D | 51.000 |
Data_IN<0>.Q | Data_IN<5>.D | 46.500 |
Data_IN<0>.Q | Data_IN<6>.D | 46.500 |
Data_IN<1>.Q | Data_IN<5>.D | 46.500 |
Data_IN<1>.Q | Data_IN<6>.D | 46.500 |
Data_IN<2>.Q | Data_IN<5>.D | 46.500 |
Data_IN<2>.Q | Data_IN<6>.D | 46.500 |
Data_IN<3>.Q | Data_IN<7>.D | 46.500 |
Data_IN<4>.Q | Data_IN<7>.D | 46.500 |
Data_IN<5>.Q | Data_IN<7>.D | 46.500 |
DDS<0>.Q | Data_IN<5>.D | 39.000 |
DDS<1>.Q | Data_IN<5>.D | 39.000 |
DDS<2>.Q | Data_IN<5>.D | 39.000 |
Data_OUT<3>.Q | Data_IN<7>.D | 39.000 |
Data_OUT<4>.Q | Data_IN<7>.D | 39.000 |
Data_OUT<5>.Q | Data_IN<7>.D | 39.000 |
state_FFd1.Q | Data_IN<5>.D | 39.000 |
state_FFd2.Q | Data_IN<5>.D | 39.000 |
state_FFd3.Q | Data_IN<5>.D | 39.000 |
state_FFd4.Q | Data_IN<5>.D | 39.000 |
Data_OUT<6>.Q | Data_IN<5>.D | 37.000 |
DDS<0>.Q | Data_IN<1>.D | 36.000 |
DDS<0>.Q | Data_IN<2>.D | 36.000 |
DDS<0>.Q | Data_IN<3>.D | 36.000 |
DDS<0>.Q | Data_IN<4>.D | 36.000 |
DDS<1>.Q | Data_IN<1>.D | 36.000 |
DDS<1>.Q | Data_IN<2>.D | 36.000 |
DDS<1>.Q | Data_IN<3>.D | 36.000 |
DDS<1>.Q | Data_IN<4>.D | 36.000 |
DDS<2>.Q | Data_IN<1>.D | 36.000 |
DDS<2>.Q | Data_IN<2>.D | 36.000 |
DDS<2>.Q | Data_IN<3>.D | 36.000 |
DDS<2>.Q | Data_IN<4>.D | 36.000 |
Data_IN<3>.Q | Data_IN<5>.D | 36.000 |
Data_IN<3>.Q | Data_IN<6>.D | 36.000 |
Data_IN<4>.Q | Data_IN<5>.D | 36.000 |
Data_IN<4>.Q | Data_IN<6>.D | 36.000 |
Data_IN<5>.Q | Data_IN<6>.D | 36.000 |
state_FFd1.Q | Data_IN<1>.D | 36.000 |
state_FFd1.Q | Data_IN<2>.D | 36.000 |
state_FFd1.Q | Data_IN<3>.D | 36.000 |
state_FFd1.Q | Data_IN<4>.D | 36.000 |
state_FFd2.Q | Data_IN<1>.D | 36.000 |
state_FFd2.Q | Data_IN<2>.D | 36.000 |
state_FFd2.Q | Data_IN<3>.D | 36.000 |
state_FFd2.Q | Data_IN<4>.D | 36.000 |
state_FFd3.Q | Data_IN<1>.D | 36.000 |
state_FFd3.Q | Data_IN<2>.D | 36.000 |
state_FFd3.Q | Data_IN<3>.D | 36.000 |
state_FFd3.Q | Data_IN<4>.D | 36.000 |
state_FFd4.Q | Data_IN<1>.D | 36.000 |
state_FFd4.Q | Data_IN<2>.D | 36.000 |
state_FFd4.Q | Data_IN<3>.D | 36.000 |
state_FFd4.Q | Data_IN<4>.D | 36.000 |
DDS<0>.Q | Data_IN<0>.D | 35.000 |
DDS<1>.Q | Data_IN<0>.D | 35.000 |
DDS<2>.Q | Data_IN<0>.D | 35.000 |
Data_IN<0>.Q | Data_IN<4>.D | 35.000 |
Data_IN<1>.Q | Data_IN<4>.D | 35.000 |
Data_IN<2>.Q | Data_IN<4>.D | 35.000 |
Data_IN<3>.Q | Data_IN<4>.D | 35.000 |
state_FFd1.Q | Data_IN<0>.D | 35.000 |
state_FFd2.Q | Data_IN<0>.D | 35.000 |
state_FFd3.Q | Data_IN<0>.D | 35.000 |
state_FFd4.Q | Data_IN<0>.D | 35.000 |
Data_OUT<3>.Q | Data_IN<5>.D | 34.000 |
Data_OUT<4>.Q | Data_IN<5>.D | 34.000 |
Data_OUT<6>.Q | Data_IN<1>.D | 34.000 |
Data_OUT<6>.Q | Data_IN<2>.D | 34.000 |
Data_OUT<6>.Q | Data_IN<3>.D | 34.000 |
Data_OUT<6>.Q | Data_IN<4>.D | 34.000 |
Data_OUT<6>.Q | Data_IN<0>.D | 33.000 |
DDS<0>.Q | Data_IN<7>.D | 31.500 |
DDS<1>.Q | Data_IN<7>.D | 31.500 |
DDS<2>.Q | Data_IN<7>.D | 31.500 |
Data_OUT<5>.Q | Data_IN<5>.D | 31.500 |
Data_OUT<7>.Q | Data_IN<5>.D | 31.500 |
Data_OUT<7>.Q | Data_IN<7>.D | 29.500 |
state_FFd3.Q | Data_IN<7>.D | 29.500 |
state_FFd4.Q | Data_IN<7>.D | 29.500 |
Data_OUT<0>.Q | Data_IN<1>.D | 28.500 |
Data_OUT<0>.Q | Data_IN<2>.D | 28.500 |
Data_OUT<0>.Q | Data_IN<3>.D | 28.500 |
Data_OUT<0>.Q | Data_IN<4>.D | 28.500 |
Data_OUT<1>.Q | Data_IN<1>.D | 28.500 |
Data_OUT<1>.Q | Data_IN<2>.D | 28.500 |
Data_OUT<1>.Q | Data_IN<3>.D | 28.500 |
Data_OUT<1>.Q | Data_IN<4>.D | 28.500 |
Data_OUT<2>.Q | Data_IN<1>.D | 28.500 |
Data_OUT<2>.Q | Data_IN<2>.D | 28.500 |
Data_OUT<2>.Q | Data_IN<3>.D | 28.500 |
Data_OUT<2>.Q | Data_IN<4>.D | 28.500 |
Data_OUT<3>.Q | Data_IN<1>.D | 28.500 |
Data_OUT<3>.Q | Data_IN<2>.D | 28.500 |
Data_OUT<3>.Q | Data_IN<3>.D | 28.500 |
Data_OUT<3>.Q | Data_IN<4>.D | 28.500 |
Data_OUT<3>.Q | Data_IN<6>.D | 28.500 |
Data_OUT<4>.Q | Data_IN<1>.D | 28.500 |
Data_OUT<4>.Q | Data_IN<2>.D | 28.500 |
Data_OUT<4>.Q | Data_IN<3>.D | 28.500 |
Data_OUT<4>.Q | Data_IN<4>.D | 28.500 |
Data_OUT<4>.Q | Data_IN<6>.D | 28.500 |
Data_OUT<5>.Q | Data_IN<1>.D | 28.500 |
Data_OUT<5>.Q | Data_IN<2>.D | 28.500 |
Data_OUT<5>.Q | Data_IN<3>.D | 28.500 |
Data_OUT<5>.Q | Data_IN<4>.D | 28.500 |
Data_OUT<5>.Q | Data_IN<6>.D | 28.500 |
Data_OUT<7>.Q | Data_IN<1>.D | 28.500 |
Data_OUT<7>.Q | Data_IN<2>.D | 28.500 |
Data_OUT<7>.Q | Data_IN<3>.D | 28.500 |
Data_OUT<7>.Q | Data_IN<4>.D | 28.500 |
state_FFd1.Q | Data_IN<7>.D | 28.500 |
state_FFd2.Q | Data_IN<7>.D | 28.500 |
Data_OUT<0>.Q | Data_IN<0>.D | 27.500 |
Data_OUT<1>.Q | Data_IN<0>.D | 27.500 |
Data_OUT<2>.Q | Data_IN<0>.D | 27.500 |
Data_OUT<3>.Q | Data_IN<0>.D | 27.500 |
Data_OUT<4>.Q | Data_IN<0>.D | 27.500 |
Data_OUT<5>.Q | Data_IN<0>.D | 27.500 |
Data_OUT<7>.Q | Data_IN<0>.D | 27.500 |
Data_OUT<6>.Q | Data_IN<7>.D | 24.000 |
Data_IN<0>.Q | Data_IN<3>.D | 22.000 |
Data_IN<1>.Q | Data_IN<3>.D | 22.000 |
Data_IN<2>.Q | Data_IN<3>.D | 22.000 |
Data_IN<7>.Q | Data_IN<7>.D | 22.000 |
DDS<0>.Q | Data_IN<6>.D | 21.000 |
DDS<1>.Q | Data_IN<6>.D | 21.000 |
DDS<2>.Q | Data_IN<6>.D | 21.000 |
Data_IN<6>.Q | Data_IN<7>.D | 21.000 |
state_FFd1.Q | RD.D | 20.000 |
state_FFd3.Q | RD.D | 20.000 |
Data_OUT<7>.Q | Data_IN<6>.D | 19.000 |
state_FFd2.Q | RD.D | 19.000 |
state_FFd4.Q | Data_IN<6>.D | 19.000 |
state_FFd4.Q | RD.D | 19.000 |
state_FFd1.Q | Data_IN<6>.D | 18.000 |
state_FFd2.Q | Data_IN<6>.D | 18.000 |
state_FFd3.Q | Data_IN<6>.D | 18.000 |
Data_OUT<0>.Q | W_CLK<0>.D | 17.000 |
Data_OUT<0>.Q | W_CLK<1>.D | 17.000 |
Data_OUT<0>.Q | W_CLK<2>.D | 17.000 |
Data_OUT<0>.Q | W_CLK<3>.D | 17.000 |
Data_OUT<1>.Q | W_CLK<3>.D | 17.000 |
Data_OUT<2>.Q | W_CLK<0>.D | 17.000 |
Data_OUT<2>.Q | W_CLK<1>.D | 17.000 |
Data_OUT<2>.Q | W_CLK<2>.D | 17.000 |
Data_OUT<2>.Q | W_CLK<3>.D | 17.000 |
Data_OUT<3>.Q | W_CLK<0>.D | 17.000 |
Data_OUT<3>.Q | W_CLK<1>.D | 17.000 |
Data_OUT<3>.Q | W_CLK<2>.D | 17.000 |
Data_OUT<3>.Q | W_CLK<3>.D | 17.000 |
Data_OUT<4>.Q | W_CLK<3>.D | 17.000 |
Data_OUT<5>.Q | W_CLK<3>.D | 17.000 |
Data_OUT<6>.Q | W_CLK<3>.D | 17.000 |
Data_OUT<7>.Q | W_CLK<0>.D | 17.000 |
Data_OUT<7>.Q | W_CLK<1>.D | 17.000 |
Data_OUT<7>.Q | W_CLK<2>.D | 17.000 |
Data_OUT<7>.Q | W_CLK<3>.D | 17.000 |
Data_OUT<1>.Q | W_CLK<0>.D | 16.000 |
Data_OUT<1>.Q | W_CLK<1>.D | 16.000 |
Data_OUT<1>.Q | W_CLK<2>.D | 16.000 |
Data_OUT<4>.Q | W_CLK<0>.D | 16.000 |
Data_OUT<4>.Q | W_CLK<1>.D | 16.000 |
Data_OUT<4>.Q | W_CLK<2>.D | 16.000 |
Data_OUT<5>.Q | W_CLK<0>.D | 16.000 |
Data_OUT<5>.Q | W_CLK<1>.D | 16.000 |
Data_OUT<5>.Q | W_CLK<2>.D | 16.000 |
Data_OUT<6>.Q | W_CLK<0>.D | 16.000 |
Data_OUT<6>.Q | W_CLK<1>.D | 16.000 |
Data_OUT<6>.Q | W_CLK<2>.D | 16.000 |
RD.Q | Data_OUT<0>.D | 16.000 |
RD.Q | Data_OUT<1>.D | 16.000 |
RD.Q | Data_OUT<2>.D | 16.000 |
RD.Q | Data_OUT<3>.D | 16.000 |
RD.Q | Data_OUT<4>.D | 16.000 |
RD.Q | Data_OUT<5>.D | 16.000 |
RD.Q | Data_OUT<7>.D | 16.000 |
Data_IN<5>.Q | Data_IN<5>.D | 14.500 |
Data_OUT<6>.Q | Data_IN<6>.D | 13.500 |
Data_IN<3>.Q | Data_IN<3>.D | 12.500 |
DDS<0>.Q | W_CLK<0>.D | 11.500 |
DDS<0>.Q | W_CLK<1>.D | 11.500 |
DDS<0>.Q | W_CLK<2>.D | 11.500 |
DDS<0>.Q | W_CLK<3>.D | 11.500 |
DDS<0>.Q | state_FFd2.D | 11.500 |
DDS<1>.Q | W_CLK<0>.D | 11.500 |
DDS<1>.Q | W_CLK<1>.D | 11.500 |
DDS<1>.Q | W_CLK<2>.D | 11.500 |
DDS<1>.Q | W_CLK<3>.D | 11.500 |
DDS<1>.Q | state_FFd2.D | 11.500 |
DDS<2>.Q | W_CLK<0>.D | 11.500 |
DDS<2>.Q | W_CLK<1>.D | 11.500 |
DDS<2>.Q | W_CLK<2>.D | 11.500 |
DDS<2>.Q | W_CLK<3>.D | 11.500 |
DDS<2>.Q | state_FFd2.D | 11.500 |
Data_IN<0>.Q | Data_IN<1>.D | 11.500 |
Data_IN<0>.Q | Data_IN<2>.D | 11.500 |
Data_IN<1>.Q | Data_IN<2>.D | 11.500 |
Data_IN<4>.Q | Data_IN<4>.D | 11.500 |
state_FFd1.Q | W_CLK<0>.D | 11.500 |
state_FFd1.Q | W_CLK<1>.D | 11.500 |
state_FFd1.Q | W_CLK<2>.D | 11.500 |
state_FFd1.Q | state_FFd1.D | 11.500 |
state_FFd1.Q | state_FFd2.D | 11.500 |
state_FFd1.Q | state_FFd3.D | 11.500 |
state_FFd1.Q | state_FFd4.D | 11.500 |
state_FFd2.Q | W_CLK<0>.D | 11.500 |
state_FFd2.Q | W_CLK<1>.D | 11.500 |
state_FFd2.Q | W_CLK<2>.D | 11.500 |
state_FFd2.Q | state_FFd1.D | 11.500 |
state_FFd2.Q | state_FFd2.D | 11.500 |
state_FFd2.Q | state_FFd3.D | 11.500 |
state_FFd2.Q | state_FFd4.D | 11.500 |
state_FFd3.Q | W_CLK<0>.D | 11.500 |
state_FFd3.Q | W_CLK<1>.D | 11.500 |
state_FFd3.Q | W_CLK<2>.D | 11.500 |
state_FFd3.Q | state_FFd1.D | 11.500 |
state_FFd3.Q | state_FFd2.D | 11.500 |
state_FFd3.Q | state_FFd3.D | 11.500 |
state_FFd3.Q | state_FFd4.D | 11.500 |
state_FFd4.Q | W_CLK<0>.D | 11.500 |
state_FFd4.Q | W_CLK<1>.D | 11.500 |
state_FFd4.Q | W_CLK<2>.D | 11.500 |
state_FFd4.Q | state_FFd2.D | 11.500 |
state_FFd4.Q | state_FFd3.D | 11.500 |
DDS<0>.Q | DDS<0>.D | 10.500 |
DDS<1>.Q | DDS<1>.D | 10.500 |
DDS<2>.Q | DDS<2>.D | 10.500 |
Data_OUT<0>.Q | Data_OUT<0>.D | 10.500 |
Data_OUT<1>.Q | Data_OUT<1>.D | 10.500 |
Data_OUT<2>.Q | Data_OUT<2>.D | 10.500 |
Data_OUT<3>.Q | Data_OUT<3>.D | 10.500 |
Data_OUT<4>.Q | Data_OUT<4>.D | 10.500 |
Data_OUT<5>.Q | Data_OUT<5>.D | 10.500 |
Data_OUT<6>.Q | Data_OUT<6>.D | 10.500 |
Data_OUT<7>.Q | Data_OUT<7>.D | 10.500 |
RD.Q | Data_OUT<6>.D | 10.500 |
state_FFd1.Q | W_CLK<3>.D | 10.500 |
state_FFd2.Q | W_CLK<3>.D | 10.500 |
state_FFd3.Q | W_CLK<3>.D | 10.500 |
state_FFd4.Q | W_CLK<3>.D | 10.500 |
state_FFd4.Q | state_FFd1.D | 10.500 |
state_FFd4.Q | state_FFd4.D | 10.500 |
Source Pad | Destination Pad | Delay |
---|---|---|
CLK | CLK_DDS | 16.000 |
Data_IN<0> | FQ_UD | 16.000 |
Data_IN<1> | FQ_UD | 16.000 |
Data_IN<2> | FQ_UD | 16.000 |
Data_IN<3> | FQ_UD | 16.000 |
Data_IN<4> | FQ_UD | 16.000 |
Data_IN<5> | FQ_UD | 16.000 |
Data_IN<6> | FQ_UD | 16.000 |
Data_IN<7> | FQ_UD | 16.000 |
RXF | FQ_UD | 16.000 |
Data_IN<0> | RESET | 15.000 |
Data_IN<1> | RESET | 15.000 |
Data_IN<2> | RESET | 15.000 |
Data_IN<3> | RESET | 15.000 |
Data_IN<4> | RESET | 15.000 |
Data_IN<5> | RESET | 15.000 |
Data_IN<6> | RESET | 15.000 |
Data_IN<7> | RESET | 15.000 |
TXE | WR | 15.000 |