********** Mapped Logic ********** |
$OpTx$FX_DC$1328 <= (NOT DDS(0).LFBK AND NOT DDS(1).LFBK); |
$OpTx$FX_DC$1329.LFBK <= Data_OUT(7).PIN
XOR $OpTx$FX_DC$1329.LFBK <= checksum(7).LFBK; |
$OpTx$FX_DC$1331.LFBK <= ((EXP15_.EXP)
OR (NOT state_FFd2 AND NOT Data_OUT(7).PIN) OR (state_FFd1 AND NOT Data_OUT(7).PIN)); |
$OpTx$INV$13_0_ <= ((RXF)
OR (NOT state_FFd2) OR (state_FFd1) OR (state_FFd3) OR (DDS(0) AND DDS(1) AND Data_OUT_int(3).LFBK AND Data_OUT_int(4).LFBK AND Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK AND Data_OUT_int(5).LFBK AND Data_OUT_int(0).LFBK AND NOT Data_OUT_int(7).LFBK AND NOT Data_OUT(6).PIN)); |
$OpTx$INV$13_1_ <= ((state_FFd4)
OR (DDS(0) AND DDS(2)) OR (DDS(1) AND DDS(2)) OR (NOT DDS(0) AND NOT DDS(1) AND NOT DDS(2)) OR (NOT DDS(0) AND NOT DDS(2) AND Data_OUT_int(3).LFBK AND NOT Data_OUT_int(4).LFBK AND Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK AND Data_OUT_int(5).LFBK AND Data_OUT_int(0).LFBK AND NOT Data_OUT_int(7).LFBK AND NOT Data_OUT(6).PIN)); |
$OpTx$INV$13_2_ <= ((Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND
Data_IN(0).PIN AND Data_IN(7).PIN AND Data_IN(6).PIN AND Data_IN(4).PIN AND DDS(2)) OR (DDS(2) AND Data_OUT_int(3).LFBK AND NOT Data_OUT_int(4).LFBK AND Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK AND NOT Data_OUT_int(5).LFBK AND Data_OUT_int(0).LFBK AND NOT Data_OUT_int(7).LFBK AND Data_OUT(6).PIN) OR (NOT DDS(1) AND NOT DDS(2) AND Data_OUT_int(3).LFBK AND Data_OUT_int(4).LFBK AND Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK AND NOT Data_OUT_int(5).LFBK AND Data_OUT_int(0).LFBK AND NOT Data_OUT_int(7).LFBK AND NOT Data_OUT(6).PIN)); |
BUF_checksum(6)__$$INT.LFBK <= NOT (checksum(6).LFBK
XOR BUF_checksum(6)__$$INT.LFBK <= NOT (((NOT state_FFd2) OR (state_FFd1) OR (state_FFd3) OR (state_FFd4) OR (EXP16_.EXP) OR (Data_OUT_int(6).EXP))); |
CLK_DDS <= DDS(2).EXP; |
FTCPE_DDS0: FTCPE port map (DDS(0),DDS_T(0),NOT CLK,'0','0');
DDS_T(0) <= ((Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND Data_IN(4).PIN AND NOT DDS(0).LFBK) OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND Data_IN(7).PIN AND Data_IN(6).PIN AND NOT Data_IN(4).PIN AND Data_IN(5).PIN AND DDS(0).LFBK) OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND NOT Data_IN(7).PIN AND Data_IN(6).PIN AND NOT Data_IN(4).PIN AND NOT Data_IN(5).PIN AND DDS(0).LFBK) OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND NOT Data_IN(4).PIN AND Data_IN(5).PIN AND DDS(0).LFBK)); |
FTCPE_DDS1: FTCPE port map (DDS(1),DDS_T(1),NOT CLK,'0','0');
DDS_T(1) <= ((Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND Data_IN(5).PIN AND NOT DDS(1).LFBK) OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND Data_IN(7).PIN AND Data_IN(6).PIN AND NOT Data_IN(4).PIN AND Data_IN(5).PIN AND DDS(1).LFBK) OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND NOT Data_IN(7).PIN AND Data_IN(6).PIN AND NOT Data_IN(4).PIN AND NOT Data_IN(5).PIN AND DDS(1).LFBK) OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND Data_IN(4).PIN AND NOT Data_IN(5).PIN AND DDS(1).LFBK)); |
FTCPE_DDS2: FTCPE port map (DDS(2),DDS_T(2),NOT CLK,'0','0');
DDS_T(2) <= ((Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND Data_IN(4).PIN AND DDS(2).LFBK) OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND Data_IN(5).PIN AND DDS(2).LFBK) OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND Data_IN(7).PIN AND Data_IN(6).PIN AND NOT Data_IN(4).PIN AND Data_IN(5).PIN AND DDS(2).LFBK) OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND NOT Data_IN(7).PIN AND Data_IN(6).PIN AND NOT Data_IN(4).PIN AND NOT Data_IN(5).PIN AND NOT DDS(2).LFBK)); |
FTCPE_Data_IN0: FTCPE port map (Data_IN_I(0),Data_IN_T(0),NOT CLK,'0','0');
Data_IN_T(0) <= (NOT $OpTx$INV$13 AND Data_OUT(0).PIN); Data_IN(0) <= Data_IN_I(0) when Data_IN_OE(0) = '1' else 'Z'; Data_IN_OE(0) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4); |
FTCPE_Data_IN1: FTCPE port map (Data_IN_I(1),EXP11_.EXP,NOT CLK,'0','0');
Data_IN(1) <= Data_IN_I(1) when Data_IN_OE(1) = '1' else 'Z'; Data_IN_OE(1) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4); |
FTCPE_Data_IN2: FTCPE port map (Data_IN_I(2),Data_IN_T(2),NOT CLK,'0','0');
Data_IN_T(2) <= ((checksum(1).EXP) OR (NOT $OpTx$INV$13 AND checksum(1).LFBK AND Data_OUT(1).PIN AND NOT Data_OUT(2).PIN) OR (NOT $OpTx$INV$13 AND NOT checksum(1).LFBK AND NOT Data_OUT(1).PIN AND Data_OUT(2).PIN) OR (NOT $OpTx$INV$13 AND NOT checksum(0).LFBK AND NOT Data_OUT(1).PIN AND Data_OUT(2).PIN) OR (NOT $OpTx$INV$13 AND NOT Data_OUT(1).PIN AND Data_OUT(2).PIN AND NOT Data_OUT(0).PIN)); Data_IN(2) <= Data_IN_I(2) when Data_IN_OE(2) = '1' else 'Z'; Data_IN_OE(2) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4); |
FDCPE_Data_IN3: FDCPE port map (Data_IN_I(3),Data_IN(3),NOT CLK,'0','0');
Data_IN(3) <= ((EXP8_.EXP) OR (EXP9_.EXP) OR ($OpTx$INV$13 AND NOT checksum(3).LFBK) OR ( NOT Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2.LFBK AND NOT $OpTx$INV$13 AND checksum(3).LFBK AND Data_OUT(3).PIN) OR (NOT $OpTx$INV$13 AND checksum(2).LFBK AND checksum(3).LFBK AND Data_OUT(2).PIN AND NOT Data_OUT(3).PIN) OR (NOT $OpTx$INV$13 AND checksum(1).LFBK AND checksum(3).LFBK AND Data_OUT(1).PIN AND Data_OUT(2).PIN AND NOT Data_OUT(3).PIN)); Data_IN(3) <= Data_IN_I(3) when Data_IN_OE(3) = '1' else 'Z'; Data_IN_OE(3) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4); |
FTCPE_Data_IN4: FTCPE port map (Data_IN_I(4),Data_IN_T(4),NOT CLK,'0','0');
Data_IN_T(4) <= ((checksum(5).EXP) OR (NOT $OpTx$INV$13 AND Madd_checksum_add0000_CARRY_IN(4)/Madd_checksum_add0000_CARRY_IN(4)_D2 AND NOT checksum(4).LFBK AND NOT Data_OUT(4).PIN) OR (NOT $OpTx$INV$13 AND NOT Madd_checksum_add0000_CARRY_IN(4)/Madd_checksum_add0000_CARRY_IN(4)_D2 AND checksum(4).LFBK AND Data_OUT(4).PIN) OR ( Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2.LFBK AND NOT $OpTx$INV$13 AND checksum(3).LFBK AND checksum(4).LFBK AND NOT Data_OUT(4).PIN) OR (NOT $OpTx$INV$13 AND checksum(3).LFBK AND checksum(4).LFBK AND NOT Data_OUT(4).PIN AND Data_OUT(3).PIN)); Data_IN(4) <= Data_IN_I(4) when Data_IN_OE(4) = '1' else 'Z'; Data_IN_OE(4) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4); |
FTCPE_Data_IN5: FTCPE port map (Data_IN_I(5),EXP7_.EXP,NOT CLK,'0','0');
Data_IN(5) <= Data_IN_I(5) when Data_IN_OE(5) = '1' else 'Z'; Data_IN_OE(5) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4); |
FTCPE_Data_IN6: FTCPE port map (Data_IN_I(6),Data_IN_T(6),NOT CLK,'0','0');
Data_IN_T(6) <= ((NOT state_FFd2) OR (state_FFd1) OR (state_FFd3) OR (EXP21_.EXP)); Data_IN(6) <= Data_IN_I(6) when Data_IN_OE(6) = '1' else 'Z'; Data_IN_OE(6) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4); |
FDCPE_Data_IN7: FDCPE port map (Data_IN_I(7),Data_IN(7),NOT CLK,'0','0');
Data_IN(7) <= ((EXP19_.EXP) OR (EXP20_.EXP) OR (checksum(7).LFBK AND NOT state_FFd2) OR (checksum(7).LFBK AND state_FFd1) OR (checksum(7).LFBK AND state_FFd3) OR (checksum(7).LFBK AND state_FFd4)); Data_IN(7) <= Data_IN_I(7) when Data_IN_OE(7) = '1' else 'Z'; Data_IN_OE(7) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4); |
FDCPE_Data_OUT0: FDCPE port map (Data_OUT(0),Data_OUT_D(0),NOT CLK,'0','0');
Data_OUT_D(0) <= ((Data_IN(0).PIN AND NOT RD.PIN) OR (Data_OUT_int(0).LFBK AND RD.PIN)); |
FDCPE_Data_OUT1: FDCPE port map (Data_OUT(1),Data_OUT_D(1),NOT CLK,'0','0');
Data_OUT_D(1) <= ((Data_IN(1).PIN AND NOT RD.PIN) OR (Data_OUT_int(1).LFBK AND RD.PIN)); |
FDCPE_Data_OUT2: FDCPE port map (Data_OUT(2),Data_OUT_D(2),NOT CLK,'0','0');
Data_OUT_D(2) <= ((Data_IN(2).PIN AND NOT RD.PIN) OR (Data_OUT_int(2).LFBK AND RD.PIN)); |
FDCPE_Data_OUT3: FDCPE port map (Data_OUT(3),Data_OUT_D(3),NOT CLK,'0','0');
Data_OUT_D(3) <= ((Data_IN(3).PIN AND NOT RD.PIN) OR (Data_OUT_int(3).LFBK AND RD.PIN)); |
FDCPE_Data_OUT4: FDCPE port map (Data_OUT(4),Data_OUT_D(4),NOT CLK,'0','0');
Data_OUT_D(4) <= ((Data_IN(4).PIN AND NOT RD.PIN) OR (Data_OUT_int(4).LFBK AND RD.PIN)); |
FDCPE_Data_OUT5: FDCPE port map (Data_OUT(5),Data_OUT_D(5),NOT CLK,'0','0');
Data_OUT_D(5) <= ((Data_IN(5).PIN AND NOT RD.PIN) OR (Data_OUT_int(5).LFBK AND RD.PIN)); |
FDCPE_Data_OUT6: FDCPE port map (Data_OUT(6),Data_OUT_D(6),NOT CLK,'0','0');
Data_OUT_D(6) <= ((Data_IN(6).PIN AND NOT RD_int.LFBK) OR (RD_int.LFBK AND Data_OUT_int(6).LFBK)); |
FDCPE_Data_OUT7: FDCPE port map (Data_OUT(7),Data_OUT_D(7),NOT CLK,'0','0');
Data_OUT_D(7) <= ((Data_IN(7).PIN AND NOT RD.PIN) OR (Data_OUT_int(7).LFBK AND RD.PIN)); |
FQ_UD <= ((state_FFd2.EXP)
OR (NOT state_FFd2.LFBK AND NOT state_FFd1.LFBK AND state_FFd3.LFBK AND NOT state_FFd4.LFBK)); |
Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 <= ((
Madd_checksum_add0000_CARRY_IN(5)/Madd_checksum_add0000_CARRY_IN(5)_D2_1_.EXP) OR (EXP3_.EXP) OR (checksum(1).LFBK AND checksum(2).LFBK AND Data_OUT(1).PIN) OR (checksum(1).LFBK AND Data_OUT(1).PIN AND Data_OUT(2).PIN) OR (checksum(1).LFBK AND checksum(0).LFBK AND Data_OUT(2).PIN AND Data_OUT(0).PIN) OR (checksum(0).LFBK AND checksum(2).LFBK AND Data_OUT(1).PIN AND Data_OUT(0).PIN) OR (checksum(0).LFBK AND Data_OUT(1).PIN AND Data_OUT(2).PIN AND Data_OUT(0).PIN)); |
Madd_checksum_add0000_CARRY_IN(4)/Madd_checksum_add0000_CARRY_IN(4)_D2_2_ <= ((Data_IN(0) AND Data_IN(1) AND Data_OUT_int(3).LFBK AND
Data_OUT_int(2).LFBK AND Data_OUT_int(0).LFBK) OR (Data_IN(0) AND Data_IN(2) AND Data_IN(3) AND Data_OUT_int(1).LFBK AND Data_OUT_int(0).LFBK) OR (Data_IN(0) AND Data_IN(2) AND Data_OUT_int(3).LFBK AND Data_OUT_int(1).LFBK AND Data_OUT_int(0).LFBK) OR (Data_IN(0) AND Data_IN(3) AND Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK AND Data_OUT_int(0).LFBK) OR (Data_IN(0) AND Data_OUT_int(3).LFBK AND Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK AND Data_OUT_int(0).LFBK)); |
Madd_checksum_add0000_CARRY_IN(4)/Madd_checksum_add0000_CARRY_IN(4)_D2_1_ <= ((Data_IN(1) AND Data_IN(2) AND Data_OUT_int(3).LFBK AND
Data_OUT_int(1).LFBK) OR (Data_IN(1) AND Data_IN(3) AND Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK) OR (Data_IN(1) AND Data_OUT_int(3).LFBK AND Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK) OR (Data_IN(0) AND Data_IN(1) AND Data_IN(2) AND Data_OUT_int(3).LFBK AND Data_OUT_int(0).LFBK) OR (Data_IN(0) AND Data_IN(1) AND Data_IN(3) AND Data_OUT_int(2).LFBK AND Data_OUT_int(0).LFBK)); |
Madd_checksum_add0000_CARRY_IN(4)/Madd_checksum_add0000_CARRY_IN(4)_D2_0_ <= ((Data_IN(3) AND Data_OUT_int(3).LFBK)
OR (Data_IN(2) AND Data_IN(3) AND Data_OUT_int(2).LFBK) OR (Data_IN(2) AND Data_OUT_int(3).LFBK AND Data_OUT_int(2).LFBK) OR (Data_IN(1) AND Data_IN(2) AND Data_IN(3) AND Data_OUT_int(1).LFBK) OR (Data_IN(0) AND Data_IN(1) AND Data_IN(2) AND Data_IN(3) AND Data_OUT_int(0).LFBK)); |
Madd_checksum_add0000_CARRY_IN(5)/Madd_checksum_add0000_CARRY_IN(5)_D2_0_ <= ((Data_IN(4) AND Data_OUT_int(4).LFBK)
OR (Data_IN(3) AND Data_IN(4) AND Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2) OR (Data_IN(3) AND Data_IN(4) AND Data_OUT_int(3).LFBK) OR (Data_IN(3) AND Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(4).LFBK) OR (Data_IN(3) AND Data_OUT_int(3).LFBK AND Data_OUT_int(4).LFBK)); |
Madd_checksum_add0000_CARRY_IN(5)/Madd_checksum_add0000_CARRY_IN(5)_D2_1_ <= ((
Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2.LFBK AND checksum(4).LFBK AND Data_OUT(3).PIN) OR ( Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2.LFBK AND Data_OUT(4).PIN AND Data_OUT(3).PIN)); |
Madd_checksum_add0000_CARRY_IN(6)/Madd_checksum_add0000_CARRY_IN(6)_D2_0_ <= ((Data_IN(5) AND Data_OUT_int(5).LFBK)
OR (Data_IN(4) AND Data_IN(5) AND Data_OUT_int(4).LFBK) OR (Data_IN(4) AND Data_OUT_int(4).LFBK AND Data_OUT_int(5).LFBK) OR (Data_IN(3) AND Data_IN(4) AND Data_IN(5) AND Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2) OR (Data_IN(3) AND Data_IN(4) AND Data_IN(5) AND Data_OUT_int(3).LFBK)); |
Madd_checksum_add0000_CARRY_IN(6)/Madd_checksum_add0000_CARRY_IN(6)_D2_1_ <= ((Data_IN(3) AND Data_IN(4) AND
Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(5).LFBK) OR (Data_IN(3) AND Data_IN(4) AND Data_OUT_int(3).LFBK AND Data_OUT_int(5).LFBK) OR (Data_IN(3) AND Data_IN(5) AND Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(4).LFBK) OR (Data_IN(3) AND Data_IN(5) AND Data_OUT_int(3).LFBK AND Data_OUT_int(4).LFBK) OR (Data_IN(3) AND Data_OUT_int(3).LFBK AND Data_OUT_int(4).LFBK AND Data_OUT_int(5).LFBK)); |
Madd_checksum_add0000_CARRY_IN(6)/Madd_checksum_add0000_CARRY_IN(6)_D2_2_ <= ((Data_IN(3) AND
Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(4).LFBK AND Data_OUT_int(5).LFBK) OR (Data_IN(4) AND Data_IN(5) AND Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(3).LFBK) OR (Data_IN(4) AND Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(3).LFBK AND Data_OUT_int(5).LFBK) OR (Data_IN(5) AND Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(3).LFBK AND Data_OUT_int(4).LFBK) OR ( Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(3).LFBK AND Data_OUT_int(4).LFBK AND Data_OUT_int(5).LFBK)); |
FDCPE_RD: FDCPE port map (RD,RD_D,CLK,'0',RXF);
RD_D <= ((EXP13_.EXP) OR (state_FFd2 AND NOT state_FFd3 AND NOT state_FFd4) OR (NOT state_FFd1 AND NOT state_FFd3 AND NOT state_FFd4)); |
RESET <= ((state_FFd2.LFBK AND state_FFd1.LFBK)
OR (state_FFd2.LFBK AND state_FFd3.LFBK AND NOT state_FFd4.LFBK) OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND NOT Data_IN(4).PIN AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND state_FFd4.LFBK AND NOT Data_IN(5).PIN)); |
WR <= ((NOT state_FFd2 AND state_FFd1 AND state_FFd3 AND
state_FFd4) OR (NOT state_FFd2 AND state_FFd1 AND state_FFd3 AND NOT TXE)); |
FDCPE_W_CLK0: FDCPE port map (W_CLK(0),W_CLK_D(0),NOT CLK,RXF,'0');
W_CLK_D(0) <= ((EXP1_.EXP) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND NOT DDS(1).LFBK AND NOT DDS(2).LFBK AND Data_OUT(5).PIN) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND NOT DDS(1).LFBK AND NOT DDS(2).LFBK AND NOT Data_OUT(4).PIN) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND NOT DDS(1).LFBK AND NOT DDS(2).LFBK AND Data_OUT(6).PIN) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND NOT DDS(1).LFBK AND NOT DDS(2).LFBK AND NOT Data_OUT(1).PIN)); |
FDCPE_W_CLK1: FDCPE port map (W_CLK(1),W_CLK_D(1),NOT CLK,RXF,'0');
W_CLK_D(1) <= ((EXP2_.EXP) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND NOT DDS(0).LFBK AND DDS(1).LFBK AND NOT DDS(2).LFBK AND NOT Data_OUT(5).PIN) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND NOT DDS(0).LFBK AND DDS(1).LFBK AND NOT DDS(2).LFBK AND Data_OUT(4).PIN) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND NOT DDS(0).LFBK AND DDS(1).LFBK AND NOT DDS(2).LFBK AND Data_OUT(6).PIN) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND NOT DDS(0).LFBK AND DDS(1).LFBK AND NOT DDS(2).LFBK AND NOT Data_OUT(1).PIN)); |
FDCPE_W_CLK2: FDCPE port map (W_CLK(2),W_CLK_D(2),NOT CLK,RXF,'0');
W_CLK_D(2) <= (($OpTx$FX_DC$1328.EXP) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND DDS(1).LFBK AND NOT DDS(2).LFBK AND NOT Data_OUT(5).PIN) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND DDS(1).LFBK AND NOT DDS(2).LFBK AND NOT Data_OUT(4).PIN) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND DDS(1).LFBK AND NOT DDS(2).LFBK AND Data_OUT(6).PIN) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND DDS(1).LFBK AND NOT DDS(2).LFBK AND NOT Data_OUT(1).PIN)); |
FDCPE_W_CLK3: FDCPE port map (W_CLK(3),W_CLK_D(3),NOT CLK,RXF,'0');
W_CLK_D(3) <= ((NOT state_FFd2.LFBK) OR (state_FFd1.LFBK) OR (state_FFd3.LFBK) OR (state_FFd4.LFBK) OR (CLK_DDS_OBUF$BUF0.EXP)); |
FDCPE_state_FFd1: FDCPE port map (state_FFd1,state_FFd1_D,CLK,RXF,'0');
state_FFd1_D <= ((DDS(0).EXP) OR (state_FFd1.LFBK AND state_FFd4.LFBK) OR (state_FFd2.LFBK AND state_FFd1.LFBK AND NOT state_FFd3.LFBK) OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND state_FFd3.LFBK)); |
FTCPE_state_FFd2: FTCPE port map (state_FFd2,state_FFd2_T,CLK,RXF,'0');
state_FFd2_T <= ((EXP0_.EXP) OR (NOT state_FFd1.LFBK AND state_FFd3.LFBK AND state_FFd4.LFBK) OR (state_FFd2.LFBK AND state_FFd1.LFBK AND state_FFd3.LFBK AND NOT state_FFd4.LFBK) OR (state_FFd1.LFBK AND state_FFd3.LFBK AND NOT state_FFd4.LFBK AND TXE)); |
FDCPE_state_FFd3: FDCPE port map (state_FFd3,state_FFd3_D,CLK,RXF,'0');
state_FFd3_D <= ((state_FFd1.EXP) OR (RESET_OBUF.EXP) OR (state_FFd2.LFBK AND state_FFd1.LFBK AND state_FFd4.LFBK) OR (state_FFd2.LFBK AND state_FFd3.LFBK AND state_FFd4.LFBK) OR (NOT state_FFd2.LFBK AND state_FFd1.LFBK AND state_FFd3.LFBK AND NOT state_FFd4.LFBK) OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND Data_IN(0).PIN AND Data_IN(7).PIN AND Data_IN(6).PIN AND state_FFd2.LFBK AND state_FFd4.LFBK AND Data_IN(5).PIN)); |
FDCPE_state_FFd4: FDCPE port map (state_FFd4,state_FFd4_D,CLK,RXF,'0');
state_FFd4_D <= ((FQ_UD_OBUF.EXP) OR (state_FFd2.LFBK AND state_FFd1.LFBK AND NOT state_FFd3.LFBK) OR (NOT state_FFd2.LFBK AND state_FFd1.LFBK AND state_FFd3.LFBK) OR (NOT state_FFd2.LFBK AND state_FFd3.LFBK AND state_FFd4.LFBK) OR (NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK)); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); |