cpldfit:  version J.40                              Xilinx Inc.
                                  Fitter Report
Design Name: top_level                           Date:  9-12-2008,  2:07PM
Device Used: XC9572-15-PC44
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
48 /72  ( 67%) 307 /360  ( 85%) 110/144 ( 76%)   28 /72  ( 39%) 28 /34  ( 82%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1          17/18       32/36       32          62/90       7/ 9
FB2          15/18       26/36       26          87/90       7/ 9
FB3           8/18       19/36       27          68/90       6/ 8
FB4           8/18       33/36       36          90/90*      5/ 8
             -----       -----                   -----       -----     
             48/72      110/144                 307/360     25/34 

* - Resource is exhausted

** Global Control Resources **

Signal 'CLK' mapped onto global clock net GCK1.
The complement of 'CLK' mapped onto global clock net GCK3.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :    2           2    |  I/O              :    24      28
Output        :    8           8    |  GCK/IO           :     3       3
Bidirectional :   17          17    |  GTS/IO           :     0       2
GCK           :    1           1    |  GSR/IO           :     1       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     28          28

** Power Data **

There are 48 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
**************************  Errors and Warnings  ***************************

WARNING:Cpld:125 - Signal
   Madd_checksum_add0000_CARRY_IN<5>/Madd_checksum_add0000_CARRY_IN<5>_D2 has
   been split into multiple macrocells to improve timing.
WARNING:Cpld:125 - Signal
   Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2 has
   been split into multiple macrocells to improve timing.
WARNING:Cpld:125 - Signal
   Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2 has
   been split into multiple macrocells to improve timing.
WARNING:Cpld:125 - Signal $OpTx$INV$13 has been split into multiple macrocells
   to improve timing.
*************************  Summary of Mapped Logic  ************************

** 25 Outputs **

Signal                                                                     Total Total Loc     Pin  Pin     Pin     Pwr  Slew Reg Init
Name                                                                       Pts   Inps          No.  Type    Use     Mode Rate State
Data_OUT<7>                                                                2     3     FB1_2   1    I/O     I/O     STD  FAST RESET
Data_OUT<5>                                                                2     3     FB1_6   3    I/O     I/O     STD  FAST RESET
Data_OUT<4>                                                                2     3     FB1_8   4    I/O     I/O     STD  FAST RESET
Data_OUT<3>                                                                2     3     FB1_11  6    GCK/I/O I/O     STD  FAST RESET
Data_OUT<2>                                                                2     3     FB1_14  7    GCK/I/O I/O     STD  FAST RESET
Data_OUT<1>                                                                2     3     FB1_15  8    I/O     I/O     STD  FAST RESET
Data_OUT<0>                                                                2     3     FB1_17  9    I/O     I/O     STD  FAST RESET
W_CLK<0>                                                                   9     16    FB2_2   35   I/O     O       STD  FAST RESET
W_CLK<1>                                                                   9     16    FB2_5   36   I/O     O       STD  FAST RESET
W_CLK<2>                                                                   9     16    FB2_6   37   I/O     O       STD  FAST RESET
W_CLK<3>                                                                   10    23    FB2_8   38   I/O     O       STD  FAST RESET
CLK_DDS                                                                    1     1     FB2_9   39   GSR/I/O O       STD  FAST 
RESET                                                                      3     12    FB2_15  43   I/O     O       STD  FAST 
FQ_UD                                                                      2     13    FB2_17  44   I/O     O       STD  FAST 
Data_IN<5>                                                                 17    17    FB3_8   13   I/O     I/O     STD  SLOW RESET
Data_IN<4>                                                                 9     16    FB3_9   14   I/O     I/O     STD  SLOW RESET
Data_IN<3>                                                                 18    16    FB3_11  18   I/O     I/O     STD  SLOW RESET
Data_IN<2>                                                                 9     12    FB3_14  19   I/O     I/O     STD  SLOW RESET
Data_IN<1>                                                                 4     10    FB3_15  20   I/O     I/O     STD  SLOW RESET
Data_IN<0>                                                                 2     8     FB3_17  22   I/O     I/O     STD  SLOW RESET
RD                                                                         11    14    FB4_2   24   I/O     I/O     STD  FAST RESET
WR                                                                         2     5     FB4_5   25   I/O     O       STD  FAST 
Data_OUT<6>                                                                2     3     FB4_11  28   I/O     I/O     STD  FAST RESET
Data_IN<7>                                                                 26    33    FB4_15  33   I/O     I/O     STD  SLOW RESET
Data_IN<6>                                                                 16    27    FB4_17  34   I/O     I/O     STD  SLOW RESET

** 23 Buried Nodes **

Signal                                                                     Total Total Loc     Pwr  Reg Init
Name                                                                       Pts   Inps          Mode State
$OpTx$INV$13_2_                                                            3     17    FB1_3   STD  
Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_2_  5     7     FB1_4   STD  
Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_1_  5     7     FB1_5   STD  
Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_0_  5     7     FB1_7   STD  
Madd_checksum_add0000_CARRY_IN<5>/Madd_checksum_add0000_CARRY_IN<5>_D2_0_  5     5     FB1_9   STD  
Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_2_  5     8     FB1_10  STD  
Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_1_  5     8     FB1_12  STD  
Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_0_  5     8     FB1_13  STD  
$OpTx$INV$13_1_                                                            5     12    FB1_16  STD  
$OpTx$INV$13_0_                                                            5     14    FB1_18  STD  
$OpTx$FX_DC$1328                                                           1     2     FB2_7   STD  
DDS<2>                                                                     4     9     FB2_10  STD  RESET
DDS<1>                                                                     4     9     FB2_11  STD  RESET
DDS<0>                                                                     4     9     FB2_12  STD  RESET
state_FFd1                                                                 5     6     FB2_13  STD  RESET
state_FFd3                                                                 8     13    FB2_14  STD  RESET
state_FFd4                                                                 9     13    FB2_16  STD  RESET
state_FFd2                                                                 9     17    FB2_18  STD  RESET
Madd_checksum_add0000_CARRY_IN<5>/Madd_checksum_add0000_CARRY_IN<5>_D2_1_  2     4     FB3_1   STD  
Madd_checksum_add0000_CARRY_IN<3>/Madd_checksum_add0000_CARRY_IN<3>_D2     7     6     FB3_2   STD  
$OpTx$FX_DC$1329                                                           2     2     FB4_4   STD  
$OpTx$FX_DC$1331                                                           15    24    FB4_8   STD  
BUF_checksum<6>__$$INT                                                     16    28    FB4_10  STD  

** 3 Inputs **

Signal                                                                     Loc     Pin  Pin     Pin     
Name                                                                               No.  Type    Use     
CLK                                                                        FB1_9   5    GCK/I/O GCK/I
TXE                                                                        FB4_8   26   I/O     I
RXF                                                                        FB4_9   27   I/O     I

Legend:
Pin No. - ~ - User Assigned
**************************  Function Block Details  ************************
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@)         - Signal used as input (wire-AND input) to the macrocell logic.
               The number of Signals Used may exceed the number of FB Inputs
               Used due to wire-ANDing in the switch matrix.
Pin No.      - ~  - User Assigned
*********************************** FB1  ***********************************
Number of function block inputs used/remaining:               32/4
Number of signals used by logic mapping into function block:  32
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0     0   5     FB1_1         (b)     
Data_OUT<7>           2       0     0   3     FB1_2   1     I/O     I/O
$OpTx$INV$13_2_       3       0     0   2     FB1_3         (b)     (b)
Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_2_
                      5       0     0   0     FB1_4         (b)     (b)
Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_1_
                      5       0     0   0     FB1_5   2     I/O     (b)
Data_OUT<5>           2       0     0   3     FB1_6   3     I/O     I/O
Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_0_
                      5       0     0   0     FB1_7         (b)     (b)
Data_OUT<4>           2       0     0   3     FB1_8   4     I/O     I/O
Madd_checksum_add0000_CARRY_IN<5>/Madd_checksum_add0000_CARRY_IN<5>_D2_0_
                      5       0     0   0     FB1_9   5     GCK/I/O GCK/I
Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_2_
                      5       0     0   0     FB1_10        (b)     (b)
Data_OUT<3>           2       0     0   3     FB1_11  6     GCK/I/O I/O
Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_1_
                      5       0     0   0     FB1_12        (b)     (b)
Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_0_
                      5       0     0   0     FB1_13        (b)     (b)
Data_OUT<2>           2       0     0   3     FB1_14  7     GCK/I/O I/O
Data_OUT<1>           2       0     0   3     FB1_15  8     I/O     I/O
$OpTx$INV$13_1_       5       0     0   0     FB1_16        (b)     (b)
Data_OUT<0>           2       0     0   3     FB1_17  9     I/O     I/O
$OpTx$INV$13_0_       5       0     0   0     FB1_18        (b)     (b)

Signals Used by Logic in Function Block
  1: DDS<0>                12: Data_OUT_int<1>.LFBK                                                    23: Data_IN<2>.PIN 
  2: DDS<1>                13: Data_OUT_int<2>.LFBK                                                    24: Data_IN<3>.PIN 
  3: DDS<2>                14: Data_OUT_int<3>.LFBK                                                    25: Data_IN<4>.PIN 
  4: Data_IN<0>            15: Data_OUT_int<4>.LFBK                                                    26: Data_IN<5>.PIN 
  5: Data_IN<1>            16: Data_OUT_int<5>.LFBK                                                    27: Data_IN<6>.PIN 
  6: Data_IN<2>            17: Data_OUT_int<7>.LFBK                                                    28: Data_IN<7>.PIN 
  7: Data_IN<3>            18: Madd_checksum_add0000_CARRY_IN<3>/Madd_checksum_add0000_CARRY_IN<3>_D2  29: state_FFd1 
  8: Data_IN<4>            19: RD.PIN                                                                  30: state_FFd2 
  9: Data_IN<5>            20: RXF                                                                     31: state_FFd3 
 10: Data_OUT<6>.PIN       21: Data_IN<0>.PIN                                                          32: state_FFd4 
 11: Data_OUT_int<0>.LFBK  22: Data_IN<1>.PIN                                                         

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
Data_OUT<7>          ................X.X........X............ 3       3
$OpTx$INV$13_2_      .XX......XXXXXXXX...XXXXX.XX............ 17      17
Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_2_ 
                     ......XXX....XXX.X...................... 7       7
Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_1_ 
                     ......XXX....XXX.X...................... 7       7
Data_OUT<5>          ...............X..X......X.............. 3       3
Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_0_ 
                     ......XXX....XXX.X...................... 7       7
Data_OUT<4>          ..............X...X.....X............... 3       3
Madd_checksum_add0000_CARRY_IN<5>/Madd_checksum_add0000_CARRY_IN<5>_D2_0_ 
                     ......XX.....XX..X...................... 5       5
Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_2_ 
                     ...XXXX...XXXX.......................... 8       8
Data_OUT<3>          .............X....X....X................ 3       3
Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_1_ 
                     ...XXXX...XXXX.......................... 8       8
Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_0_ 
                     ...XXXX...XXXX.......................... 8       8
Data_OUT<2>          ............X.....X...X................. 3       3
Data_OUT<1>          ...........X......X..X.................. 3       3
$OpTx$INV$13_1_      XXX......XXXXXXXX..............X........ 12      12
Data_OUT<0>          ..........X.......X.X................... 3       3
$OpTx$INV$13_0_      XX.......XXXXXXXX..X........XXX......... 14      14
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB2  ***********************************
Number of function block inputs used/remaining:               26/10
Number of signals used by logic mapping into function block:  26
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\5   0     FB2_1         (b)     (b)
W_CLK<0>              9       4<-   0   0     FB2_2   35    I/O     O
(unused)              0       0   /\4   1     FB2_3         (b)     (b)
(unused)              0       0   \/4   1     FB2_4         (b)     (b)
W_CLK<1>              9       4<-   0   0     FB2_5   36    I/O     O
W_CLK<2>              9       4<-   0   0     FB2_6   37    I/O     O
$OpTx$FX_DC$1328      1       0   /\4   0     FB2_7         (b)     (b)
W_CLK<3>             10       5<-   0   0     FB2_8   38    I/O     O
CLK_DDS               1       1<- /\5   0     FB2_9   39    GSR/I/O O
DDS<2>                4       0   /\1   0     FB2_10        (b)     (b)
DDS<1>                4       0     0   1     FB2_11  40    GTS/I/O (b)
DDS<0>                4       0   \/1   0     FB2_12        (b)     (b)
state_FFd1            5       1<- \/1   0     FB2_13        (b)     (b)
state_FFd3            8       3<-   0   0     FB2_14  42    GTS/I/O (b)
RESET                 3       0   /\2   0     FB2_15  43    I/O     O
state_FFd4            9       4<-   0   0     FB2_16        (b)     (b)
FQ_UD                 2       1<- /\4   0     FB2_17  44    I/O     O
state_FFd2            9       5<- /\1   0     FB2_18        (b)     (b)

Signals Used by Logic in Function Block
  1: CLK               10: Data_OUT<5>.PIN   19: Data_IN<4>.PIN 
  2: DDS<0>.LFBK       11: Data_OUT<6>.PIN   20: Data_IN<5>.PIN 
  3: DDS<1>.LFBK       12: Data_OUT<7>.PIN   21: Data_IN<6>.PIN 
  4: DDS<2>.LFBK       13: RXF               22: Data_IN<7>.PIN 
  5: Data_OUT<0>.PIN   14: TXE               23: state_FFd1.LFBK 
  6: Data_OUT<1>.PIN   15: Data_IN<0>.PIN    24: state_FFd2.LFBK 
  7: Data_OUT<2>.PIN   16: Data_IN<1>.PIN    25: state_FFd3.LFBK 
  8: Data_OUT<3>.PIN   17: Data_IN<2>.PIN    26: state_FFd4.LFBK 
  9: Data_OUT<4>.PIN   18: Data_IN<3>.PIN   

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
W_CLK<0>             .XXXXXXXXXXXX.........XXXX.............. 16      16
W_CLK<1>             .XXXXXXXXXXXX.........XXXX.............. 16      16
W_CLK<2>             .XXXXXXXXXXXX.........XXXX.............. 16      16
$OpTx$FX_DC$1328     .XX..................................... 2       2
W_CLK<3>             .XXXXXXXXXXXX.XXXXX.XXXXXX.............. 23      23
CLK_DDS              X....................................... 1       1
DDS<2>               ...X..........XXXXXXXX.................. 9       9
DDS<1>               ..X...........XXXXXXXX.................. 9       9
DDS<0>               .X............XXXXXXXX.................. 9       9
state_FFd1           ............XX........XXXX.............. 6       6
state_FFd3           ............X.XXXXXXXXXXXX.............. 13      13
RESET                ..............XXXXXXXXXXXX.............. 12      12
state_FFd4           ............X.XXXXXXXXXXXX.............. 13      13
FQ_UD                ............X.XXXXXXXXXXXX.............. 13      13
state_FFd2           .XXX........XXXXXXXXXXXXXX.............. 17      17
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB3  ***********************************
Number of function block inputs used/remaining:               19/17
Number of signals used by logic mapping into function block:  27
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
Madd_checksum_add0000_CARRY_IN<5>/Madd_checksum_add0000_CARRY_IN<5>_D2_1_
                      2       0   \/1   2     FB3_1         (b)     (b)
Madd_checksum_add0000_CARRY_IN<3>/Madd_checksum_add0000_CARRY_IN<3>_D2
                      7       2<-   0   0     FB3_2   11    I/O     (b)
(unused)              0       0   /\1   4     FB3_3         (b)     (b)
(unused)              0       0   \/1   4     FB3_4         (b)     (b)
(unused)              0       0   \/5   0     FB3_5   12    I/O     (b)
(unused)              0       0   \/5   0     FB3_6         (b)     (b)
(unused)              0       0   \/5   0     FB3_7         (b)     (b)
Data_IN<5>           17      16<- \/4   0     FB3_8   13    I/O     I/O
Data_IN<4>            9       4<-   0   0     FB3_9   14    I/O     I/O
(unused)              0       0   \/5   0     FB3_10        (b)     (b)
Data_IN<3>           18      13<-   0   0     FB3_11  18    I/O     I/O
(unused)              0       0   /\5   0     FB3_12        (b)     (b)
(unused)              0       0   /\3   2     FB3_13        (b)     (b)
Data_IN<2>            9       4<-   0   0     FB3_14  19    I/O     I/O
Data_IN<1>            4       3<- /\4   0     FB3_15  20    I/O     I/O
(unused)              0       0   /\3   2     FB3_16        (b)     (b)
Data_IN<0>            2       0     0   3     FB3_17  22    I/O     I/O
(unused)              0       0     0   5     FB3_18        (b)     

Signals Used by Logic in Function Block
  1: $OpTx$INV$13      10: Data_OUT<5>.PIN                                                              19: checksum<0>.LFBK 
  2: $OpTx$INV$13_0_   11: Madd_checksum_add0000_CARRY_IN<3>/Madd_checksum_add0000_CARRY_IN<3>_D2.LFBK  20: checksum<1>.LFBK 
  3: $OpTx$INV$13_1_   12: Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2       21: checksum<2>.LFBK 
  4: $OpTx$INV$13_2_   13: Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_0_    22: checksum<3>.LFBK 
  5: Data_OUT<0>.PIN   14: Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_1_    23: checksum<4>.LFBK 
  6: Data_OUT<1>.PIN   15: Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_2_    24: checksum<5>.LFBK 
  7: Data_OUT<2>.PIN   16: Madd_checksum_add0000_CARRY_IN<5>/Madd_checksum_add0000_CARRY_IN<5>_D2       25: state_FFd1 
  8: Data_OUT<3>.PIN   17: Madd_checksum_add0000_CARRY_IN<5>/Madd_checksum_add0000_CARRY_IN<5>_D2_0_    26: state_FFd2 
  9: Data_OUT<4>.PIN   18: Madd_checksum_add0000_CARRY_IN<5>/Madd_checksum_add0000_CARRY_IN<5>_D2_1_    27: state_FFd4 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
Madd_checksum_add0000_CARRY_IN<5>/Madd_checksum_add0000_CARRY_IN<5>_D2_1_ 
                     .......XX.X...........X................. 4       4
Madd_checksum_add0000_CARRY_IN<3>/Madd_checksum_add0000_CARRY_IN<3>_D2 
                     ....XXX...........XXX................... 6       6
Data_IN<5>           X@@@...XXXX....XXX...XXXXXX............. 17      14
Data_IN<4>           X@@@...XX.XX@@@......XX.XXX............. 16      10
Data_IN<3>           X@@@XXXX..X.......XXXX..XXX............. 16      13
Data_IN<2>           X@@@XXX...........XX....XXX............. 12      9
Data_IN<1>           X@@@XX............X.....XXX............. 10      7
Data_IN<0>           X@@@X...................XXX............. 8       5
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*********************************** FB4  ***********************************
Number of function block inputs used/remaining:               33/3
Number of signals used by logic mapping into function block:  36
Signal              Total   Imp   Exp Unused  Loc     Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt               #    Type    Use
(unused)              0       0   /\5   0     FB4_1         (b)     (b)
RD                   11       8<- /\2   0     FB4_2   24    I/O     I/O
(unused)              0       0   /\5   0     FB4_3         (b)     (b)
$OpTx$FX_DC$1329      2       0   /\3   0     FB4_4         (b)     (b)
WR                    2       0   \/3   0     FB4_5   25    I/O     O
(unused)              0       0   \/5   0     FB4_6         (b)     (b)
(unused)              0       0   \/5   0     FB4_7         (b)     (b)
$OpTx$FX_DC$1331     15      13<- \/3   0     FB4_8   26    I/O     I
(unused)              0       0   \/5   0     FB4_9   27    I/O     I
BUF_checksum<6>__$$INT
                     16      11<-   0   0     FB4_10        (b)     (b)
Data_OUT<6>           2       0   /\3   0     FB4_11  28    I/O     I/O
(unused)              0       0   \/5   0     FB4_12        (b)     (b)
(unused)              0       0   \/5   0     FB4_13        (b)     (b)
(unused)              0       0   \/5   0     FB4_14  29    I/O     (b)
Data_IN<7>           26      21<-   0   0     FB4_15  33    I/O     I/O
(unused)              0       0   /\5   0     FB4_16        (b)     (b)
Data_IN<6>           16      12<- /\1   0     FB4_17  34    I/O     I/O
(unused)              0       0   /\5   0     FB4_18        (b)     (b)

Signals Used by Logic in Function Block
  1: $OpTx$FX_DC$1328             13: Data_OUT<5>.PIN                                                            25: Data_IN<0>.PIN 
  2: $OpTx$FX_DC$1329.LFBK        14: Data_OUT<7>.PIN                                                            26: Data_IN<1>.PIN 
  3: $OpTx$FX_DC$1331.LFBK        15: Data_OUT_int<6>.LFBK                                                       27: Data_IN<2>.PIN 
  4: BUF_checksum<6>__$$INT.LFBK  16: Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2     28: Data_IN<3>.PIN 
  5: DDS<0>                       17: Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_0_  29: Data_IN<4>.PIN 
  6: DDS<1>                       18: Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_1_  30: Data_IN<5>.PIN 
  7: DDS<2>                       19: Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_2_  31: Data_IN<6>.PIN 
  8: Data_OUT<0>.PIN              20: RD_int.LFBK                                                                32: Data_IN<7>.PIN 
  9: Data_OUT<1>.PIN              21: RXF                                                                        33: state_FFd1 
 10: Data_OUT<2>.PIN              22: TXE                                                                        34: state_FFd2 
 11: Data_OUT<3>.PIN              23: checksum<6>.LFBK                                                           35: state_FFd3 
 12: Data_OUT<4>.PIN              24: checksum<7>.LFBK                                                           36: state_FFd4 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
RD                   ....................XX..XXXXXXXXXXXX.... 14      14
$OpTx$FX_DC$1329     .............X.........X................ 2       2
WR                   .....................X..........XXXX.... 5       5
$OpTx$FX_DC$1331     ....XXXXXXXXXXX.....X..XXXXXX.XXXXXX.... 24      24
BUF_checksum<6>__$$INT 
                     ....XXXXXXXXXXXXXXX.X.X.XXXXX.XXXXXX.... 28      28
Data_OUT<6>          ..............X....X..........X......... 3       3
Data_IN<7>           XXXXXXXXXXXXXXXXXXX.X.XXXXXXX.XXXXXX.... 33      33
Data_IN<6>           ....XXXXXXXXXXXXXXX.X...XXXXX.XXXXXX.... 27      27
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
*******************************  Equations  ********************************

********** Mapped Logic **********


$OpTx$FX_DC$1328 <= (NOT DDS(0).LFBK AND NOT DDS(1).LFBK);


$OpTx$FX_DC$1329.LFBK <= Data_OUT(7).PIN
	 XOR 
$OpTx$FX_DC$1329.LFBK <= checksum(7).LFBK;


$OpTx$FX_DC$1331.LFBK <= ((EXP15_.EXP)
	OR (NOT state_FFd2 AND NOT Data_OUT(7).PIN)
	OR (state_FFd1 AND NOT Data_OUT(7).PIN));


$OpTx$INV$13_0_ <= ((RXF)
	OR (NOT state_FFd2)
	OR (state_FFd1)
	OR (state_FFd3)
	OR (DDS(0) AND DDS(1) AND Data_OUT_int(3).LFBK AND 
	Data_OUT_int(4).LFBK AND Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK AND 
	Data_OUT_int(5).LFBK AND Data_OUT_int(0).LFBK AND NOT Data_OUT_int(7).LFBK AND 
	NOT Data_OUT(6).PIN));


$OpTx$INV$13_1_ <= ((state_FFd4)
	OR (DDS(0) AND DDS(2))
	OR (DDS(1) AND DDS(2))
	OR (NOT DDS(0) AND NOT DDS(1) AND NOT DDS(2))
	OR (NOT DDS(0) AND NOT DDS(2) AND Data_OUT_int(3).LFBK AND 
	NOT Data_OUT_int(4).LFBK AND Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK AND 
	Data_OUT_int(5).LFBK AND Data_OUT_int(0).LFBK AND NOT Data_OUT_int(7).LFBK AND 
	NOT Data_OUT(6).PIN));


$OpTx$INV$13_2_ <= ((Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND Data_IN(7).PIN AND Data_IN(6).PIN AND Data_IN(4).PIN AND 
	DDS(2))
	OR (DDS(2) AND Data_OUT_int(3).LFBK AND 
	NOT Data_OUT_int(4).LFBK AND Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK AND 
	NOT Data_OUT_int(5).LFBK AND Data_OUT_int(0).LFBK AND NOT Data_OUT_int(7).LFBK AND 
	Data_OUT(6).PIN)
	OR (NOT DDS(1) AND NOT DDS(2) AND Data_OUT_int(3).LFBK AND 
	Data_OUT_int(4).LFBK AND Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK AND 
	NOT Data_OUT_int(5).LFBK AND Data_OUT_int(0).LFBK AND NOT Data_OUT_int(7).LFBK AND 
	NOT Data_OUT(6).PIN));


BUF_checksum(6)__$$INT.LFBK <= NOT (checksum(6).LFBK
	 XOR 
BUF_checksum(6)__$$INT.LFBK <= NOT (((NOT state_FFd2)
	OR (state_FFd1)
	OR (state_FFd3)
	OR (state_FFd4)
	OR (EXP16_.EXP)
	OR (Data_OUT_int(6).EXP)));


CLK_DDS <= DDS(2).EXP;

FTCPE_DDS0: FTCPE port map (DDS(0),DDS_T(0),NOT CLK,'0','0');
DDS_T(0) <= ((Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND Data_IN(4).PIN AND 
	NOT DDS(0).LFBK)
	OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND Data_IN(7).PIN AND Data_IN(6).PIN AND NOT Data_IN(4).PIN AND 
	Data_IN(5).PIN AND DDS(0).LFBK)
	OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND NOT Data_IN(7).PIN AND Data_IN(6).PIN AND NOT Data_IN(4).PIN AND 
	NOT Data_IN(5).PIN AND DDS(0).LFBK)
	OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND NOT Data_IN(4).PIN AND 
	Data_IN(5).PIN AND DDS(0).LFBK));

FTCPE_DDS1: FTCPE port map (DDS(1),DDS_T(1),NOT CLK,'0','0');
DDS_T(1) <= ((Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND Data_IN(5).PIN AND 
	NOT DDS(1).LFBK)
	OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND Data_IN(7).PIN AND Data_IN(6).PIN AND NOT Data_IN(4).PIN AND 
	Data_IN(5).PIN AND DDS(1).LFBK)
	OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND NOT Data_IN(7).PIN AND Data_IN(6).PIN AND NOT Data_IN(4).PIN AND 
	NOT Data_IN(5).PIN AND DDS(1).LFBK)
	OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND Data_IN(4).PIN AND 
	NOT Data_IN(5).PIN AND DDS(1).LFBK));

FTCPE_DDS2: FTCPE port map (DDS(2),DDS_T(2),NOT CLK,'0','0');
DDS_T(2) <= ((Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND Data_IN(4).PIN AND 
	DDS(2).LFBK)
	OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND Data_IN(5).PIN AND 
	DDS(2).LFBK)
	OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND Data_IN(7).PIN AND Data_IN(6).PIN AND NOT Data_IN(4).PIN AND 
	Data_IN(5).PIN AND DDS(2).LFBK)
	OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND NOT Data_IN(7).PIN AND Data_IN(6).PIN AND NOT Data_IN(4).PIN AND 
	NOT Data_IN(5).PIN AND NOT DDS(2).LFBK));

FTCPE_Data_IN0: FTCPE port map (Data_IN_I(0),Data_IN_T(0),NOT CLK,'0','0');
Data_IN_T(0) <= (NOT $OpTx$INV$13 AND Data_OUT(0).PIN);
Data_IN(0) <= Data_IN_I(0) when Data_IN_OE(0) = '1' else 'Z';
Data_IN_OE(0) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4);

FTCPE_Data_IN1: FTCPE port map (Data_IN_I(1),EXP11_.EXP,NOT CLK,'0','0');
Data_IN(1) <= Data_IN_I(1) when Data_IN_OE(1) = '1' else 'Z';
Data_IN_OE(1) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4);

FTCPE_Data_IN2: FTCPE port map (Data_IN_I(2),Data_IN_T(2),NOT CLK,'0','0');
Data_IN_T(2) <= ((checksum(1).EXP)
	OR (NOT $OpTx$INV$13 AND checksum(1).LFBK AND 
	Data_OUT(1).PIN AND NOT Data_OUT(2).PIN)
	OR (NOT $OpTx$INV$13 AND NOT checksum(1).LFBK AND 
	NOT Data_OUT(1).PIN AND Data_OUT(2).PIN)
	OR (NOT $OpTx$INV$13 AND NOT checksum(0).LFBK AND 
	NOT Data_OUT(1).PIN AND Data_OUT(2).PIN)
	OR (NOT $OpTx$INV$13 AND NOT Data_OUT(1).PIN AND Data_OUT(2).PIN AND 
	NOT Data_OUT(0).PIN));
Data_IN(2) <= Data_IN_I(2) when Data_IN_OE(2) = '1' else 'Z';
Data_IN_OE(2) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4);

FDCPE_Data_IN3: FDCPE port map (Data_IN_I(3),Data_IN(3),NOT CLK,'0','0');
Data_IN(3) <= ((EXP8_.EXP)
	OR (EXP9_.EXP)
	OR ($OpTx$INV$13 AND NOT checksum(3).LFBK)
	OR (
	NOT Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2.LFBK AND NOT $OpTx$INV$13 AND checksum(3).LFBK AND 
	Data_OUT(3).PIN)
	OR (NOT $OpTx$INV$13 AND checksum(2).LFBK AND 
	checksum(3).LFBK AND Data_OUT(2).PIN AND NOT Data_OUT(3).PIN)
	OR (NOT $OpTx$INV$13 AND checksum(1).LFBK AND 
	checksum(3).LFBK AND Data_OUT(1).PIN AND Data_OUT(2).PIN AND 
	NOT Data_OUT(3).PIN));
Data_IN(3) <= Data_IN_I(3) when Data_IN_OE(3) = '1' else 'Z';
Data_IN_OE(3) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4);

FTCPE_Data_IN4: FTCPE port map (Data_IN_I(4),Data_IN_T(4),NOT CLK,'0','0');
Data_IN_T(4) <= ((checksum(5).EXP)
	OR (NOT $OpTx$INV$13 AND 
	Madd_checksum_add0000_CARRY_IN(4)/Madd_checksum_add0000_CARRY_IN(4)_D2 AND NOT checksum(4).LFBK AND NOT Data_OUT(4).PIN)
	OR (NOT $OpTx$INV$13 AND 
	NOT Madd_checksum_add0000_CARRY_IN(4)/Madd_checksum_add0000_CARRY_IN(4)_D2 AND checksum(4).LFBK AND Data_OUT(4).PIN)
	OR (
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2.LFBK AND NOT $OpTx$INV$13 AND checksum(3).LFBK AND 
	checksum(4).LFBK AND NOT Data_OUT(4).PIN)
	OR (NOT $OpTx$INV$13 AND checksum(3).LFBK AND 
	checksum(4).LFBK AND NOT Data_OUT(4).PIN AND Data_OUT(3).PIN));
Data_IN(4) <= Data_IN_I(4) when Data_IN_OE(4) = '1' else 'Z';
Data_IN_OE(4) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4);

FTCPE_Data_IN5: FTCPE port map (Data_IN_I(5),EXP7_.EXP,NOT CLK,'0','0');
Data_IN(5) <= Data_IN_I(5) when Data_IN_OE(5) = '1' else 'Z';
Data_IN_OE(5) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4);

FTCPE_Data_IN6: FTCPE port map (Data_IN_I(6),Data_IN_T(6),NOT CLK,'0','0');
Data_IN_T(6) <= ((NOT state_FFd2)
	OR (state_FFd1)
	OR (state_FFd3)
	OR (EXP21_.EXP));
Data_IN(6) <= Data_IN_I(6) when Data_IN_OE(6) = '1' else 'Z';
Data_IN_OE(6) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4);

FDCPE_Data_IN7: FDCPE port map (Data_IN_I(7),Data_IN(7),NOT CLK,'0','0');
Data_IN(7) <= ((EXP19_.EXP)
	OR (EXP20_.EXP)
	OR (checksum(7).LFBK AND NOT state_FFd2)
	OR (checksum(7).LFBK AND state_FFd1)
	OR (checksum(7).LFBK AND state_FFd3)
	OR (checksum(7).LFBK AND state_FFd4));
Data_IN(7) <= Data_IN_I(7) when Data_IN_OE(7) = '1' else 'Z';
Data_IN_OE(7) <= (NOT state_FFd2 AND state_FFd1 AND state_FFd4);

FDCPE_Data_OUT0: FDCPE port map (Data_OUT(0),Data_OUT_D(0),NOT CLK,'0','0');
Data_OUT_D(0) <= ((Data_IN(0).PIN AND NOT RD.PIN)
	OR (Data_OUT_int(0).LFBK AND RD.PIN));

FDCPE_Data_OUT1: FDCPE port map (Data_OUT(1),Data_OUT_D(1),NOT CLK,'0','0');
Data_OUT_D(1) <= ((Data_IN(1).PIN AND NOT RD.PIN)
	OR (Data_OUT_int(1).LFBK AND RD.PIN));

FDCPE_Data_OUT2: FDCPE port map (Data_OUT(2),Data_OUT_D(2),NOT CLK,'0','0');
Data_OUT_D(2) <= ((Data_IN(2).PIN AND NOT RD.PIN)
	OR (Data_OUT_int(2).LFBK AND RD.PIN));

FDCPE_Data_OUT3: FDCPE port map (Data_OUT(3),Data_OUT_D(3),NOT CLK,'0','0');
Data_OUT_D(3) <= ((Data_IN(3).PIN AND NOT RD.PIN)
	OR (Data_OUT_int(3).LFBK AND RD.PIN));

FDCPE_Data_OUT4: FDCPE port map (Data_OUT(4),Data_OUT_D(4),NOT CLK,'0','0');
Data_OUT_D(4) <= ((Data_IN(4).PIN AND NOT RD.PIN)
	OR (Data_OUT_int(4).LFBK AND RD.PIN));

FDCPE_Data_OUT5: FDCPE port map (Data_OUT(5),Data_OUT_D(5),NOT CLK,'0','0');
Data_OUT_D(5) <= ((Data_IN(5).PIN AND NOT RD.PIN)
	OR (Data_OUT_int(5).LFBK AND RD.PIN));

FDCPE_Data_OUT6: FDCPE port map (Data_OUT(6),Data_OUT_D(6),NOT CLK,'0','0');
Data_OUT_D(6) <= ((Data_IN(6).PIN AND NOT RD_int.LFBK)
	OR (RD_int.LFBK AND Data_OUT_int(6).LFBK));

FDCPE_Data_OUT7: FDCPE port map (Data_OUT(7),Data_OUT_D(7),NOT CLK,'0','0');
Data_OUT_D(7) <= ((Data_IN(7).PIN AND NOT RD.PIN)
	OR (Data_OUT_int(7).LFBK AND RD.PIN));














































FQ_UD <= ((state_FFd2.EXP)
	OR (NOT state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	state_FFd3.LFBK AND NOT state_FFd4.LFBK));


Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 <= ((
	Madd_checksum_add0000_CARRY_IN(5)/Madd_checksum_add0000_CARRY_IN(5)_D2_1_.EXP)
	OR (EXP3_.EXP)
	OR (checksum(1).LFBK AND checksum(2).LFBK AND 
	Data_OUT(1).PIN)
	OR (checksum(1).LFBK AND Data_OUT(1).PIN AND 
	Data_OUT(2).PIN)
	OR (checksum(1).LFBK AND checksum(0).LFBK AND 
	Data_OUT(2).PIN AND Data_OUT(0).PIN)
	OR (checksum(0).LFBK AND checksum(2).LFBK AND 
	Data_OUT(1).PIN AND Data_OUT(0).PIN)
	OR (checksum(0).LFBK AND Data_OUT(1).PIN AND 
	Data_OUT(2).PIN AND Data_OUT(0).PIN));


Madd_checksum_add0000_CARRY_IN(4)/Madd_checksum_add0000_CARRY_IN(4)_D2_2_ <= ((Data_IN(0) AND Data_IN(1) AND Data_OUT_int(3).LFBK AND 
	Data_OUT_int(2).LFBK AND Data_OUT_int(0).LFBK)
	OR (Data_IN(0) AND Data_IN(2) AND Data_IN(3) AND 
	Data_OUT_int(1).LFBK AND Data_OUT_int(0).LFBK)
	OR (Data_IN(0) AND Data_IN(2) AND Data_OUT_int(3).LFBK AND 
	Data_OUT_int(1).LFBK AND Data_OUT_int(0).LFBK)
	OR (Data_IN(0) AND Data_IN(3) AND Data_OUT_int(1).LFBK AND 
	Data_OUT_int(2).LFBK AND Data_OUT_int(0).LFBK)
	OR (Data_IN(0) AND Data_OUT_int(3).LFBK AND 
	Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK AND Data_OUT_int(0).LFBK));


Madd_checksum_add0000_CARRY_IN(4)/Madd_checksum_add0000_CARRY_IN(4)_D2_1_ <= ((Data_IN(1) AND Data_IN(2) AND Data_OUT_int(3).LFBK AND 
	Data_OUT_int(1).LFBK)
	OR (Data_IN(1) AND Data_IN(3) AND Data_OUT_int(1).LFBK AND 
	Data_OUT_int(2).LFBK)
	OR (Data_IN(1) AND Data_OUT_int(3).LFBK AND 
	Data_OUT_int(1).LFBK AND Data_OUT_int(2).LFBK)
	OR (Data_IN(0) AND Data_IN(1) AND Data_IN(2) AND 
	Data_OUT_int(3).LFBK AND Data_OUT_int(0).LFBK)
	OR (Data_IN(0) AND Data_IN(1) AND Data_IN(3) AND 
	Data_OUT_int(2).LFBK AND Data_OUT_int(0).LFBK));


Madd_checksum_add0000_CARRY_IN(4)/Madd_checksum_add0000_CARRY_IN(4)_D2_0_ <= ((Data_IN(3) AND Data_OUT_int(3).LFBK)
	OR (Data_IN(2) AND Data_IN(3) AND Data_OUT_int(2).LFBK)
	OR (Data_IN(2) AND Data_OUT_int(3).LFBK AND 
	Data_OUT_int(2).LFBK)
	OR (Data_IN(1) AND Data_IN(2) AND Data_IN(3) AND 
	Data_OUT_int(1).LFBK)
	OR (Data_IN(0) AND Data_IN(1) AND Data_IN(2) AND 
	Data_IN(3) AND Data_OUT_int(0).LFBK));


Madd_checksum_add0000_CARRY_IN(5)/Madd_checksum_add0000_CARRY_IN(5)_D2_0_ <= ((Data_IN(4) AND Data_OUT_int(4).LFBK)
	OR (Data_IN(3) AND Data_IN(4) AND 
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2)
	OR (Data_IN(3) AND Data_IN(4) AND Data_OUT_int(3).LFBK)
	OR (Data_IN(3) AND 
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(4).LFBK)
	OR (Data_IN(3) AND Data_OUT_int(3).LFBK AND 
	Data_OUT_int(4).LFBK));


Madd_checksum_add0000_CARRY_IN(5)/Madd_checksum_add0000_CARRY_IN(5)_D2_1_ <= ((
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2.LFBK AND checksum(4).LFBK AND Data_OUT(3).PIN)
	OR (
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2.LFBK AND Data_OUT(4).PIN AND Data_OUT(3).PIN));


Madd_checksum_add0000_CARRY_IN(6)/Madd_checksum_add0000_CARRY_IN(6)_D2_0_ <= ((Data_IN(5) AND Data_OUT_int(5).LFBK)
	OR (Data_IN(4) AND Data_IN(5) AND Data_OUT_int(4).LFBK)
	OR (Data_IN(4) AND Data_OUT_int(4).LFBK AND 
	Data_OUT_int(5).LFBK)
	OR (Data_IN(3) AND Data_IN(4) AND Data_IN(5) AND 
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2)
	OR (Data_IN(3) AND Data_IN(4) AND Data_IN(5) AND 
	Data_OUT_int(3).LFBK));


Madd_checksum_add0000_CARRY_IN(6)/Madd_checksum_add0000_CARRY_IN(6)_D2_1_ <= ((Data_IN(3) AND Data_IN(4) AND 
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(5).LFBK)
	OR (Data_IN(3) AND Data_IN(4) AND Data_OUT_int(3).LFBK AND 
	Data_OUT_int(5).LFBK)
	OR (Data_IN(3) AND Data_IN(5) AND 
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(4).LFBK)
	OR (Data_IN(3) AND Data_IN(5) AND Data_OUT_int(3).LFBK AND 
	Data_OUT_int(4).LFBK)
	OR (Data_IN(3) AND Data_OUT_int(3).LFBK AND 
	Data_OUT_int(4).LFBK AND Data_OUT_int(5).LFBK));


Madd_checksum_add0000_CARRY_IN(6)/Madd_checksum_add0000_CARRY_IN(6)_D2_2_ <= ((Data_IN(3) AND 
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(4).LFBK AND Data_OUT_int(5).LFBK)
	OR (Data_IN(4) AND Data_IN(5) AND 
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(3).LFBK)
	OR (Data_IN(4) AND 
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(3).LFBK AND Data_OUT_int(5).LFBK)
	OR (Data_IN(5) AND 
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(3).LFBK AND Data_OUT_int(4).LFBK)
	OR (
	Madd_checksum_add0000_CARRY_IN(3)/Madd_checksum_add0000_CARRY_IN(3)_D2 AND Data_OUT_int(3).LFBK AND Data_OUT_int(4).LFBK AND 
	Data_OUT_int(5).LFBK));

FDCPE_RD: FDCPE port map (RD,RD_D,CLK,'0',RXF);
RD_D <= ((EXP13_.EXP)
	OR (state_FFd2 AND NOT state_FFd3 AND NOT state_FFd4)
	OR (NOT state_FFd1 AND NOT state_FFd3 AND NOT state_FFd4));


RESET <= ((state_FFd2.LFBK AND state_FFd1.LFBK)
	OR (state_FFd2.LFBK AND state_FFd3.LFBK AND 
	NOT state_FFd4.LFBK)
	OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND NOT Data_IN(7).PIN AND NOT Data_IN(6).PIN AND NOT Data_IN(4).PIN AND 
	NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND state_FFd4.LFBK AND 
	NOT Data_IN(5).PIN));


WR <= ((NOT state_FFd2 AND state_FFd1 AND state_FFd3 AND 
	state_FFd4)
	OR (NOT state_FFd2 AND state_FFd1 AND state_FFd3 AND NOT TXE));

FDCPE_W_CLK0: FDCPE port map (W_CLK(0),W_CLK_D(0),NOT CLK,RXF,'0');
W_CLK_D(0) <= ((EXP1_.EXP)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND NOT DDS(1).LFBK AND 
	NOT DDS(2).LFBK AND Data_OUT(5).PIN)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND NOT DDS(1).LFBK AND 
	NOT DDS(2).LFBK AND NOT Data_OUT(4).PIN)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND NOT DDS(1).LFBK AND 
	NOT DDS(2).LFBK AND Data_OUT(6).PIN)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND NOT DDS(1).LFBK AND 
	NOT DDS(2).LFBK AND NOT Data_OUT(1).PIN));

FDCPE_W_CLK1: FDCPE port map (W_CLK(1),W_CLK_D(1),NOT CLK,RXF,'0');
W_CLK_D(1) <= ((EXP2_.EXP)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND NOT DDS(0).LFBK AND DDS(1).LFBK AND 
	NOT DDS(2).LFBK AND NOT Data_OUT(5).PIN)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND NOT DDS(0).LFBK AND DDS(1).LFBK AND 
	NOT DDS(2).LFBK AND Data_OUT(4).PIN)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND NOT DDS(0).LFBK AND DDS(1).LFBK AND 
	NOT DDS(2).LFBK AND Data_OUT(6).PIN)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND NOT DDS(0).LFBK AND DDS(1).LFBK AND 
	NOT DDS(2).LFBK AND NOT Data_OUT(1).PIN));

FDCPE_W_CLK2: FDCPE port map (W_CLK(2),W_CLK_D(2),NOT CLK,RXF,'0');
W_CLK_D(2) <= (($OpTx$FX_DC$1328.EXP)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND DDS(1).LFBK AND 
	NOT DDS(2).LFBK AND NOT Data_OUT(5).PIN)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND DDS(1).LFBK AND 
	NOT DDS(2).LFBK AND NOT Data_OUT(4).PIN)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND DDS(1).LFBK AND 
	NOT DDS(2).LFBK AND Data_OUT(6).PIN)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK AND NOT state_FFd4.LFBK AND DDS(0).LFBK AND DDS(1).LFBK AND 
	NOT DDS(2).LFBK AND NOT Data_OUT(1).PIN));

FDCPE_W_CLK3: FDCPE port map (W_CLK(3),W_CLK_D(3),NOT CLK,RXF,'0');
W_CLK_D(3) <= ((NOT state_FFd2.LFBK)
	OR (state_FFd1.LFBK)
	OR (state_FFd3.LFBK)
	OR (state_FFd4.LFBK)
	OR (CLK_DDS_OBUF$BUF0.EXP));

FDCPE_state_FFd1: FDCPE port map (state_FFd1,state_FFd1_D,CLK,RXF,'0');
state_FFd1_D <= ((DDS(0).EXP)
	OR (state_FFd1.LFBK AND state_FFd4.LFBK)
	OR (state_FFd2.LFBK AND state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK)
	OR (state_FFd2.LFBK AND NOT state_FFd1.LFBK AND 
	state_FFd3.LFBK));

FTCPE_state_FFd2: FTCPE port map (state_FFd2,state_FFd2_T,CLK,RXF,'0');
state_FFd2_T <= ((EXP0_.EXP)
	OR (NOT state_FFd1.LFBK AND state_FFd3.LFBK AND 
	state_FFd4.LFBK)
	OR (state_FFd2.LFBK AND state_FFd1.LFBK AND 
	state_FFd3.LFBK AND NOT state_FFd4.LFBK)
	OR (state_FFd1.LFBK AND state_FFd3.LFBK AND 
	NOT state_FFd4.LFBK AND TXE));

FDCPE_state_FFd3: FDCPE port map (state_FFd3,state_FFd3_D,CLK,RXF,'0');
state_FFd3_D <= ((state_FFd1.EXP)
	OR (RESET_OBUF.EXP)
	OR (state_FFd2.LFBK AND state_FFd1.LFBK AND 
	state_FFd4.LFBK)
	OR (state_FFd2.LFBK AND state_FFd3.LFBK AND 
	state_FFd4.LFBK)
	OR (NOT state_FFd2.LFBK AND state_FFd1.LFBK AND 
	state_FFd3.LFBK AND NOT state_FFd4.LFBK)
	OR (Data_IN(3).PIN AND Data_IN(2).PIN AND Data_IN(1).PIN AND 
	Data_IN(0).PIN AND Data_IN(7).PIN AND Data_IN(6).PIN AND 
	state_FFd2.LFBK AND state_FFd4.LFBK AND Data_IN(5).PIN));

FDCPE_state_FFd4: FDCPE port map (state_FFd4,state_FFd4_D,CLK,RXF,'0');
state_FFd4_D <= ((FQ_UD_OBUF.EXP)
	OR (state_FFd2.LFBK AND state_FFd1.LFBK AND 
	NOT state_FFd3.LFBK)
	OR (NOT state_FFd2.LFBK AND state_FFd1.LFBK AND 
	state_FFd3.LFBK)
	OR (NOT state_FFd2.LFBK AND state_FFd3.LFBK AND 
	state_FFd4.LFBK)
	OR (NOT state_FFd1.LFBK AND NOT state_FFd3.LFBK AND 
	NOT state_FFd4.LFBK));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC9572-15-PC44


   --------------------------------  
  /6  5  4  3  2  1  44 43 42 41 40 \
 | 7                             39 | 
 | 8                             38 | 
 | 9                             37 | 
 | 10                            36 | 
 | 11        XC9572-15-PC44      35 | 
 | 12                            34 | 
 | 13                            33 | 
 | 14                            32 | 
 | 15                            31 | 
 | 16                            30 | 
 | 17                            29 | 
 \ 18 19 20 21 22 23 24 25 26 27 28 /
   --------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 Data_OUT<7>                      23 GND                           
  2 TIE                              24 RD                            
  3 Data_OUT<5>                      25 WR                            
  4 Data_OUT<4>                      26 TXE                           
  5 CLK                              27 RXF                           
  6 Data_OUT<3>                      28 Data_OUT<6>                   
  7 Data_OUT<2>                      29 TIE                           
  8 Data_OUT<1>                      30 TDO                           
  9 Data_OUT<0>                      31 GND                           
 10 GND                              32 VCC                           
 11 TIE                              33 Data_IN<7>                    
 12 TIE                              34 Data_IN<6>                    
 13 Data_IN<5>                       35 W_CLK<0>                      
 14 Data_IN<4>                       36 W_CLK<1>                      
 15 TDI                              37 W_CLK<2>                      
 16 TMS                              38 W_CLK<3>                      
 17 TCK                              39 CLK_DDS                       
 18 Data_IN<3>                       40 TIE                           
 19 Data_IN<2>                       41 VCC                           
 20 Data_IN<1>                       42 TIE                           
 21 VCC                              43 RESET                         
 22 Data_IN<0>                       44 FQ_UD                         


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9572-15-PC44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25