Design Name | top_level |
Fitting Status | Successful |
Software Version | J.40 |
Device Used | XC9572-15-PC44 |
Date | 9-12-2008, 2:07PM |
Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
---|---|---|---|---|
48/72 (67%) | 307/360 (86%) | 28/72 (39%) | 28/34 (83%) | 110/144 (77%) |
|
|
Signal mapped onto global clock net (GCK1) | CLK |
Signal mapped onto global clock net (GCK3) | /CLK |
Macrocells in high performance mode (MCHP) | 48 |
Macrocells in low power mode (MCLP) | 0 |
Total macrocells used (MC) | 48 |