Logic

Signal Name Total Pterms Total Inputs Function Block Macrocell Power Mode Slew Rate Pin Number Pin Type Pin Use Reg Init State
Data_OUT<7> 2 3 FB1 MC2 STD FAST 1 I/O I/O RESET
Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_1_ 5 7 FB1 MC5 STD   2 I/O (b)  
Data_OUT<5> 2 3 FB1 MC6 STD FAST 3 I/O I/O RESET
Data_OUT<4> 2 3 FB1 MC8 STD FAST 4 I/O I/O RESET
Madd_checksum_add0000_CARRY_IN<5>/Madd_checksum_add0000_CARRY_IN<5>_D2_0_ 5 5 FB1 MC9 STD   5 I/O/GCK1 GCK/I  
Data_OUT<3> 2 3 FB1 MC11 STD FAST 6 I/O/GCK2 I/O RESET
Data_OUT<2> 2 3 FB1 MC14 STD FAST 7 I/O/GCK3 I/O RESET
Data_OUT<1> 2 3 FB1 MC15 STD FAST 8 I/O I/O RESET
Data_OUT<0> 2 3 FB1 MC17 STD FAST 9 I/O I/O RESET
Madd_checksum_add0000_CARRY_IN<3>/Madd_checksum_add0000_CARRY_IN<3>_D2 7 6 FB3 MC2 STD   11 I/O (b)  
Data_IN<5> 17 17 FB3 MC8 STD SLOW 13 I/O I/O RESET
Data_IN<4> 9 16 FB3 MC9 STD SLOW 14 I/O I/O RESET
Data_IN<3> 18 16 FB3 MC11 STD SLOW 18 I/O I/O RESET
Data_IN<2> 9 12 FB3 MC14 STD SLOW 19 I/O I/O RESET
Data_IN<1> 4 10 FB3 MC15 STD SLOW 20 I/O I/O RESET
Data_IN<0> 2 8 FB3 MC17 STD SLOW 22 I/O I/O RESET
RD 11 14 FB4 MC2 STD FAST 24 I/O I/O RESET
WR 2 5 FB4 MC5 STD FAST 25 I/O O  
$OpTx$FX_DC$1331.LFBK 15 24 FB4 MC8 STD   26 I/O I  
Data_OUT<6> 2 3 FB4 MC11 STD FAST 28 I/O I/O RESET
Data_IN<7> 26 33 FB4 MC15 STD SLOW 33 I/O I/O RESET
Data_IN<6> 16 27 FB4 MC17 STD SLOW 34 I/O I/O RESET
W_CLK<0> 9 16 FB2 MC2 STD FAST 35 I/O O RESET
W_CLK<1> 9 16 FB2 MC5 STD FAST 36 I/O O RESET
W_CLK<2> 9 16 FB2 MC6 STD FAST 37 I/O O RESET
W_CLK<3> 10 23 FB2 MC8 STD FAST 38 I/O O RESET
CLK_DDS 1 1 FB2 MC9 STD FAST 39 I/O/GSR O  
DDS<1> 4 9 FB2 MC11 STD   40 I/O/GTS2 (b) RESET
state_FFd3 8 13 FB2 MC14 STD   42 I/O/GTS1 (b) RESET
RESET 3 12 FB2 MC15 STD FAST 43 I/O O  
FQ_UD 2 13 FB2 MC17 STD FAST 44 I/O O  
$OpTx$INV$13_2_ 3 17 FB1 MC3 STD     (b) (b)        
Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_2_ 5 7 FB1 MC4 STD     (b) (b)        
Madd_checksum_add0000_CARRY_IN<6>/Madd_checksum_add0000_CARRY_IN<6>_D2_0_ 5 7 FB1 MC7 STD     (b) (b)        
Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_2_ 5 8 FB1 MC10 STD     (b) (b)        
Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_1_ 5 8 FB1 MC12 STD     (b) (b)        
Madd_checksum_add0000_CARRY_IN<4>/Madd_checksum_add0000_CARRY_IN<4>_D2_0_ 5 8 FB1 MC13 STD     (b) (b)        
$OpTx$INV$13_1_ 5 12 FB1 MC16 STD     (b) (b)        
$OpTx$INV$13_0_ 5 14 FB1 MC18 STD     (b) (b)        
$OpTx$FX_DC$1328 1 2 FB2 MC7 STD     (b) (b)        
DDS<2> 4 9 FB2 MC10 STD     (b) (b) T     RESET
DDS<0> 4 9 FB2 MC12 STD     (b) (b) T     RESET
state_FFd1 5 6 FB2 MC13 STD     (b) (b) D     RESET
state_FFd4 9 13 FB2 MC16 STD     (b) (b) D     RESET
state_FFd2 9 17 FB2 MC18 STD     (b) (b) T     RESET
Madd_checksum_add0000_CARRY_IN<5>/Madd_checksum_add0000_CARRY_IN<5>_D2_1_ 2 4 FB3 MC1 STD     (b) (b)        
$OpTx$FX_DC$1329.LFBK 2 2 FB4 MC4 STD     (b) (b)        
BUF_checksum<6>__$$INT.LFBK 16 28 FB4 MC10 STD     (b) (b)