#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U) |
#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U) |
#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U) |
#define ADC_BASE (APB2PERIPH_BASE + 0x2300U) |
#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U) |
#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U) |
APB1 peripherals
#define APB1PERIPH_BASE PERIPH_BASE |
#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U) |
#define BKPSRAM_BASE 0x40024000U |
Base address of : Backup SRAM(4 KB)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U) |
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U) |
#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U) |
#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U) |
#define DAC_BASE (APB1PERIPH_BASE + 0x7400U) |
#define DBGMCU_BASE 0xE0042000U |
USB registers base address
#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U) |
#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U) |
#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U) |
#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U) |
#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U) |
#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U) |
#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U) |
#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U) |
#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U) |
#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U) |
#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U) |
#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U) |
#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U) |
#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U) |
#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U) |
#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U) |
#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U) |
#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U) |
#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U) |
#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U) |
AHB2 peripherals
#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U) |
#define ETH_DMA_BASE (ETH_BASE + 0x1000U) |
#define ETH_MAC_BASE (ETH_BASE) |
#define ETH_MMC_BASE (ETH_BASE + 0x0100U) |
#define ETH_PTP_BASE (ETH_BASE + 0x0700U) |
#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U) |
#define FLASH_BASE FLASHAXI_BASE |
Peripheral memory map
#define FLASH_END 0x080FFFFFU |
FLASH end address
#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U) |
#define FLASHAXI_BASE 0x08000000U |
Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI
#define FLASHITCM_BASE 0x00200000U |
Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM
#define FLASHSIZE_BASE 0x1FF0F442U |
FLASH Size register base address
#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U) |
#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U) |
#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U) |
#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U) |
#define FMC_R_BASE 0xA0000000U |
Base address of : FMC Control registers
#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U) |
#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U) |
#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U) |
#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U) |
#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U) |
#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U) |
#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U) |
#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U) |
#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U) |
#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U) |
#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U) |
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U) |
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U) |
#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U) |
#define I2C4_BASE (APB1PERIPH_BASE + 0x6000U) |
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U) |
#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U) |
#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U) |
#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U) |
#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U) |
AHB1 peripherals
#define PACKAGESIZE_BASE 0x1FFF7BF0U |
Package size register base address
#define PERIPH_BASE 0x40000000U |
Base address of : AHB/ABP Peripherals
#define PWR_BASE (APB1PERIPH_BASE + 0x7000U) |
#define QSPI_BASE 0x90000000U |
Base address of : QSPI memories accessible over AXI
#define QSPI_R_BASE 0xA0001000U |
Base address of : QSPI Control registers
#define RAMDTCM_BASE 0x20000000U |
Base address of : 64KB system data RAM accessible over DTCM
#define RAMITCM_BASE 0x00000000U |
Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM
#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U) |
#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U) |
FMC Bankx registers base address
#define RTC_BASE (APB1PERIPH_BASE + 0x2800U) |
#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U) |
#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U) |
#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U) |
#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U) |
#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U) |
#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U) |
#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U) |
#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U) |
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U) |
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U) |
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U) |
#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U) |
#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U) |
#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U) |
#define SRAM1_BASE 0x20010000U |
Base address of : 240KB RAM1 accessible over AXI/AHB
#define SRAM2_BASE 0x2004C000U |
Base address of : 16KB RAM2 accessible over AXI/AHB
#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U) |
#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U) |
#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U) |
#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U) |
#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U) |
#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U) |
#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U) |
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U) |
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U) |
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U) |
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U) |
#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U) |
#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U) |
#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U) |
#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U) |
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U) |
#define UART5_BASE (APB1PERIPH_BASE + 0x5000U) |
#define UART7_BASE (APB1PERIPH_BASE + 0x7800U) |
#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U) |
APB2 peripherals
#define UID_BASE 0x1FF0F420U |
Unique device ID register base address
#define USART1_BASE (APB2PERIPH_BASE + 0x1000U) |
#define USART2_BASE (APB1PERIPH_BASE + 0x4400U) |
#define USART3_BASE (APB1PERIPH_BASE + 0x4800U) |
#define USART6_BASE (APB2PERIPH_BASE + 0x1400U) |
#define USB_OTG_DEVICE_BASE 0x800U |
#define USB_OTG_EP_REG_SIZE 0x20U |
#define USB_OTG_FIFO_BASE 0x1000U |
#define USB_OTG_FIFO_SIZE 0x1000U |
#define USB_OTG_FS_PERIPH_BASE 0x50000000U |
#define USB_OTG_GLOBAL_BASE 0x000U |
#define USB_OTG_HOST_BASE 0x400U |
#define USB_OTG_HOST_CHANNEL_BASE 0x500U |
#define USB_OTG_HOST_CHANNEL_SIZE 0x20U |
#define USB_OTG_HOST_PORT_BASE 0x440U |
#define USB_OTG_HS_PERIPH_BASE 0x40040000U |
#define USB_OTG_IN_ENDPOINT_BASE 0x900U |
#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U |
#define USB_OTG_PCGCCTL_BASE 0xE00U |
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U) |