#define ADC ((ADC_Common_TypeDef *) ADC_BASE) |
#define ADC1 ((ADC_TypeDef *) ADC1_BASE) |
#define ADC2 ((ADC_TypeDef *) ADC2_BASE) |
#define ADC3 ((ADC_TypeDef *) ADC3_BASE) |
#define CAN1 ((CAN_TypeDef *) CAN1_BASE) |
#define CAN2 ((CAN_TypeDef *) CAN2_BASE) |
#define CEC ((CEC_TypeDef *) CEC_BASE) |
#define CRC ((CRC_TypeDef *) CRC_BASE) |
#define DAC ((DAC_TypeDef *) DAC_BASE) |
#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) |
#define DCMI ((DCMI_TypeDef *) DCMI_BASE) |
#define DMA1 ((DMA_TypeDef *) DMA1_BASE) |
#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE) |
#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE) |
#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE) |
#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE) |
#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE) |
#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE) |
#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE) |
#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE) |
#define DMA2 ((DMA_TypeDef *) DMA2_BASE) |
#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE) |
#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE) |
#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE) |
#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE) |
#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE) |
#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE) |
#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE) |
#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE) |
#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE) |
#define ETH ((ETH_TypeDef *) ETH_BASE) |
#define EXTI ((EXTI_TypeDef *) EXTI_BASE) |
#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) |
#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE) |
#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE) |
#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE) |
#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE) |
#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) |
#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) |
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) |
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) |
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) |
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) |
#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE) |
#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE) |
#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE) |
#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE) |
#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE) |
#define I2C1 ((I2C_TypeDef *) I2C1_BASE) |
#define I2C2 ((I2C_TypeDef *) I2C2_BASE) |
#define I2C3 ((I2C_TypeDef *) I2C3_BASE) |
#define I2C4 ((I2C_TypeDef *) I2C4_BASE) |
#define IWDG ((IWDG_TypeDef *) IWDG_BASE) |
#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) |
#define LTDC ((LTDC_TypeDef *)LTDC_BASE) |
#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE) |
#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE) |
#define PWR ((PWR_TypeDef *) PWR_BASE) |
#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE) |
#define RCC ((RCC_TypeDef *) RCC_BASE) |
#define RNG ((RNG_TypeDef *) RNG_BASE) |
#define RTC ((RTC_TypeDef *) RTC_BASE) |
#define SAI1 ((SAI_TypeDef *) SAI1_BASE) |
#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE) |
#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE) |
#define SAI2 ((SAI_TypeDef *) SAI2_BASE) |
#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE) |
#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE) |
#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE) |
#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE) |
#define SPI1 ((SPI_TypeDef *) SPI1_BASE) |
#define SPI2 ((SPI_TypeDef *) SPI2_BASE) |
#define SPI3 ((SPI_TypeDef *) SPI3_BASE) |
#define SPI4 ((SPI_TypeDef *) SPI4_BASE) |
#define SPI5 ((SPI_TypeDef *) SPI5_BASE) |
#define SPI6 ((SPI_TypeDef *) SPI6_BASE) |
#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) |
#define TIM1 ((TIM_TypeDef *) TIM1_BASE) |
#define TIM10 ((TIM_TypeDef *) TIM10_BASE) |
#define TIM11 ((TIM_TypeDef *) TIM11_BASE) |
#define TIM12 ((TIM_TypeDef *) TIM12_BASE) |
#define TIM13 ((TIM_TypeDef *) TIM13_BASE) |
#define TIM14 ((TIM_TypeDef *) TIM14_BASE) |
#define TIM2 ((TIM_TypeDef *) TIM2_BASE) |
#define TIM3 ((TIM_TypeDef *) TIM3_BASE) |
#define TIM4 ((TIM_TypeDef *) TIM4_BASE) |
#define TIM5 ((TIM_TypeDef *) TIM5_BASE) |
#define TIM6 ((TIM_TypeDef *) TIM6_BASE) |
#define TIM7 ((TIM_TypeDef *) TIM7_BASE) |
#define TIM8 ((TIM_TypeDef *) TIM8_BASE) |
#define TIM9 ((TIM_TypeDef *) TIM9_BASE) |
#define UART4 ((USART_TypeDef *) UART4_BASE) |
#define UART5 ((USART_TypeDef *) UART5_BASE) |
#define UART7 ((USART_TypeDef *) UART7_BASE) |
#define UART8 ((USART_TypeDef *) UART8_BASE) |
#define USART1 ((USART_TypeDef *) USART1_BASE) |
#define USART2 ((USART_TypeDef *) USART2_BASE) |
#define USART3 ((USART_TypeDef *) USART3_BASE) |
#define USART6 ((USART_TypeDef *) USART6_BASE) |
#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE) |
#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE) |
#define WWDG ((WWDG_TypeDef *) WWDG_BASE) |