Flexible Memory Controller Bank5_6. More...
#include <stm32f746xx.h>
Data Fields | |
__IO uint32_t | SDCR [2] |
__IO uint32_t | SDTR [2] |
__IO uint32_t | SDCMR |
__IO uint32_t | SDRTR |
__IO uint32_t | SDSR |
Flexible Memory Controller Bank5_6.
__IO uint32_t FMC_Bank5_6_TypeDef::SDCMR |
SDRAM Command Mode register, Address offset: 0x150
__IO uint32_t FMC_Bank5_6_TypeDef::SDCR[2] |
SDRAM Control registers , Address offset: 0x140-0x144
__IO uint32_t FMC_Bank5_6_TypeDef::SDRTR |
SDRAM Refresh Timer register, Address offset: 0x154
__IO uint32_t FMC_Bank5_6_TypeDef::SDSR |
SDRAM Status register, Address offset: 0x158
__IO uint32_t FMC_Bank5_6_TypeDef::SDTR[2] |
SDRAM Timing registers , Address offset: 0x148-0x14C