EU1KY AA FW
Peripheral_Registers_Bits_Definition

Macros

#define ADC_SR_AWD   0x00000001U
 
#define ADC_SR_EOC   0x00000002U
 
#define ADC_SR_JEOC   0x00000004U
 
#define ADC_SR_JSTRT   0x00000008U
 
#define ADC_SR_STRT   0x00000010U
 
#define ADC_SR_OVR   0x00000020U
 
#define ADC_CR1_AWDCH   0x0000001FU
 
#define ADC_CR1_AWDCH_0   0x00000001U
 
#define ADC_CR1_AWDCH_1   0x00000002U
 
#define ADC_CR1_AWDCH_2   0x00000004U
 
#define ADC_CR1_AWDCH_3   0x00000008U
 
#define ADC_CR1_AWDCH_4   0x00000010U
 
#define ADC_CR1_EOCIE   0x00000020U
 
#define ADC_CR1_AWDIE   0x00000040U
 
#define ADC_CR1_JEOCIE   0x00000080U
 
#define ADC_CR1_SCAN   0x00000100U
 
#define ADC_CR1_AWDSGL   0x00000200U
 
#define ADC_CR1_JAUTO   0x00000400U
 
#define ADC_CR1_DISCEN   0x00000800U
 
#define ADC_CR1_JDISCEN   0x00001000U
 
#define ADC_CR1_DISCNUM   0x0000E000U
 
#define ADC_CR1_DISCNUM_0   0x00002000U
 
#define ADC_CR1_DISCNUM_1   0x00004000U
 
#define ADC_CR1_DISCNUM_2   0x00008000U
 
#define ADC_CR1_JAWDEN   0x00400000U
 
#define ADC_CR1_AWDEN   0x00800000U
 
#define ADC_CR1_RES   0x03000000U
 
#define ADC_CR1_RES_0   0x01000000U
 
#define ADC_CR1_RES_1   0x02000000U
 
#define ADC_CR1_OVRIE   0x04000000U
 
#define ADC_CR2_ADON   0x00000001U
 
#define ADC_CR2_CONT   0x00000002U
 
#define ADC_CR2_DMA   0x00000100U
 
#define ADC_CR2_DDS   0x00000200U
 
#define ADC_CR2_EOCS   0x00000400U
 
#define ADC_CR2_ALIGN   0x00000800U
 
#define ADC_CR2_JEXTSEL   0x000F0000U
 
#define ADC_CR2_JEXTSEL_0   0x00010000U
 
#define ADC_CR2_JEXTSEL_1   0x00020000U
 
#define ADC_CR2_JEXTSEL_2   0x00040000U
 
#define ADC_CR2_JEXTSEL_3   0x00080000U
 
#define ADC_CR2_JEXTEN   0x00300000U
 
#define ADC_CR2_JEXTEN_0   0x00100000U
 
#define ADC_CR2_JEXTEN_1   0x00200000U
 
#define ADC_CR2_JSWSTART   0x00400000U
 
#define ADC_CR2_EXTSEL   0x0F000000U
 
#define ADC_CR2_EXTSEL_0   0x01000000U
 
#define ADC_CR2_EXTSEL_1   0x02000000U
 
#define ADC_CR2_EXTSEL_2   0x04000000U
 
#define ADC_CR2_EXTSEL_3   0x08000000U
 
#define ADC_CR2_EXTEN   0x30000000U
 
#define ADC_CR2_EXTEN_0   0x10000000U
 
#define ADC_CR2_EXTEN_1   0x20000000U
 
#define ADC_CR2_SWSTART   0x40000000U
 
#define ADC_SMPR1_SMP10   0x00000007U
 
#define ADC_SMPR1_SMP10_0   0x00000001U
 
#define ADC_SMPR1_SMP10_1   0x00000002U
 
#define ADC_SMPR1_SMP10_2   0x00000004U
 
#define ADC_SMPR1_SMP11   0x00000038U
 
#define ADC_SMPR1_SMP11_0   0x00000008U
 
#define ADC_SMPR1_SMP11_1   0x00000010U
 
#define ADC_SMPR1_SMP11_2   0x00000020U
 
#define ADC_SMPR1_SMP12   0x000001C0U
 
#define ADC_SMPR1_SMP12_0   0x00000040U
 
#define ADC_SMPR1_SMP12_1   0x00000080U
 
#define ADC_SMPR1_SMP12_2   0x00000100U
 
#define ADC_SMPR1_SMP13   0x00000E00U
 
#define ADC_SMPR1_SMP13_0   0x00000200U
 
#define ADC_SMPR1_SMP13_1   0x00000400U
 
#define ADC_SMPR1_SMP13_2   0x00000800U
 
#define ADC_SMPR1_SMP14   0x00007000U
 
#define ADC_SMPR1_SMP14_0   0x00001000U
 
#define ADC_SMPR1_SMP14_1   0x00002000U
 
#define ADC_SMPR1_SMP14_2   0x00004000U
 
#define ADC_SMPR1_SMP15   0x00038000U
 
#define ADC_SMPR1_SMP15_0   0x00008000U
 
#define ADC_SMPR1_SMP15_1   0x00010000U
 
#define ADC_SMPR1_SMP15_2   0x00020000U
 
#define ADC_SMPR1_SMP16   0x001C0000U
 
#define ADC_SMPR1_SMP16_0   0x00040000U
 
#define ADC_SMPR1_SMP16_1   0x00080000U
 
#define ADC_SMPR1_SMP16_2   0x00100000U
 
#define ADC_SMPR1_SMP17   0x00E00000U
 
#define ADC_SMPR1_SMP17_0   0x00200000U
 
#define ADC_SMPR1_SMP17_1   0x00400000U
 
#define ADC_SMPR1_SMP17_2   0x00800000U
 
#define ADC_SMPR1_SMP18   0x07000000U
 
#define ADC_SMPR1_SMP18_0   0x01000000U
 
#define ADC_SMPR1_SMP18_1   0x02000000U
 
#define ADC_SMPR1_SMP18_2   0x04000000U
 
#define ADC_SMPR2_SMP0   0x00000007U
 
#define ADC_SMPR2_SMP0_0   0x00000001U
 
#define ADC_SMPR2_SMP0_1   0x00000002U
 
#define ADC_SMPR2_SMP0_2   0x00000004U
 
#define ADC_SMPR2_SMP1   0x00000038U
 
#define ADC_SMPR2_SMP1_0   0x00000008U
 
#define ADC_SMPR2_SMP1_1   0x00000010U
 
#define ADC_SMPR2_SMP1_2   0x00000020U
 
#define ADC_SMPR2_SMP2   0x000001C0U
 
#define ADC_SMPR2_SMP2_0   0x00000040U
 
#define ADC_SMPR2_SMP2_1   0x00000080U
 
#define ADC_SMPR2_SMP2_2   0x00000100U
 
#define ADC_SMPR2_SMP3   0x00000E00U
 
#define ADC_SMPR2_SMP3_0   0x00000200U
 
#define ADC_SMPR2_SMP3_1   0x00000400U
 
#define ADC_SMPR2_SMP3_2   0x00000800U
 
#define ADC_SMPR2_SMP4   0x00007000U
 
#define ADC_SMPR2_SMP4_0   0x00001000U
 
#define ADC_SMPR2_SMP4_1   0x00002000U
 
#define ADC_SMPR2_SMP4_2   0x00004000U
 
#define ADC_SMPR2_SMP5   0x00038000U
 
#define ADC_SMPR2_SMP5_0   0x00008000U
 
#define ADC_SMPR2_SMP5_1   0x00010000U
 
#define ADC_SMPR2_SMP5_2   0x00020000U
 
#define ADC_SMPR2_SMP6   0x001C0000U
 
#define ADC_SMPR2_SMP6_0   0x00040000U
 
#define ADC_SMPR2_SMP6_1   0x00080000U
 
#define ADC_SMPR2_SMP6_2   0x00100000U
 
#define ADC_SMPR2_SMP7   0x00E00000U
 
#define ADC_SMPR2_SMP7_0   0x00200000U
 
#define ADC_SMPR2_SMP7_1   0x00400000U
 
#define ADC_SMPR2_SMP7_2   0x00800000U
 
#define ADC_SMPR2_SMP8   0x07000000U
 
#define ADC_SMPR2_SMP8_0   0x01000000U
 
#define ADC_SMPR2_SMP8_1   0x02000000U
 
#define ADC_SMPR2_SMP8_2   0x04000000U
 
#define ADC_SMPR2_SMP9   0x38000000U
 
#define ADC_SMPR2_SMP9_0   0x08000000U
 
#define ADC_SMPR2_SMP9_1   0x10000000U
 
#define ADC_SMPR2_SMP9_2   0x20000000U
 
#define ADC_JOFR1_JOFFSET1   0x0FFFU
 
#define ADC_JOFR2_JOFFSET2   0x0FFFU
 
#define ADC_JOFR3_JOFFSET3   0x0FFFU
 
#define ADC_JOFR4_JOFFSET4   0x0FFFU
 
#define ADC_HTR_HT   0x0FFFU
 
#define ADC_LTR_LT   0x0FFFU
 
#define ADC_SQR1_SQ13   0x0000001FU
 
#define ADC_SQR1_SQ13_0   0x00000001U
 
#define ADC_SQR1_SQ13_1   0x00000002U
 
#define ADC_SQR1_SQ13_2   0x00000004U
 
#define ADC_SQR1_SQ13_3   0x00000008U
 
#define ADC_SQR1_SQ13_4   0x00000010U
 
#define ADC_SQR1_SQ14   0x000003E0U
 
#define ADC_SQR1_SQ14_0   0x00000020U
 
#define ADC_SQR1_SQ14_1   0x00000040U
 
#define ADC_SQR1_SQ14_2   0x00000080U
 
#define ADC_SQR1_SQ14_3   0x00000100U
 
#define ADC_SQR1_SQ14_4   0x00000200U
 
#define ADC_SQR1_SQ15   0x00007C00U
 
#define ADC_SQR1_SQ15_0   0x00000400U
 
#define ADC_SQR1_SQ15_1   0x00000800U
 
#define ADC_SQR1_SQ15_2   0x00001000U
 
#define ADC_SQR1_SQ15_3   0x00002000U
 
#define ADC_SQR1_SQ15_4   0x00004000U
 
#define ADC_SQR1_SQ16   0x000F8000U
 
#define ADC_SQR1_SQ16_0   0x00008000U
 
#define ADC_SQR1_SQ16_1   0x00010000U
 
#define ADC_SQR1_SQ16_2   0x00020000U
 
#define ADC_SQR1_SQ16_3   0x00040000U
 
#define ADC_SQR1_SQ16_4   0x00080000U
 
#define ADC_SQR1_L   0x00F00000U
 
#define ADC_SQR1_L_0   0x00100000U
 
#define ADC_SQR1_L_1   0x00200000U
 
#define ADC_SQR1_L_2   0x00400000U
 
#define ADC_SQR1_L_3   0x00800000U
 
#define ADC_SQR2_SQ7   0x0000001FU
 
#define ADC_SQR2_SQ7_0   0x00000001U
 
#define ADC_SQR2_SQ7_1   0x00000002U
 
#define ADC_SQR2_SQ7_2   0x00000004U
 
#define ADC_SQR2_SQ7_3   0x00000008U
 
#define ADC_SQR2_SQ7_4   0x00000010U
 
#define ADC_SQR2_SQ8   0x000003E0U
 
#define ADC_SQR2_SQ8_0   0x00000020U
 
#define ADC_SQR2_SQ8_1   0x00000040U
 
#define ADC_SQR2_SQ8_2   0x00000080U
 
#define ADC_SQR2_SQ8_3   0x00000100U
 
#define ADC_SQR2_SQ8_4   0x00000200U
 
#define ADC_SQR2_SQ9   0x00007C00U
 
#define ADC_SQR2_SQ9_0   0x00000400U
 
#define ADC_SQR2_SQ9_1   0x00000800U
 
#define ADC_SQR2_SQ9_2   0x00001000U
 
#define ADC_SQR2_SQ9_3   0x00002000U
 
#define ADC_SQR2_SQ9_4   0x00004000U
 
#define ADC_SQR2_SQ10   0x000F8000U
 
#define ADC_SQR2_SQ10_0   0x00008000U
 
#define ADC_SQR2_SQ10_1   0x00010000U
 
#define ADC_SQR2_SQ10_2   0x00020000U
 
#define ADC_SQR2_SQ10_3   0x00040000U
 
#define ADC_SQR2_SQ10_4   0x00080000U
 
#define ADC_SQR2_SQ11   0x01F00000U
 
#define ADC_SQR2_SQ11_0   0x00100000U
 
#define ADC_SQR2_SQ11_1   0x00200000U
 
#define ADC_SQR2_SQ11_2   0x00400000U
 
#define ADC_SQR2_SQ11_3   0x00800000U
 
#define ADC_SQR2_SQ11_4   0x01000000U
 
#define ADC_SQR2_SQ12   0x3E000000U
 
#define ADC_SQR2_SQ12_0   0x02000000U
 
#define ADC_SQR2_SQ12_1   0x04000000U
 
#define ADC_SQR2_SQ12_2   0x08000000U
 
#define ADC_SQR2_SQ12_3   0x10000000U
 
#define ADC_SQR2_SQ12_4   0x20000000U
 
#define ADC_SQR3_SQ1   0x0000001FU
 
#define ADC_SQR3_SQ1_0   0x00000001U
 
#define ADC_SQR3_SQ1_1   0x00000002U
 
#define ADC_SQR3_SQ1_2   0x00000004U
 
#define ADC_SQR3_SQ1_3   0x00000008U
 
#define ADC_SQR3_SQ1_4   0x00000010U
 
#define ADC_SQR3_SQ2   0x000003E0U
 
#define ADC_SQR3_SQ2_0   0x00000020U
 
#define ADC_SQR3_SQ2_1   0x00000040U
 
#define ADC_SQR3_SQ2_2   0x00000080U
 
#define ADC_SQR3_SQ2_3   0x00000100U
 
#define ADC_SQR3_SQ2_4   0x00000200U
 
#define ADC_SQR3_SQ3   0x00007C00U
 
#define ADC_SQR3_SQ3_0   0x00000400U
 
#define ADC_SQR3_SQ3_1   0x00000800U
 
#define ADC_SQR3_SQ3_2   0x00001000U
 
#define ADC_SQR3_SQ3_3   0x00002000U
 
#define ADC_SQR3_SQ3_4   0x00004000U
 
#define ADC_SQR3_SQ4   0x000F8000U
 
#define ADC_SQR3_SQ4_0   0x00008000U
 
#define ADC_SQR3_SQ4_1   0x00010000U
 
#define ADC_SQR3_SQ4_2   0x00020000U
 
#define ADC_SQR3_SQ4_3   0x00040000U
 
#define ADC_SQR3_SQ4_4   0x00080000U
 
#define ADC_SQR3_SQ5   0x01F00000U
 
#define ADC_SQR3_SQ5_0   0x00100000U
 
#define ADC_SQR3_SQ5_1   0x00200000U
 
#define ADC_SQR3_SQ5_2   0x00400000U
 
#define ADC_SQR3_SQ5_3   0x00800000U
 
#define ADC_SQR3_SQ5_4   0x01000000U
 
#define ADC_SQR3_SQ6   0x3E000000U
 
#define ADC_SQR3_SQ6_0   0x02000000U
 
#define ADC_SQR3_SQ6_1   0x04000000U
 
#define ADC_SQR3_SQ6_2   0x08000000U
 
#define ADC_SQR3_SQ6_3   0x10000000U
 
#define ADC_SQR3_SQ6_4   0x20000000U
 
#define ADC_JSQR_JSQ1   0x0000001FU
 
#define ADC_JSQR_JSQ1_0   0x00000001U
 
#define ADC_JSQR_JSQ1_1   0x00000002U
 
#define ADC_JSQR_JSQ1_2   0x00000004U
 
#define ADC_JSQR_JSQ1_3   0x00000008U
 
#define ADC_JSQR_JSQ1_4   0x00000010U
 
#define ADC_JSQR_JSQ2   0x000003E0U
 
#define ADC_JSQR_JSQ2_0   0x00000020U
 
#define ADC_JSQR_JSQ2_1   0x00000040U
 
#define ADC_JSQR_JSQ2_2   0x00000080U
 
#define ADC_JSQR_JSQ2_3   0x00000100U
 
#define ADC_JSQR_JSQ2_4   0x00000200U
 
#define ADC_JSQR_JSQ3   0x00007C00U
 
#define ADC_JSQR_JSQ3_0   0x00000400U
 
#define ADC_JSQR_JSQ3_1   0x00000800U
 
#define ADC_JSQR_JSQ3_2   0x00001000U
 
#define ADC_JSQR_JSQ3_3   0x00002000U
 
#define ADC_JSQR_JSQ3_4   0x00004000U
 
#define ADC_JSQR_JSQ4   0x000F8000U
 
#define ADC_JSQR_JSQ4_0   0x00008000U
 
#define ADC_JSQR_JSQ4_1   0x00010000U
 
#define ADC_JSQR_JSQ4_2   0x00020000U
 
#define ADC_JSQR_JSQ4_3   0x00040000U
 
#define ADC_JSQR_JSQ4_4   0x00080000U
 
#define ADC_JSQR_JL   0x00300000U
 
#define ADC_JSQR_JL_0   0x00100000U
 
#define ADC_JSQR_JL_1   0x00200000U
 
#define ADC_JDR1_JDATA   ((uint16_t)0xFFFFU)
 
#define ADC_JDR2_JDATA   ((uint16_t)0xFFFFU)
 
#define ADC_JDR3_JDATA   ((uint16_t)0xFFFFU)
 
#define ADC_JDR4_JDATA   ((uint16_t)0xFFFFU)
 
#define ADC_DR_DATA   0x0000FFFFU
 
#define ADC_DR_ADC2DATA   0xFFFF0000U
 
#define ADC_CSR_AWD1   0x00000001U
 
#define ADC_CSR_EOC1   0x00000002U
 
#define ADC_CSR_JEOC1   0x00000004U
 
#define ADC_CSR_JSTRT1   0x00000008U
 
#define ADC_CSR_STRT1   0x00000010U
 
#define ADC_CSR_OVR1   0x00000020U
 
#define ADC_CSR_AWD2   0x00000100U
 
#define ADC_CSR_EOC2   0x00000200U
 
#define ADC_CSR_JEOC2   0x00000400U
 
#define ADC_CSR_JSTRT2   0x00000800U
 
#define ADC_CSR_STRT2   0x00001000U
 
#define ADC_CSR_OVR2   0x00002000U
 
#define ADC_CSR_AWD3   0x00010000U
 
#define ADC_CSR_EOC3   0x00020000U
 
#define ADC_CSR_JEOC3   0x00040000U
 
#define ADC_CSR_JSTRT3   0x00080000U
 
#define ADC_CSR_STRT3   0x00100000U
 
#define ADC_CSR_OVR3   0x00200000U
 
#define ADC_CSR_DOVR1   ADC_CSR_OVR1
 
#define ADC_CSR_DOVR2   ADC_CSR_OVR2
 
#define ADC_CSR_DOVR3   ADC_CSR_OVR3
 
#define ADC_CCR_MULTI   0x0000001FU
 
#define ADC_CCR_MULTI_0   0x00000001U
 
#define ADC_CCR_MULTI_1   0x00000002U
 
#define ADC_CCR_MULTI_2   0x00000004U
 
#define ADC_CCR_MULTI_3   0x00000008U
 
#define ADC_CCR_MULTI_4   0x00000010U
 
#define ADC_CCR_DELAY   0x00000F00U
 
#define ADC_CCR_DELAY_0   0x00000100U
 
#define ADC_CCR_DELAY_1   0x00000200U
 
#define ADC_CCR_DELAY_2   0x00000400U
 
#define ADC_CCR_DELAY_3   0x00000800U
 
#define ADC_CCR_DDS   0x00002000U
 
#define ADC_CCR_DMA   0x0000C000U
 
#define ADC_CCR_DMA_0   0x00004000U
 
#define ADC_CCR_DMA_1   0x00008000U
 
#define ADC_CCR_ADCPRE   0x00030000U
 
#define ADC_CCR_ADCPRE_0   0x00010000U
 
#define ADC_CCR_ADCPRE_1   0x00020000U
 
#define ADC_CCR_VBATE   0x00400000U
 
#define ADC_CCR_TSVREFE   0x00800000U
 
#define ADC_CDR_DATA1   0x0000FFFFU
 
#define ADC_CDR_DATA2   0xFFFF0000U
 
#define CAN_MCR_INRQ   0x00000001U
 
#define CAN_MCR_SLEEP   0x00000002U
 
#define CAN_MCR_TXFP   0x00000004U
 
#define CAN_MCR_RFLM   0x00000008U
 
#define CAN_MCR_NART   0x00000010U
 
#define CAN_MCR_AWUM   0x00000020U
 
#define CAN_MCR_ABOM   0x00000040U
 
#define CAN_MCR_TTCM   0x00000080U
 
#define CAN_MCR_RESET   0x00008000U
 
#define CAN_MSR_INAK   0x00000001U
 
#define CAN_MSR_SLAK   0x00000002U
 
#define CAN_MSR_ERRI   0x00000004U
 
#define CAN_MSR_WKUI   0x00000008U
 
#define CAN_MSR_SLAKI   0x00000010U
 
#define CAN_MSR_TXM   0x00000100U
 
#define CAN_MSR_RXM   0x00000200U
 
#define CAN_MSR_SAMP   0x00000400U
 
#define CAN_MSR_RX   0x00000800U
 
#define CAN_TSR_RQCP0   0x00000001U
 
#define CAN_TSR_TXOK0   0x00000002U
 
#define CAN_TSR_ALST0   0x00000004U
 
#define CAN_TSR_TERR0   0x00000008U
 
#define CAN_TSR_ABRQ0   0x00000080U
 
#define CAN_TSR_RQCP1   0x00000100U
 
#define CAN_TSR_TXOK1   0x00000200U
 
#define CAN_TSR_ALST1   0x00000400U
 
#define CAN_TSR_TERR1   0x00000800U
 
#define CAN_TSR_ABRQ1   0x00008000U
 
#define CAN_TSR_RQCP2   0x00010000U
 
#define CAN_TSR_TXOK2   0x00020000U
 
#define CAN_TSR_ALST2   0x00040000U
 
#define CAN_TSR_TERR2   0x00080000U
 
#define CAN_TSR_ABRQ2   0x00800000U
 
#define CAN_TSR_CODE   0x03000000U
 
#define CAN_TSR_TME   0x1C000000U
 
#define CAN_TSR_TME0   0x04000000U
 
#define CAN_TSR_TME1   0x08000000U
 
#define CAN_TSR_TME2   0x10000000U
 
#define CAN_TSR_LOW   0xE0000000U
 
#define CAN_TSR_LOW0   0x20000000U
 
#define CAN_TSR_LOW1   0x40000000U
 
#define CAN_TSR_LOW2   0x80000000U
 
#define CAN_RF0R_FMP0   0x00000003U
 
#define CAN_RF0R_FULL0   0x00000008U
 
#define CAN_RF0R_FOVR0   0x00000010U
 
#define CAN_RF0R_RFOM0   0x00000020U
 
#define CAN_RF1R_FMP1   0x00000003U
 
#define CAN_RF1R_FULL1   0x00000008U
 
#define CAN_RF1R_FOVR1   0x00000010U
 
#define CAN_RF1R_RFOM1   0x00000020U
 
#define CAN_IER_TMEIE   0x00000001U
 
#define CAN_IER_FMPIE0   0x00000002U
 
#define CAN_IER_FFIE0   0x00000004U
 
#define CAN_IER_FOVIE0   0x00000008U
 
#define CAN_IER_FMPIE1   0x00000010U
 
#define CAN_IER_FFIE1   0x00000020U
 
#define CAN_IER_FOVIE1   0x00000040U
 
#define CAN_IER_EWGIE   0x00000100U
 
#define CAN_IER_EPVIE   0x00000200U
 
#define CAN_IER_BOFIE   0x00000400U
 
#define CAN_IER_LECIE   0x00000800U
 
#define CAN_IER_ERRIE   0x00008000U
 
#define CAN_IER_WKUIE   0x00010000U
 
#define CAN_IER_SLKIE   0x00020000U
 
#define CAN_ESR_EWGF   0x00000001U
 
#define CAN_ESR_EPVF   0x00000002U
 
#define CAN_ESR_BOFF   0x00000004U
 
#define CAN_ESR_LEC   0x00000070U
 
#define CAN_ESR_LEC_0   0x00000010U
 
#define CAN_ESR_LEC_1   0x00000020U
 
#define CAN_ESR_LEC_2   0x00000040U
 
#define CAN_ESR_TEC   0x00FF0000U
 
#define CAN_ESR_REC   0xFF000000U
 
#define CAN_BTR_BRP   0x000003FFU
 
#define CAN_BTR_TS1   0x000F0000U
 
#define CAN_BTR_TS1_0   0x00010000U
 
#define CAN_BTR_TS1_1   0x00020000U
 
#define CAN_BTR_TS1_2   0x00040000U
 
#define CAN_BTR_TS1_3   0x00080000U
 
#define CAN_BTR_TS2   0x00700000U
 
#define CAN_BTR_TS2_0   0x00100000U
 
#define CAN_BTR_TS2_1   0x00200000U
 
#define CAN_BTR_TS2_2   0x00400000U
 
#define CAN_BTR_SJW   0x03000000U
 
#define CAN_BTR_SJW_0   0x01000000U
 
#define CAN_BTR_SJW_1   0x02000000U
 
#define CAN_BTR_LBKM   0x40000000U
 
#define CAN_BTR_SILM   0x80000000U
 
#define CAN_TI0R_TXRQ   0x00000001U
 
#define CAN_TI0R_RTR   0x00000002U
 
#define CAN_TI0R_IDE   0x00000004U
 
#define CAN_TI0R_EXID   0x001FFFF8U
 
#define CAN_TI0R_STID   0xFFE00000U
 
#define CAN_TDT0R_DLC   0x0000000FU
 
#define CAN_TDT0R_TGT   0x00000100U
 
#define CAN_TDT0R_TIME   0xFFFF0000U
 
#define CAN_TDL0R_DATA0   0x000000FFU
 
#define CAN_TDL0R_DATA1   0x0000FF00U
 
#define CAN_TDL0R_DATA2   0x00FF0000U
 
#define CAN_TDL0R_DATA3   0xFF000000U
 
#define CAN_TDH0R_DATA4   0x000000FFU
 
#define CAN_TDH0R_DATA5   0x0000FF00U
 
#define CAN_TDH0R_DATA6   0x00FF0000U
 
#define CAN_TDH0R_DATA7   0xFF000000U
 
#define CAN_TI1R_TXRQ   0x00000001U
 
#define CAN_TI1R_RTR   0x00000002U
 
#define CAN_TI1R_IDE   0x00000004U
 
#define CAN_TI1R_EXID   0x001FFFF8U
 
#define CAN_TI1R_STID   0xFFE00000U
 
#define CAN_TDT1R_DLC   0x0000000FU
 
#define CAN_TDT1R_TGT   0x00000100U
 
#define CAN_TDT1R_TIME   0xFFFF0000U
 
#define CAN_TDL1R_DATA0   0x000000FFU
 
#define CAN_TDL1R_DATA1   0x0000FF00U
 
#define CAN_TDL1R_DATA2   0x00FF0000U
 
#define CAN_TDL1R_DATA3   0xFF000000U
 
#define CAN_TDH1R_DATA4   0x000000FFU
 
#define CAN_TDH1R_DATA5   0x0000FF00U
 
#define CAN_TDH1R_DATA6   0x00FF0000U
 
#define CAN_TDH1R_DATA7   0xFF000000U
 
#define CAN_TI2R_TXRQ   0x00000001U
 
#define CAN_TI2R_RTR   0x00000002U
 
#define CAN_TI2R_IDE   0x00000004U
 
#define CAN_TI2R_EXID   0x001FFFF8U
 
#define CAN_TI2R_STID   0xFFE00000U
 
#define CAN_TDT2R_DLC   0x0000000FU
 
#define CAN_TDT2R_TGT   0x00000100U
 
#define CAN_TDT2R_TIME   0xFFFF0000U
 
#define CAN_TDL2R_DATA0   0x000000FFU
 
#define CAN_TDL2R_DATA1   0x0000FF00U
 
#define CAN_TDL2R_DATA2   0x00FF0000U
 
#define CAN_TDL2R_DATA3   0xFF000000U
 
#define CAN_TDH2R_DATA4   0x000000FFU
 
#define CAN_TDH2R_DATA5   0x0000FF00U
 
#define CAN_TDH2R_DATA6   0x00FF0000U
 
#define CAN_TDH2R_DATA7   0xFF000000U
 
#define CAN_RI0R_RTR   0x00000002U
 
#define CAN_RI0R_IDE   0x00000004U
 
#define CAN_RI0R_EXID   0x001FFFF8U
 
#define CAN_RI0R_STID   0xFFE00000U
 
#define CAN_RDT0R_DLC   0x0000000FU
 
#define CAN_RDT0R_FMI   0x0000FF00U
 
#define CAN_RDT0R_TIME   0xFFFF0000U
 
#define CAN_RDL0R_DATA0   0x000000FFU
 
#define CAN_RDL0R_DATA1   0x0000FF00U
 
#define CAN_RDL0R_DATA2   0x00FF0000U
 
#define CAN_RDL0R_DATA3   0xFF000000U
 
#define CAN_RDH0R_DATA4   0x000000FFU
 
#define CAN_RDH0R_DATA5   0x0000FF00U
 
#define CAN_RDH0R_DATA6   0x00FF0000U
 
#define CAN_RDH0R_DATA7   0xFF000000U
 
#define CAN_RI1R_RTR   0x00000002U
 
#define CAN_RI1R_IDE   0x00000004U
 
#define CAN_RI1R_EXID   0x001FFFF8U
 
#define CAN_RI1R_STID   0xFFE00000U
 
#define CAN_RDT1R_DLC   0x0000000FU
 
#define CAN_RDT1R_FMI   0x0000FF00U
 
#define CAN_RDT1R_TIME   0xFFFF0000U
 
#define CAN_RDL1R_DATA0   0x000000FFU
 
#define CAN_RDL1R_DATA1   0x0000FF00U
 
#define CAN_RDL1R_DATA2   0x00FF0000U
 
#define CAN_RDL1R_DATA3   0xFF000000U
 
#define CAN_RDH1R_DATA4   0x000000FFU
 
#define CAN_RDH1R_DATA5   0x0000FF00U
 
#define CAN_RDH1R_DATA6   0x00FF0000U
 
#define CAN_RDH1R_DATA7   0xFF000000U
 
#define CAN_FMR_FINIT   ((uint8_t)0x01U)
 
#define CAN_FMR_CAN2SB   0x00003F00U
 
#define CAN_FM1R_FBM   0x3FFFU
 
#define CAN_FM1R_FBM0   0x0001U
 
#define CAN_FM1R_FBM1   0x0002U
 
#define CAN_FM1R_FBM2   0x0004U
 
#define CAN_FM1R_FBM3   0x0008U
 
#define CAN_FM1R_FBM4   0x0010U
 
#define CAN_FM1R_FBM5   0x0020U
 
#define CAN_FM1R_FBM6   0x0040U
 
#define CAN_FM1R_FBM7   0x0080U
 
#define CAN_FM1R_FBM8   0x0100U
 
#define CAN_FM1R_FBM9   0x0200U
 
#define CAN_FM1R_FBM10   0x0400U
 
#define CAN_FM1R_FBM11   0x0800U
 
#define CAN_FM1R_FBM12   0x1000U
 
#define CAN_FM1R_FBM13   0x2000U
 
#define CAN_FS1R_FSC   0x00003FFFU
 
#define CAN_FS1R_FSC0   0x00000001U
 
#define CAN_FS1R_FSC1   0x00000002U
 
#define CAN_FS1R_FSC2   0x00000004U
 
#define CAN_FS1R_FSC3   0x00000008U
 
#define CAN_FS1R_FSC4   0x00000010U
 
#define CAN_FS1R_FSC5   0x00000020U
 
#define CAN_FS1R_FSC6   0x00000040U
 
#define CAN_FS1R_FSC7   0x00000080U
 
#define CAN_FS1R_FSC8   0x00000100U
 
#define CAN_FS1R_FSC9   0x00000200U
 
#define CAN_FS1R_FSC10   0x00000400U
 
#define CAN_FS1R_FSC11   0x00000800U
 
#define CAN_FS1R_FSC12   0x00001000U
 
#define CAN_FS1R_FSC13   0x00002000U
 
#define CAN_FFA1R_FFA   0x00003FFFU
 
#define CAN_FFA1R_FFA0   0x00000001U
 
#define CAN_FFA1R_FFA1   0x00000002U
 
#define CAN_FFA1R_FFA2   0x00000004U
 
#define CAN_FFA1R_FFA3   0x00000008U
 
#define CAN_FFA1R_FFA4   0x00000010U
 
#define CAN_FFA1R_FFA5   0x00000020U
 
#define CAN_FFA1R_FFA6   0x00000040U
 
#define CAN_FFA1R_FFA7   0x00000080U
 
#define CAN_FFA1R_FFA8   0x00000100U
 
#define CAN_FFA1R_FFA9   0x00000200U
 
#define CAN_FFA1R_FFA10   0x00000400U
 
#define CAN_FFA1R_FFA11   0x00000800U
 
#define CAN_FFA1R_FFA12   0x00001000U
 
#define CAN_FFA1R_FFA13   0x00002000U
 
#define CAN_FA1R_FACT   0x00003FFFU
 
#define CAN_FA1R_FACT0   0x00000001U
 
#define CAN_FA1R_FACT1   0x00000002U
 
#define CAN_FA1R_FACT2   0x00000004U
 
#define CAN_FA1R_FACT3   0x00000008U
 
#define CAN_FA1R_FACT4   0x00000010U
 
#define CAN_FA1R_FACT5   0x00000020U
 
#define CAN_FA1R_FACT6   0x00000040U
 
#define CAN_FA1R_FACT7   0x00000080U
 
#define CAN_FA1R_FACT8   0x00000100U
 
#define CAN_FA1R_FACT9   0x00000200U
 
#define CAN_FA1R_FACT10   0x00000400U
 
#define CAN_FA1R_FACT11   0x00000800U
 
#define CAN_FA1R_FACT12   0x00001000U
 
#define CAN_FA1R_FACT13   0x00002000U
 
#define CAN_F0R1_FB0   0x00000001U
 
#define CAN_F0R1_FB1   0x00000002U
 
#define CAN_F0R1_FB2   0x00000004U
 
#define CAN_F0R1_FB3   0x00000008U
 
#define CAN_F0R1_FB4   0x00000010U
 
#define CAN_F0R1_FB5   0x00000020U
 
#define CAN_F0R1_FB6   0x00000040U
 
#define CAN_F0R1_FB7   0x00000080U
 
#define CAN_F0R1_FB8   0x00000100U
 
#define CAN_F0R1_FB9   0x00000200U
 
#define CAN_F0R1_FB10   0x00000400U
 
#define CAN_F0R1_FB11   0x00000800U
 
#define CAN_F0R1_FB12   0x00001000U
 
#define CAN_F0R1_FB13   0x00002000U
 
#define CAN_F0R1_FB14   0x00004000U
 
#define CAN_F0R1_FB15   0x00008000U
 
#define CAN_F0R1_FB16   0x00010000U
 
#define CAN_F0R1_FB17   0x00020000U
 
#define CAN_F0R1_FB18   0x00040000U
 
#define CAN_F0R1_FB19   0x00080000U
 
#define CAN_F0R1_FB20   0x00100000U
 
#define CAN_F0R1_FB21   0x00200000U
 
#define CAN_F0R1_FB22   0x00400000U
 
#define CAN_F0R1_FB23   0x00800000U
 
#define CAN_F0R1_FB24   0x01000000U
 
#define CAN_F0R1_FB25   0x02000000U
 
#define CAN_F0R1_FB26   0x04000000U
 
#define CAN_F0R1_FB27   0x08000000U
 
#define CAN_F0R1_FB28   0x10000000U
 
#define CAN_F0R1_FB29   0x20000000U
 
#define CAN_F0R1_FB30   0x40000000U
 
#define CAN_F0R1_FB31   0x80000000U
 
#define CAN_F1R1_FB0   0x00000001U
 
#define CAN_F1R1_FB1   0x00000002U
 
#define CAN_F1R1_FB2   0x00000004U
 
#define CAN_F1R1_FB3   0x00000008U
 
#define CAN_F1R1_FB4   0x00000010U
 
#define CAN_F1R1_FB5   0x00000020U
 
#define CAN_F1R1_FB6   0x00000040U
 
#define CAN_F1R1_FB7   0x00000080U
 
#define CAN_F1R1_FB8   0x00000100U
 
#define CAN_F1R1_FB9   0x00000200U
 
#define CAN_F1R1_FB10   0x00000400U
 
#define CAN_F1R1_FB11   0x00000800U
 
#define CAN_F1R1_FB12   0x00001000U
 
#define CAN_F1R1_FB13   0x00002000U
 
#define CAN_F1R1_FB14   0x00004000U
 
#define CAN_F1R1_FB15   0x00008000U
 
#define CAN_F1R1_FB16   0x00010000U
 
#define CAN_F1R1_FB17   0x00020000U
 
#define CAN_F1R1_FB18   0x00040000U
 
#define CAN_F1R1_FB19   0x00080000U
 
#define CAN_F1R1_FB20   0x00100000U
 
#define CAN_F1R1_FB21   0x00200000U
 
#define CAN_F1R1_FB22   0x00400000U
 
#define CAN_F1R1_FB23   0x00800000U
 
#define CAN_F1R1_FB24   0x01000000U
 
#define CAN_F1R1_FB25   0x02000000U
 
#define CAN_F1R1_FB26   0x04000000U
 
#define CAN_F1R1_FB27   0x08000000U
 
#define CAN_F1R1_FB28   0x10000000U
 
#define CAN_F1R1_FB29   0x20000000U
 
#define CAN_F1R1_FB30   0x40000000U
 
#define CAN_F1R1_FB31   0x80000000U
 
#define CAN_F2R1_FB0   0x00000001U
 
#define CAN_F2R1_FB1   0x00000002U
 
#define CAN_F2R1_FB2   0x00000004U
 
#define CAN_F2R1_FB3   0x00000008U
 
#define CAN_F2R1_FB4   0x00000010U
 
#define CAN_F2R1_FB5   0x00000020U
 
#define CAN_F2R1_FB6   0x00000040U
 
#define CAN_F2R1_FB7   0x00000080U
 
#define CAN_F2R1_FB8   0x00000100U
 
#define CAN_F2R1_FB9   0x00000200U
 
#define CAN_F2R1_FB10   0x00000400U
 
#define CAN_F2R1_FB11   0x00000800U
 
#define CAN_F2R1_FB12   0x00001000U
 
#define CAN_F2R1_FB13   0x00002000U
 
#define CAN_F2R1_FB14   0x00004000U
 
#define CAN_F2R1_FB15   0x00008000U
 
#define CAN_F2R1_FB16   0x00010000U
 
#define CAN_F2R1_FB17   0x00020000U
 
#define CAN_F2R1_FB18   0x00040000U
 
#define CAN_F2R1_FB19   0x00080000U
 
#define CAN_F2R1_FB20   0x00100000U
 
#define CAN_F2R1_FB21   0x00200000U
 
#define CAN_F2R1_FB22   0x00400000U
 
#define CAN_F2R1_FB23   0x00800000U
 
#define CAN_F2R1_FB24   0x01000000U
 
#define CAN_F2R1_FB25   0x02000000U
 
#define CAN_F2R1_FB26   0x04000000U
 
#define CAN_F2R1_FB27   0x08000000U
 
#define CAN_F2R1_FB28   0x10000000U
 
#define CAN_F2R1_FB29   0x20000000U
 
#define CAN_F2R1_FB30   0x40000000U
 
#define CAN_F2R1_FB31   0x80000000U
 
#define CAN_F3R1_FB0   0x00000001U
 
#define CAN_F3R1_FB1   0x00000002U
 
#define CAN_F3R1_FB2   0x00000004U
 
#define CAN_F3R1_FB3   0x00000008U
 
#define CAN_F3R1_FB4   0x00000010U
 
#define CAN_F3R1_FB5   0x00000020U
 
#define CAN_F3R1_FB6   0x00000040U
 
#define CAN_F3R1_FB7   0x00000080U
 
#define CAN_F3R1_FB8   0x00000100U
 
#define CAN_F3R1_FB9   0x00000200U
 
#define CAN_F3R1_FB10   0x00000400U
 
#define CAN_F3R1_FB11   0x00000800U
 
#define CAN_F3R1_FB12   0x00001000U
 
#define CAN_F3R1_FB13   0x00002000U
 
#define CAN_F3R1_FB14   0x00004000U
 
#define CAN_F3R1_FB15   0x00008000U
 
#define CAN_F3R1_FB16   0x00010000U
 
#define CAN_F3R1_FB17   0x00020000U
 
#define CAN_F3R1_FB18   0x00040000U
 
#define CAN_F3R1_FB19   0x00080000U
 
#define CAN_F3R1_FB20   0x00100000U
 
#define CAN_F3R1_FB21   0x00200000U
 
#define CAN_F3R1_FB22   0x00400000U
 
#define CAN_F3R1_FB23   0x00800000U
 
#define CAN_F3R1_FB24   0x01000000U
 
#define CAN_F3R1_FB25   0x02000000U
 
#define CAN_F3R1_FB26   0x04000000U
 
#define CAN_F3R1_FB27   0x08000000U
 
#define CAN_F3R1_FB28   0x10000000U
 
#define CAN_F3R1_FB29   0x20000000U
 
#define CAN_F3R1_FB30   0x40000000U
 
#define CAN_F3R1_FB31   0x80000000U
 
#define CAN_F4R1_FB0   0x00000001U
 
#define CAN_F4R1_FB1   0x00000002U
 
#define CAN_F4R1_FB2   0x00000004U
 
#define CAN_F4R1_FB3   0x00000008U
 
#define CAN_F4R1_FB4   0x00000010U
 
#define CAN_F4R1_FB5   0x00000020U
 
#define CAN_F4R1_FB6   0x00000040U
 
#define CAN_F4R1_FB7   0x00000080U
 
#define CAN_F4R1_FB8   0x00000100U
 
#define CAN_F4R1_FB9   0x00000200U
 
#define CAN_F4R1_FB10   0x00000400U
 
#define CAN_F4R1_FB11   0x00000800U
 
#define CAN_F4R1_FB12   0x00001000U
 
#define CAN_F4R1_FB13   0x00002000U
 
#define CAN_F4R1_FB14   0x00004000U
 
#define CAN_F4R1_FB15   0x00008000U
 
#define CAN_F4R1_FB16   0x00010000U
 
#define CAN_F4R1_FB17   0x00020000U
 
#define CAN_F4R1_FB18   0x00040000U
 
#define CAN_F4R1_FB19   0x00080000U
 
#define CAN_F4R1_FB20   0x00100000U
 
#define CAN_F4R1_FB21   0x00200000U
 
#define CAN_F4R1_FB22   0x00400000U
 
#define CAN_F4R1_FB23   0x00800000U
 
#define CAN_F4R1_FB24   0x01000000U
 
#define CAN_F4R1_FB25   0x02000000U
 
#define CAN_F4R1_FB26   0x04000000U
 
#define CAN_F4R1_FB27   0x08000000U
 
#define CAN_F4R1_FB28   0x10000000U
 
#define CAN_F4R1_FB29   0x20000000U
 
#define CAN_F4R1_FB30   0x40000000U
 
#define CAN_F4R1_FB31   0x80000000U
 
#define CAN_F5R1_FB0   0x00000001U
 
#define CAN_F5R1_FB1   0x00000002U
 
#define CAN_F5R1_FB2   0x00000004U
 
#define CAN_F5R1_FB3   0x00000008U
 
#define CAN_F5R1_FB4   0x00000010U
 
#define CAN_F5R1_FB5   0x00000020U
 
#define CAN_F5R1_FB6   0x00000040U
 
#define CAN_F5R1_FB7   0x00000080U
 
#define CAN_F5R1_FB8   0x00000100U
 
#define CAN_F5R1_FB9   0x00000200U
 
#define CAN_F5R1_FB10   0x00000400U
 
#define CAN_F5R1_FB11   0x00000800U
 
#define CAN_F5R1_FB12   0x00001000U
 
#define CAN_F5R1_FB13   0x00002000U
 
#define CAN_F5R1_FB14   0x00004000U
 
#define CAN_F5R1_FB15   0x00008000U
 
#define CAN_F5R1_FB16   0x00010000U
 
#define CAN_F5R1_FB17   0x00020000U
 
#define CAN_F5R1_FB18   0x00040000U
 
#define CAN_F5R1_FB19   0x00080000U
 
#define CAN_F5R1_FB20   0x00100000U
 
#define CAN_F5R1_FB21   0x00200000U
 
#define CAN_F5R1_FB22   0x00400000U
 
#define CAN_F5R1_FB23   0x00800000U
 
#define CAN_F5R1_FB24   0x01000000U
 
#define CAN_F5R1_FB25   0x02000000U
 
#define CAN_F5R1_FB26   0x04000000U
 
#define CAN_F5R1_FB27   0x08000000U
 
#define CAN_F5R1_FB28   0x10000000U
 
#define CAN_F5R1_FB29   0x20000000U
 
#define CAN_F5R1_FB30   0x40000000U
 
#define CAN_F5R1_FB31   0x80000000U
 
#define CAN_F6R1_FB0   0x00000001U
 
#define CAN_F6R1_FB1   0x00000002U
 
#define CAN_F6R1_FB2   0x00000004U
 
#define CAN_F6R1_FB3   0x00000008U
 
#define CAN_F6R1_FB4   0x00000010U
 
#define CAN_F6R1_FB5   0x00000020U
 
#define CAN_F6R1_FB6   0x00000040U
 
#define CAN_F6R1_FB7   0x00000080U
 
#define CAN_F6R1_FB8   0x00000100U
 
#define CAN_F6R1_FB9   0x00000200U
 
#define CAN_F6R1_FB10   0x00000400U
 
#define CAN_F6R1_FB11   0x00000800U
 
#define CAN_F6R1_FB12   0x00001000U
 
#define CAN_F6R1_FB13   0x00002000U
 
#define CAN_F6R1_FB14   0x00004000U
 
#define CAN_F6R1_FB15   0x00008000U
 
#define CAN_F6R1_FB16   0x00010000U
 
#define CAN_F6R1_FB17   0x00020000U
 
#define CAN_F6R1_FB18   0x00040000U
 
#define CAN_F6R1_FB19   0x00080000U
 
#define CAN_F6R1_FB20   0x00100000U
 
#define CAN_F6R1_FB21   0x00200000U
 
#define CAN_F6R1_FB22   0x00400000U
 
#define CAN_F6R1_FB23   0x00800000U
 
#define CAN_F6R1_FB24   0x01000000U
 
#define CAN_F6R1_FB25   0x02000000U
 
#define CAN_F6R1_FB26   0x04000000U
 
#define CAN_F6R1_FB27   0x08000000U
 
#define CAN_F6R1_FB28   0x10000000U
 
#define CAN_F6R1_FB29   0x20000000U
 
#define CAN_F6R1_FB30   0x40000000U
 
#define CAN_F6R1_FB31   0x80000000U
 
#define CAN_F7R1_FB0   0x00000001U
 
#define CAN_F7R1_FB1   0x00000002U
 
#define CAN_F7R1_FB2   0x00000004U
 
#define CAN_F7R1_FB3   0x00000008U
 
#define CAN_F7R1_FB4   0x00000010U
 
#define CAN_F7R1_FB5   0x00000020U
 
#define CAN_F7R1_FB6   0x00000040U
 
#define CAN_F7R1_FB7   0x00000080U
 
#define CAN_F7R1_FB8   0x00000100U
 
#define CAN_F7R1_FB9   0x00000200U
 
#define CAN_F7R1_FB10   0x00000400U
 
#define CAN_F7R1_FB11   0x00000800U
 
#define CAN_F7R1_FB12   0x00001000U
 
#define CAN_F7R1_FB13   0x00002000U
 
#define CAN_F7R1_FB14   0x00004000U
 
#define CAN_F7R1_FB15   0x00008000U
 
#define CAN_F7R1_FB16   0x00010000U
 
#define CAN_F7R1_FB17   0x00020000U
 
#define CAN_F7R1_FB18   0x00040000U
 
#define CAN_F7R1_FB19   0x00080000U
 
#define CAN_F7R1_FB20   0x00100000U
 
#define CAN_F7R1_FB21   0x00200000U
 
#define CAN_F7R1_FB22   0x00400000U
 
#define CAN_F7R1_FB23   0x00800000U
 
#define CAN_F7R1_FB24   0x01000000U
 
#define CAN_F7R1_FB25   0x02000000U
 
#define CAN_F7R1_FB26   0x04000000U
 
#define CAN_F7R1_FB27   0x08000000U
 
#define CAN_F7R1_FB28   0x10000000U
 
#define CAN_F7R1_FB29   0x20000000U
 
#define CAN_F7R1_FB30   0x40000000U
 
#define CAN_F7R1_FB31   0x80000000U
 
#define CAN_F8R1_FB0   0x00000001U
 
#define CAN_F8R1_FB1   0x00000002U
 
#define CAN_F8R1_FB2   0x00000004U
 
#define CAN_F8R1_FB3   0x00000008U
 
#define CAN_F8R1_FB4   0x00000010U
 
#define CAN_F8R1_FB5   0x00000020U
 
#define CAN_F8R1_FB6   0x00000040U
 
#define CAN_F8R1_FB7   0x00000080U
 
#define CAN_F8R1_FB8   0x00000100U
 
#define CAN_F8R1_FB9   0x00000200U
 
#define CAN_F8R1_FB10   0x00000400U
 
#define CAN_F8R1_FB11   0x00000800U
 
#define CAN_F8R1_FB12   0x00001000U
 
#define CAN_F8R1_FB13   0x00002000U
 
#define CAN_F8R1_FB14   0x00004000U
 
#define CAN_F8R1_FB15   0x00008000U
 
#define CAN_F8R1_FB16   0x00010000U
 
#define CAN_F8R1_FB17   0x00020000U
 
#define CAN_F8R1_FB18   0x00040000U
 
#define CAN_F8R1_FB19   0x00080000U
 
#define CAN_F8R1_FB20   0x00100000U
 
#define CAN_F8R1_FB21   0x00200000U
 
#define CAN_F8R1_FB22   0x00400000U
 
#define CAN_F8R1_FB23   0x00800000U
 
#define CAN_F8R1_FB24   0x01000000U
 
#define CAN_F8R1_FB25   0x02000000U
 
#define CAN_F8R1_FB26   0x04000000U
 
#define CAN_F8R1_FB27   0x08000000U
 
#define CAN_F8R1_FB28   0x10000000U
 
#define CAN_F8R1_FB29   0x20000000U
 
#define CAN_F8R1_FB30   0x40000000U
 
#define CAN_F8R1_FB31   0x80000000U
 
#define CAN_F9R1_FB0   0x00000001U
 
#define CAN_F9R1_FB1   0x00000002U
 
#define CAN_F9R1_FB2   0x00000004U
 
#define CAN_F9R1_FB3   0x00000008U
 
#define CAN_F9R1_FB4   0x00000010U
 
#define CAN_F9R1_FB5   0x00000020U
 
#define CAN_F9R1_FB6   0x00000040U
 
#define CAN_F9R1_FB7   0x00000080U
 
#define CAN_F9R1_FB8   0x00000100U
 
#define CAN_F9R1_FB9   0x00000200U
 
#define CAN_F9R1_FB10   0x00000400U
 
#define CAN_F9R1_FB11   0x00000800U
 
#define CAN_F9R1_FB12   0x00001000U
 
#define CAN_F9R1_FB13   0x00002000U
 
#define CAN_F9R1_FB14   0x00004000U
 
#define CAN_F9R1_FB15   0x00008000U
 
#define CAN_F9R1_FB16   0x00010000U
 
#define CAN_F9R1_FB17   0x00020000U
 
#define CAN_F9R1_FB18   0x00040000U
 
#define CAN_F9R1_FB19   0x00080000U
 
#define CAN_F9R1_FB20   0x00100000U
 
#define CAN_F9R1_FB21   0x00200000U
 
#define CAN_F9R1_FB22   0x00400000U
 
#define CAN_F9R1_FB23   0x00800000U
 
#define CAN_F9R1_FB24   0x01000000U
 
#define CAN_F9R1_FB25   0x02000000U
 
#define CAN_F9R1_FB26   0x04000000U
 
#define CAN_F9R1_FB27   0x08000000U
 
#define CAN_F9R1_FB28   0x10000000U
 
#define CAN_F9R1_FB29   0x20000000U
 
#define CAN_F9R1_FB30   0x40000000U
 
#define CAN_F9R1_FB31   0x80000000U
 
#define CAN_F10R1_FB0   0x00000001U
 
#define CAN_F10R1_FB1   0x00000002U
 
#define CAN_F10R1_FB2   0x00000004U
 
#define CAN_F10R1_FB3   0x00000008U
 
#define CAN_F10R1_FB4   0x00000010U
 
#define CAN_F10R1_FB5   0x00000020U
 
#define CAN_F10R1_FB6   0x00000040U
 
#define CAN_F10R1_FB7   0x00000080U
 
#define CAN_F10R1_FB8   0x00000100U
 
#define CAN_F10R1_FB9   0x00000200U
 
#define CAN_F10R1_FB10   0x00000400U
 
#define CAN_F10R1_FB11   0x00000800U
 
#define CAN_F10R1_FB12   0x00001000U
 
#define CAN_F10R1_FB13   0x00002000U
 
#define CAN_F10R1_FB14   0x00004000U
 
#define CAN_F10R1_FB15   0x00008000U
 
#define CAN_F10R1_FB16   0x00010000U
 
#define CAN_F10R1_FB17   0x00020000U
 
#define CAN_F10R1_FB18   0x00040000U
 
#define CAN_F10R1_FB19   0x00080000U
 
#define CAN_F10R1_FB20   0x00100000U
 
#define CAN_F10R1_FB21   0x00200000U
 
#define CAN_F10R1_FB22   0x00400000U
 
#define CAN_F10R1_FB23   0x00800000U
 
#define CAN_F10R1_FB24   0x01000000U
 
#define CAN_F10R1_FB25   0x02000000U
 
#define CAN_F10R1_FB26   0x04000000U
 
#define CAN_F10R1_FB27   0x08000000U
 
#define CAN_F10R1_FB28   0x10000000U
 
#define CAN_F10R1_FB29   0x20000000U
 
#define CAN_F10R1_FB30   0x40000000U
 
#define CAN_F10R1_FB31   0x80000000U
 
#define CAN_F11R1_FB0   0x00000001U
 
#define CAN_F11R1_FB1   0x00000002U
 
#define CAN_F11R1_FB2   0x00000004U
 
#define CAN_F11R1_FB3   0x00000008U
 
#define CAN_F11R1_FB4   0x00000010U
 
#define CAN_F11R1_FB5   0x00000020U
 
#define CAN_F11R1_FB6   0x00000040U
 
#define CAN_F11R1_FB7   0x00000080U
 
#define CAN_F11R1_FB8   0x00000100U
 
#define CAN_F11R1_FB9   0x00000200U
 
#define CAN_F11R1_FB10   0x00000400U
 
#define CAN_F11R1_FB11   0x00000800U
 
#define CAN_F11R1_FB12   0x00001000U
 
#define CAN_F11R1_FB13   0x00002000U
 
#define CAN_F11R1_FB14   0x00004000U
 
#define CAN_F11R1_FB15   0x00008000U
 
#define CAN_F11R1_FB16   0x00010000U
 
#define CAN_F11R1_FB17   0x00020000U
 
#define CAN_F11R1_FB18   0x00040000U
 
#define CAN_F11R1_FB19   0x00080000U
 
#define CAN_F11R1_FB20   0x00100000U
 
#define CAN_F11R1_FB21   0x00200000U
 
#define CAN_F11R1_FB22   0x00400000U
 
#define CAN_F11R1_FB23   0x00800000U
 
#define CAN_F11R1_FB24   0x01000000U
 
#define CAN_F11R1_FB25   0x02000000U
 
#define CAN_F11R1_FB26   0x04000000U
 
#define CAN_F11R1_FB27   0x08000000U
 
#define CAN_F11R1_FB28   0x10000000U
 
#define CAN_F11R1_FB29   0x20000000U
 
#define CAN_F11R1_FB30   0x40000000U
 
#define CAN_F11R1_FB31   0x80000000U
 
#define CAN_F12R1_FB0   0x00000001U
 
#define CAN_F12R1_FB1   0x00000002U
 
#define CAN_F12R1_FB2   0x00000004U
 
#define CAN_F12R1_FB3   0x00000008U
 
#define CAN_F12R1_FB4   0x00000010U
 
#define CAN_F12R1_FB5   0x00000020U
 
#define CAN_F12R1_FB6   0x00000040U
 
#define CAN_F12R1_FB7   0x00000080U
 
#define CAN_F12R1_FB8   0x00000100U
 
#define CAN_F12R1_FB9   0x00000200U
 
#define CAN_F12R1_FB10   0x00000400U
 
#define CAN_F12R1_FB11   0x00000800U
 
#define CAN_F12R1_FB12   0x00001000U
 
#define CAN_F12R1_FB13   0x00002000U
 
#define CAN_F12R1_FB14   0x00004000U
 
#define CAN_F12R1_FB15   0x00008000U
 
#define CAN_F12R1_FB16   0x00010000U
 
#define CAN_F12R1_FB17   0x00020000U
 
#define CAN_F12R1_FB18   0x00040000U
 
#define CAN_F12R1_FB19   0x00080000U
 
#define CAN_F12R1_FB20   0x00100000U
 
#define CAN_F12R1_FB21   0x00200000U
 
#define CAN_F12R1_FB22   0x00400000U
 
#define CAN_F12R1_FB23   0x00800000U
 
#define CAN_F12R1_FB24   0x01000000U
 
#define CAN_F12R1_FB25   0x02000000U
 
#define CAN_F12R1_FB26   0x04000000U
 
#define CAN_F12R1_FB27   0x08000000U
 
#define CAN_F12R1_FB28   0x10000000U
 
#define CAN_F12R1_FB29   0x20000000U
 
#define CAN_F12R1_FB30   0x40000000U
 
#define CAN_F12R1_FB31   0x80000000U
 
#define CAN_F13R1_FB0   0x00000001U
 
#define CAN_F13R1_FB1   0x00000002U
 
#define CAN_F13R1_FB2   0x00000004U
 
#define CAN_F13R1_FB3   0x00000008U
 
#define CAN_F13R1_FB4   0x00000010U
 
#define CAN_F13R1_FB5   0x00000020U
 
#define CAN_F13R1_FB6   0x00000040U
 
#define CAN_F13R1_FB7   0x00000080U
 
#define CAN_F13R1_FB8   0x00000100U
 
#define CAN_F13R1_FB9   0x00000200U
 
#define CAN_F13R1_FB10   0x00000400U
 
#define CAN_F13R1_FB11   0x00000800U
 
#define CAN_F13R1_FB12   0x00001000U
 
#define CAN_F13R1_FB13   0x00002000U
 
#define CAN_F13R1_FB14   0x00004000U
 
#define CAN_F13R1_FB15   0x00008000U
 
#define CAN_F13R1_FB16   0x00010000U
 
#define CAN_F13R1_FB17   0x00020000U
 
#define CAN_F13R1_FB18   0x00040000U
 
#define CAN_F13R1_FB19   0x00080000U
 
#define CAN_F13R1_FB20   0x00100000U
 
#define CAN_F13R1_FB21   0x00200000U
 
#define CAN_F13R1_FB22   0x00400000U
 
#define CAN_F13R1_FB23   0x00800000U
 
#define CAN_F13R1_FB24   0x01000000U
 
#define CAN_F13R1_FB25   0x02000000U
 
#define CAN_F13R1_FB26   0x04000000U
 
#define CAN_F13R1_FB27   0x08000000U
 
#define CAN_F13R1_FB28   0x10000000U
 
#define CAN_F13R1_FB29   0x20000000U
 
#define CAN_F13R1_FB30   0x40000000U
 
#define CAN_F13R1_FB31   0x80000000U
 
#define CAN_F0R2_FB0   0x00000001U
 
#define CAN_F0R2_FB1   0x00000002U
 
#define CAN_F0R2_FB2   0x00000004U
 
#define CAN_F0R2_FB3   0x00000008U
 
#define CAN_F0R2_FB4   0x00000010U
 
#define CAN_F0R2_FB5   0x00000020U
 
#define CAN_F0R2_FB6   0x00000040U
 
#define CAN_F0R2_FB7   0x00000080U
 
#define CAN_F0R2_FB8   0x00000100U
 
#define CAN_F0R2_FB9   0x00000200U
 
#define CAN_F0R2_FB10   0x00000400U
 
#define CAN_F0R2_FB11   0x00000800U
 
#define CAN_F0R2_FB12   0x00001000U
 
#define CAN_F0R2_FB13   0x00002000U
 
#define CAN_F0R2_FB14   0x00004000U
 
#define CAN_F0R2_FB15   0x00008000U
 
#define CAN_F0R2_FB16   0x00010000U
 
#define CAN_F0R2_FB17   0x00020000U
 
#define CAN_F0R2_FB18   0x00040000U
 
#define CAN_F0R2_FB19   0x00080000U
 
#define CAN_F0R2_FB20   0x00100000U
 
#define CAN_F0R2_FB21   0x00200000U
 
#define CAN_F0R2_FB22   0x00400000U
 
#define CAN_F0R2_FB23   0x00800000U
 
#define CAN_F0R2_FB24   0x01000000U
 
#define CAN_F0R2_FB25   0x02000000U
 
#define CAN_F0R2_FB26   0x04000000U
 
#define CAN_F0R2_FB27   0x08000000U
 
#define CAN_F0R2_FB28   0x10000000U
 
#define CAN_F0R2_FB29   0x20000000U
 
#define CAN_F0R2_FB30   0x40000000U
 
#define CAN_F0R2_FB31   0x80000000U
 
#define CAN_F1R2_FB0   0x00000001U
 
#define CAN_F1R2_FB1   0x00000002U
 
#define CAN_F1R2_FB2   0x00000004U
 
#define CAN_F1R2_FB3   0x00000008U
 
#define CAN_F1R2_FB4   0x00000010U
 
#define CAN_F1R2_FB5   0x00000020U
 
#define CAN_F1R2_FB6   0x00000040U
 
#define CAN_F1R2_FB7   0x00000080U
 
#define CAN_F1R2_FB8   0x00000100U
 
#define CAN_F1R2_FB9   0x00000200U
 
#define CAN_F1R2_FB10   0x00000400U
 
#define CAN_F1R2_FB11   0x00000800U
 
#define CAN_F1R2_FB12   0x00001000U
 
#define CAN_F1R2_FB13   0x00002000U
 
#define CAN_F1R2_FB14   0x00004000U
 
#define CAN_F1R2_FB15   0x00008000U
 
#define CAN_F1R2_FB16   0x00010000U
 
#define CAN_F1R2_FB17   0x00020000U
 
#define CAN_F1R2_FB18   0x00040000U
 
#define CAN_F1R2_FB19   0x00080000U
 
#define CAN_F1R2_FB20   0x00100000U
 
#define CAN_F1R2_FB21   0x00200000U
 
#define CAN_F1R2_FB22   0x00400000U
 
#define CAN_F1R2_FB23   0x00800000U
 
#define CAN_F1R2_FB24   0x01000000U
 
#define CAN_F1R2_FB25   0x02000000U
 
#define CAN_F1R2_FB26   0x04000000U
 
#define CAN_F1R2_FB27   0x08000000U
 
#define CAN_F1R2_FB28   0x10000000U
 
#define CAN_F1R2_FB29   0x20000000U
 
#define CAN_F1R2_FB30   0x40000000U
 
#define CAN_F1R2_FB31   0x80000000U
 
#define CAN_F2R2_FB0   0x00000001U
 
#define CAN_F2R2_FB1   0x00000002U
 
#define CAN_F2R2_FB2   0x00000004U
 
#define CAN_F2R2_FB3   0x00000008U
 
#define CAN_F2R2_FB4   0x00000010U
 
#define CAN_F2R2_FB5   0x00000020U
 
#define CAN_F2R2_FB6   0x00000040U
 
#define CAN_F2R2_FB7   0x00000080U
 
#define CAN_F2R2_FB8   0x00000100U
 
#define CAN_F2R2_FB9   0x00000200U
 
#define CAN_F2R2_FB10   0x00000400U
 
#define CAN_F2R2_FB11   0x00000800U
 
#define CAN_F2R2_FB12   0x00001000U
 
#define CAN_F2R2_FB13   0x00002000U
 
#define CAN_F2R2_FB14   0x00004000U
 
#define CAN_F2R2_FB15   0x00008000U
 
#define CAN_F2R2_FB16   0x00010000U
 
#define CAN_F2R2_FB17   0x00020000U
 
#define CAN_F2R2_FB18   0x00040000U
 
#define CAN_F2R2_FB19   0x00080000U
 
#define CAN_F2R2_FB20   0x00100000U
 
#define CAN_F2R2_FB21   0x00200000U
 
#define CAN_F2R2_FB22   0x00400000U
 
#define CAN_F2R2_FB23   0x00800000U
 
#define CAN_F2R2_FB24   0x01000000U
 
#define CAN_F2R2_FB25   0x02000000U
 
#define CAN_F2R2_FB26   0x04000000U
 
#define CAN_F2R2_FB27   0x08000000U
 
#define CAN_F2R2_FB28   0x10000000U
 
#define CAN_F2R2_FB29   0x20000000U
 
#define CAN_F2R2_FB30   0x40000000U
 
#define CAN_F2R2_FB31   0x80000000U
 
#define CAN_F3R2_FB0   0x00000001U
 
#define CAN_F3R2_FB1   0x00000002U
 
#define CAN_F3R2_FB2   0x00000004U
 
#define CAN_F3R2_FB3   0x00000008U
 
#define CAN_F3R2_FB4   0x00000010U
 
#define CAN_F3R2_FB5   0x00000020U
 
#define CAN_F3R2_FB6   0x00000040U
 
#define CAN_F3R2_FB7   0x00000080U
 
#define CAN_F3R2_FB8   0x00000100U
 
#define CAN_F3R2_FB9   0x00000200U
 
#define CAN_F3R2_FB10   0x00000400U
 
#define CAN_F3R2_FB11   0x00000800U
 
#define CAN_F3R2_FB12   0x00001000U
 
#define CAN_F3R2_FB13   0x00002000U
 
#define CAN_F3R2_FB14   0x00004000U
 
#define CAN_F3R2_FB15   0x00008000U
 
#define CAN_F3R2_FB16   0x00010000U
 
#define CAN_F3R2_FB17   0x00020000U
 
#define CAN_F3R2_FB18   0x00040000U
 
#define CAN_F3R2_FB19   0x00080000U
 
#define CAN_F3R2_FB20   0x00100000U
 
#define CAN_F3R2_FB21   0x00200000U
 
#define CAN_F3R2_FB22   0x00400000U
 
#define CAN_F3R2_FB23   0x00800000U
 
#define CAN_F3R2_FB24   0x01000000U
 
#define CAN_F3R2_FB25   0x02000000U
 
#define CAN_F3R2_FB26   0x04000000U
 
#define CAN_F3R2_FB27   0x08000000U
 
#define CAN_F3R2_FB28   0x10000000U
 
#define CAN_F3R2_FB29   0x20000000U
 
#define CAN_F3R2_FB30   0x40000000U
 
#define CAN_F3R2_FB31   0x80000000U
 
#define CAN_F4R2_FB0   0x00000001U
 
#define CAN_F4R2_FB1   0x00000002U
 
#define CAN_F4R2_FB2   0x00000004U
 
#define CAN_F4R2_FB3   0x00000008U
 
#define CAN_F4R2_FB4   0x00000010U
 
#define CAN_F4R2_FB5   0x00000020U
 
#define CAN_F4R2_FB6   0x00000040U
 
#define CAN_F4R2_FB7   0x00000080U
 
#define CAN_F4R2_FB8   0x00000100U
 
#define CAN_F4R2_FB9   0x00000200U
 
#define CAN_F4R2_FB10   0x00000400U
 
#define CAN_F4R2_FB11   0x00000800U
 
#define CAN_F4R2_FB12   0x00001000U
 
#define CAN_F4R2_FB13   0x00002000U
 
#define CAN_F4R2_FB14   0x00004000U
 
#define CAN_F4R2_FB15   0x00008000U
 
#define CAN_F4R2_FB16   0x00010000U
 
#define CAN_F4R2_FB17   0x00020000U
 
#define CAN_F4R2_FB18   0x00040000U
 
#define CAN_F4R2_FB19   0x00080000U
 
#define CAN_F4R2_FB20   0x00100000U
 
#define CAN_F4R2_FB21   0x00200000U
 
#define CAN_F4R2_FB22   0x00400000U
 
#define CAN_F4R2_FB23   0x00800000U
 
#define CAN_F4R2_FB24   0x01000000U
 
#define CAN_F4R2_FB25   0x02000000U
 
#define CAN_F4R2_FB26   0x04000000U
 
#define CAN_F4R2_FB27   0x08000000U
 
#define CAN_F4R2_FB28   0x10000000U
 
#define CAN_F4R2_FB29   0x20000000U
 
#define CAN_F4R2_FB30   0x40000000U
 
#define CAN_F4R2_FB31   0x80000000U
 
#define CAN_F5R2_FB0   0x00000001U
 
#define CAN_F5R2_FB1   0x00000002U
 
#define CAN_F5R2_FB2   0x00000004U
 
#define CAN_F5R2_FB3   0x00000008U
 
#define CAN_F5R2_FB4   0x00000010U
 
#define CAN_F5R2_FB5   0x00000020U
 
#define CAN_F5R2_FB6   0x00000040U
 
#define CAN_F5R2_FB7   0x00000080U
 
#define CAN_F5R2_FB8   0x00000100U
 
#define CAN_F5R2_FB9   0x00000200U
 
#define CAN_F5R2_FB10   0x00000400U
 
#define CAN_F5R2_FB11   0x00000800U
 
#define CAN_F5R2_FB12   0x00001000U
 
#define CAN_F5R2_FB13   0x00002000U
 
#define CAN_F5R2_FB14   0x00004000U
 
#define CAN_F5R2_FB15   0x00008000U
 
#define CAN_F5R2_FB16   0x00010000U
 
#define CAN_F5R2_FB17   0x00020000U
 
#define CAN_F5R2_FB18   0x00040000U
 
#define CAN_F5R2_FB19   0x00080000U
 
#define CAN_F5R2_FB20   0x00100000U
 
#define CAN_F5R2_FB21   0x00200000U
 
#define CAN_F5R2_FB22   0x00400000U
 
#define CAN_F5R2_FB23   0x00800000U
 
#define CAN_F5R2_FB24   0x01000000U
 
#define CAN_F5R2_FB25   0x02000000U
 
#define CAN_F5R2_FB26   0x04000000U
 
#define CAN_F5R2_FB27   0x08000000U
 
#define CAN_F5R2_FB28   0x10000000U
 
#define CAN_F5R2_FB29   0x20000000U
 
#define CAN_F5R2_FB30   0x40000000U
 
#define CAN_F5R2_FB31   0x80000000U
 
#define CAN_F6R2_FB0   0x00000001U
 
#define CAN_F6R2_FB1   0x00000002U
 
#define CAN_F6R2_FB2   0x00000004U
 
#define CAN_F6R2_FB3   0x00000008U
 
#define CAN_F6R2_FB4   0x00000010U
 
#define CAN_F6R2_FB5   0x00000020U
 
#define CAN_F6R2_FB6   0x00000040U
 
#define CAN_F6R2_FB7   0x00000080U
 
#define CAN_F6R2_FB8   0x00000100U
 
#define CAN_F6R2_FB9   0x00000200U
 
#define CAN_F6R2_FB10   0x00000400U
 
#define CAN_F6R2_FB11   0x00000800U
 
#define CAN_F6R2_FB12   0x00001000U
 
#define CAN_F6R2_FB13   0x00002000U
 
#define CAN_F6R2_FB14   0x00004000U
 
#define CAN_F6R2_FB15   0x00008000U
 
#define CAN_F6R2_FB16   0x00010000U
 
#define CAN_F6R2_FB17   0x00020000U
 
#define CAN_F6R2_FB18   0x00040000U
 
#define CAN_F6R2_FB19   0x00080000U
 
#define CAN_F6R2_FB20   0x00100000U
 
#define CAN_F6R2_FB21   0x00200000U
 
#define CAN_F6R2_FB22   0x00400000U
 
#define CAN_F6R2_FB23   0x00800000U
 
#define CAN_F6R2_FB24   0x01000000U
 
#define CAN_F6R2_FB25   0x02000000U
 
#define CAN_F6R2_FB26   0x04000000U
 
#define CAN_F6R2_FB27   0x08000000U
 
#define CAN_F6R2_FB28   0x10000000U
 
#define CAN_F6R2_FB29   0x20000000U
 
#define CAN_F6R2_FB30   0x40000000U
 
#define CAN_F6R2_FB31   0x80000000U
 
#define CAN_F7R2_FB0   0x00000001U
 
#define CAN_F7R2_FB1   0x00000002U
 
#define CAN_F7R2_FB2   0x00000004U
 
#define CAN_F7R2_FB3   0x00000008U
 
#define CAN_F7R2_FB4   0x00000010U
 
#define CAN_F7R2_FB5   0x00000020U
 
#define CAN_F7R2_FB6   0x00000040U
 
#define CAN_F7R2_FB7   0x00000080U
 
#define CAN_F7R2_FB8   0x00000100U
 
#define CAN_F7R2_FB9   0x00000200U
 
#define CAN_F7R2_FB10   0x00000400U
 
#define CAN_F7R2_FB11   0x00000800U
 
#define CAN_F7R2_FB12   0x00001000U
 
#define CAN_F7R2_FB13   0x00002000U
 
#define CAN_F7R2_FB14   0x00004000U
 
#define CAN_F7R2_FB15   0x00008000U
 
#define CAN_F7R2_FB16   0x00010000U
 
#define CAN_F7R2_FB17   0x00020000U
 
#define CAN_F7R2_FB18   0x00040000U
 
#define CAN_F7R2_FB19   0x00080000U
 
#define CAN_F7R2_FB20   0x00100000U
 
#define CAN_F7R2_FB21   0x00200000U
 
#define CAN_F7R2_FB22   0x00400000U
 
#define CAN_F7R2_FB23   0x00800000U
 
#define CAN_F7R2_FB24   0x01000000U
 
#define CAN_F7R2_FB25   0x02000000U
 
#define CAN_F7R2_FB26   0x04000000U
 
#define CAN_F7R2_FB27   0x08000000U
 
#define CAN_F7R2_FB28   0x10000000U
 
#define CAN_F7R2_FB29   0x20000000U
 
#define CAN_F7R2_FB30   0x40000000U
 
#define CAN_F7R2_FB31   0x80000000U
 
#define CAN_F8R2_FB0   0x00000001U
 
#define CAN_F8R2_FB1   0x00000002U
 
#define CAN_F8R2_FB2   0x00000004U
 
#define CAN_F8R2_FB3   0x00000008U
 
#define CAN_F8R2_FB4   0x00000010U
 
#define CAN_F8R2_FB5   0x00000020U
 
#define CAN_F8R2_FB6   0x00000040U
 
#define CAN_F8R2_FB7   0x00000080U
 
#define CAN_F8R2_FB8   0x00000100U
 
#define CAN_F8R2_FB9   0x00000200U
 
#define CAN_F8R2_FB10   0x00000400U
 
#define CAN_F8R2_FB11   0x00000800U
 
#define CAN_F8R2_FB12   0x00001000U
 
#define CAN_F8R2_FB13   0x00002000U
 
#define CAN_F8R2_FB14   0x00004000U
 
#define CAN_F8R2_FB15   0x00008000U
 
#define CAN_F8R2_FB16   0x00010000U
 
#define CAN_F8R2_FB17   0x00020000U
 
#define CAN_F8R2_FB18   0x00040000U
 
#define CAN_F8R2_FB19   0x00080000U
 
#define CAN_F8R2_FB20   0x00100000U
 
#define CAN_F8R2_FB21   0x00200000U
 
#define CAN_F8R2_FB22   0x00400000U
 
#define CAN_F8R2_FB23   0x00800000U
 
#define CAN_F8R2_FB24   0x01000000U
 
#define CAN_F8R2_FB25   0x02000000U
 
#define CAN_F8R2_FB26   0x04000000U
 
#define CAN_F8R2_FB27   0x08000000U
 
#define CAN_F8R2_FB28   0x10000000U
 
#define CAN_F8R2_FB29   0x20000000U
 
#define CAN_F8R2_FB30   0x40000000U
 
#define CAN_F8R2_FB31   0x80000000U
 
#define CAN_F9R2_FB0   0x00000001U
 
#define CAN_F9R2_FB1   0x00000002U
 
#define CAN_F9R2_FB2   0x00000004U
 
#define CAN_F9R2_FB3   0x00000008U
 
#define CAN_F9R2_FB4   0x00000010U
 
#define CAN_F9R2_FB5   0x00000020U
 
#define CAN_F9R2_FB6   0x00000040U
 
#define CAN_F9R2_FB7   0x00000080U
 
#define CAN_F9R2_FB8   0x00000100U
 
#define CAN_F9R2_FB9   0x00000200U
 
#define CAN_F9R2_FB10   0x00000400U
 
#define CAN_F9R2_FB11   0x00000800U
 
#define CAN_F9R2_FB12   0x00001000U
 
#define CAN_F9R2_FB13   0x00002000U
 
#define CAN_F9R2_FB14   0x00004000U
 
#define CAN_F9R2_FB15   0x00008000U
 
#define CAN_F9R2_FB16   0x00010000U
 
#define CAN_F9R2_FB17   0x00020000U
 
#define CAN_F9R2_FB18   0x00040000U
 
#define CAN_F9R2_FB19   0x00080000U
 
#define CAN_F9R2_FB20   0x00100000U
 
#define CAN_F9R2_FB21   0x00200000U
 
#define CAN_F9R2_FB22   0x00400000U
 
#define CAN_F9R2_FB23   0x00800000U
 
#define CAN_F9R2_FB24   0x01000000U
 
#define CAN_F9R2_FB25   0x02000000U
 
#define CAN_F9R2_FB26   0x04000000U
 
#define CAN_F9R2_FB27   0x08000000U
 
#define CAN_F9R2_FB28   0x10000000U
 
#define CAN_F9R2_FB29   0x20000000U
 
#define CAN_F9R2_FB30   0x40000000U
 
#define CAN_F9R2_FB31   0x80000000U
 
#define CAN_F10R2_FB0   0x00000001U
 
#define CAN_F10R2_FB1   0x00000002U
 
#define CAN_F10R2_FB2   0x00000004U
 
#define CAN_F10R2_FB3   0x00000008U
 
#define CAN_F10R2_FB4   0x00000010U
 
#define CAN_F10R2_FB5   0x00000020U
 
#define CAN_F10R2_FB6   0x00000040U
 
#define CAN_F10R2_FB7   0x00000080U
 
#define CAN_F10R2_FB8   0x00000100U
 
#define CAN_F10R2_FB9   0x00000200U
 
#define CAN_F10R2_FB10   0x00000400U
 
#define CAN_F10R2_FB11   0x00000800U
 
#define CAN_F10R2_FB12   0x00001000U
 
#define CAN_F10R2_FB13   0x00002000U
 
#define CAN_F10R2_FB14   0x00004000U
 
#define CAN_F10R2_FB15   0x00008000U
 
#define CAN_F10R2_FB16   0x00010000U
 
#define CAN_F10R2_FB17   0x00020000U
 
#define CAN_F10R2_FB18   0x00040000U
 
#define CAN_F10R2_FB19   0x00080000U
 
#define CAN_F10R2_FB20   0x00100000U
 
#define CAN_F10R2_FB21   0x00200000U
 
#define CAN_F10R2_FB22   0x00400000U
 
#define CAN_F10R2_FB23   0x00800000U
 
#define CAN_F10R2_FB24   0x01000000U
 
#define CAN_F10R2_FB25   0x02000000U
 
#define CAN_F10R2_FB26   0x04000000U
 
#define CAN_F10R2_FB27   0x08000000U
 
#define CAN_F10R2_FB28   0x10000000U
 
#define CAN_F10R2_FB29   0x20000000U
 
#define CAN_F10R2_FB30   0x40000000U
 
#define CAN_F10R2_FB31   0x80000000U
 
#define CAN_F11R2_FB0   0x00000001U
 
#define CAN_F11R2_FB1   0x00000002U
 
#define CAN_F11R2_FB2   0x00000004U
 
#define CAN_F11R2_FB3   0x00000008U
 
#define CAN_F11R2_FB4   0x00000010U
 
#define CAN_F11R2_FB5   0x00000020U
 
#define CAN_F11R2_FB6   0x00000040U
 
#define CAN_F11R2_FB7   0x00000080U
 
#define CAN_F11R2_FB8   0x00000100U
 
#define CAN_F11R2_FB9   0x00000200U
 
#define CAN_F11R2_FB10   0x00000400U
 
#define CAN_F11R2_FB11   0x00000800U
 
#define CAN_F11R2_FB12   0x00001000U
 
#define CAN_F11R2_FB13   0x00002000U
 
#define CAN_F11R2_FB14   0x00004000U
 
#define CAN_F11R2_FB15   0x00008000U
 
#define CAN_F11R2_FB16   0x00010000U
 
#define CAN_F11R2_FB17   0x00020000U
 
#define CAN_F11R2_FB18   0x00040000U
 
#define CAN_F11R2_FB19   0x00080000U
 
#define CAN_F11R2_FB20   0x00100000U
 
#define CAN_F11R2_FB21   0x00200000U
 
#define CAN_F11R2_FB22   0x00400000U
 
#define CAN_F11R2_FB23   0x00800000U
 
#define CAN_F11R2_FB24   0x01000000U
 
#define CAN_F11R2_FB25   0x02000000U
 
#define CAN_F11R2_FB26   0x04000000U
 
#define CAN_F11R2_FB27   0x08000000U
 
#define CAN_F11R2_FB28   0x10000000U
 
#define CAN_F11R2_FB29   0x20000000U
 
#define CAN_F11R2_FB30   0x40000000U
 
#define CAN_F11R2_FB31   0x80000000U
 
#define CAN_F12R2_FB0   0x00000001U
 
#define CAN_F12R2_FB1   0x00000002U
 
#define CAN_F12R2_FB2   0x00000004U
 
#define CAN_F12R2_FB3   0x00000008U
 
#define CAN_F12R2_FB4   0x00000010U
 
#define CAN_F12R2_FB5   0x00000020U
 
#define CAN_F12R2_FB6   0x00000040U
 
#define CAN_F12R2_FB7   0x00000080U
 
#define CAN_F12R2_FB8   0x00000100U
 
#define CAN_F12R2_FB9   0x00000200U
 
#define CAN_F12R2_FB10   0x00000400U
 
#define CAN_F12R2_FB11   0x00000800U
 
#define CAN_F12R2_FB12   0x00001000U
 
#define CAN_F12R2_FB13   0x00002000U
 
#define CAN_F12R2_FB14   0x00004000U
 
#define CAN_F12R2_FB15   0x00008000U
 
#define CAN_F12R2_FB16   0x00010000U
 
#define CAN_F12R2_FB17   0x00020000U
 
#define CAN_F12R2_FB18   0x00040000U
 
#define CAN_F12R2_FB19   0x00080000U
 
#define CAN_F12R2_FB20   0x00100000U
 
#define CAN_F12R2_FB21   0x00200000U
 
#define CAN_F12R2_FB22   0x00400000U
 
#define CAN_F12R2_FB23   0x00800000U
 
#define CAN_F12R2_FB24   0x01000000U
 
#define CAN_F12R2_FB25   0x02000000U
 
#define CAN_F12R2_FB26   0x04000000U
 
#define CAN_F12R2_FB27   0x08000000U
 
#define CAN_F12R2_FB28   0x10000000U
 
#define CAN_F12R2_FB29   0x20000000U
 
#define CAN_F12R2_FB30   0x40000000U
 
#define CAN_F12R2_FB31   0x80000000U
 
#define CAN_F13R2_FB0   0x00000001U
 
#define CAN_F13R2_FB1   0x00000002U
 
#define CAN_F13R2_FB2   0x00000004U
 
#define CAN_F13R2_FB3   0x00000008U
 
#define CAN_F13R2_FB4   0x00000010U
 
#define CAN_F13R2_FB5   0x00000020U
 
#define CAN_F13R2_FB6   0x00000040U
 
#define CAN_F13R2_FB7   0x00000080U
 
#define CAN_F13R2_FB8   0x00000100U
 
#define CAN_F13R2_FB9   0x00000200U
 
#define CAN_F13R2_FB10   0x00000400U
 
#define CAN_F13R2_FB11   0x00000800U
 
#define CAN_F13R2_FB12   0x00001000U
 
#define CAN_F13R2_FB13   0x00002000U
 
#define CAN_F13R2_FB14   0x00004000U
 
#define CAN_F13R2_FB15   0x00008000U
 
#define CAN_F13R2_FB16   0x00010000U
 
#define CAN_F13R2_FB17   0x00020000U
 
#define CAN_F13R2_FB18   0x00040000U
 
#define CAN_F13R2_FB19   0x00080000U
 
#define CAN_F13R2_FB20   0x00100000U
 
#define CAN_F13R2_FB21   0x00200000U
 
#define CAN_F13R2_FB22   0x00400000U
 
#define CAN_F13R2_FB23   0x00800000U
 
#define CAN_F13R2_FB24   0x01000000U
 
#define CAN_F13R2_FB25   0x02000000U
 
#define CAN_F13R2_FB26   0x04000000U
 
#define CAN_F13R2_FB27   0x08000000U
 
#define CAN_F13R2_FB28   0x10000000U
 
#define CAN_F13R2_FB29   0x20000000U
 
#define CAN_F13R2_FB30   0x40000000U
 
#define CAN_F13R2_FB31   0x80000000U
 
#define CEC_CR_CECEN   0x00000001U
 
#define CEC_CR_TXSOM   0x00000002U
 
#define CEC_CR_TXEOM   0x00000004U
 
#define CEC_CFGR_SFT   0x00000007U
 
#define CEC_CFGR_RXTOL   0x00000008U
 
#define CEC_CFGR_BRESTP   0x00000010U
 
#define CEC_CFGR_BREGEN   0x00000020U
 
#define CEC_CFGR_LBPEGEN   0x00000040U
 
#define CEC_CFGR_BRDNOGEN   0x00000080U
 
#define CEC_CFGR_SFTOPT   0x00000100U
 
#define CEC_CFGR_OAR   0x7FFF0000U
 
#define CEC_CFGR_LSTN   0x80000000U
 
#define CEC_TXDR_TXD   0x000000FFU
 
#define CEC_TXDR_RXD   0x000000FFU
 
#define CEC_ISR_RXBR   0x00000001U
 
#define CEC_ISR_RXEND   0x00000002U
 
#define CEC_ISR_RXOVR   0x00000004U
 
#define CEC_ISR_BRE   0x00000008U
 
#define CEC_ISR_SBPE   0x00000010U
 
#define CEC_ISR_LBPE   0x00000020U
 
#define CEC_ISR_RXACKE   0x00000040U
 
#define CEC_ISR_ARBLST   0x00000080U
 
#define CEC_ISR_TXBR   0x00000100U
 
#define CEC_ISR_TXEND   0x00000200U
 
#define CEC_ISR_TXUDR   0x00000400U
 
#define CEC_ISR_TXERR   0x00000800U
 
#define CEC_ISR_TXACKE   0x00001000U
 
#define CEC_IER_RXBRIE   0x00000001U
 
#define CEC_IER_RXENDIE   0x00000002U
 
#define CEC_IER_RXOVRIE   0x00000004U
 
#define CEC_IER_BREIE   0x00000008U
 
#define CEC_IER_SBPEIE   0x00000010U
 
#define CEC_IER_LBPEIE   0x00000020U
 
#define CEC_IER_RXACKEIE   0x00000040U
 
#define CEC_IER_ARBLSTIE   0x00000080U
 
#define CEC_IER_TXBRIE   0x00000100U
 
#define CEC_IER_TXENDIE   0x00000200U
 
#define CEC_IER_TXUDRIE   0x00000400U
 
#define CEC_IER_TXERRIE   0x00000800U
 
#define CEC_IER_TXACKEIE   0x00001000U
 
#define CRC_DR_DR   0xFFFFFFFFU
 
#define CRC_IDR_IDR   0x000000FFU
 
#define CRC_CR_RESET   0x00000001U
 
#define CRC_CR_POLYSIZE   0x00000018U
 
#define CRC_CR_POLYSIZE_0   0x00000008U
 
#define CRC_CR_POLYSIZE_1   0x00000010U
 
#define CRC_CR_REV_IN   0x00000060U
 
#define CRC_CR_REV_IN_0   0x00000020U
 
#define CRC_CR_REV_IN_1   0x00000040U
 
#define CRC_CR_REV_OUT   0x00000080U
 
#define CRC_INIT_INIT   0xFFFFFFFFU
 
#define CRC_POL_POL   0xFFFFFFFFU
 
#define DAC_CR_EN1   0x00000001U
 
#define DAC_CR_BOFF1   0x00000002U
 
#define DAC_CR_TEN1   0x00000004U
 
#define DAC_CR_TSEL1   0x00000038U
 
#define DAC_CR_TSEL1_0   0x00000008U
 
#define DAC_CR_TSEL1_1   0x00000010U
 
#define DAC_CR_TSEL1_2   0x00000020U
 
#define DAC_CR_WAVE1   0x000000C0U
 
#define DAC_CR_WAVE1_0   0x00000040U
 
#define DAC_CR_WAVE1_1   0x00000080U
 
#define DAC_CR_MAMP1   0x00000F00U
 
#define DAC_CR_MAMP1_0   0x00000100U
 
#define DAC_CR_MAMP1_1   0x00000200U
 
#define DAC_CR_MAMP1_2   0x00000400U
 
#define DAC_CR_MAMP1_3   0x00000800U
 
#define DAC_CR_DMAEN1   0x00001000U
 
#define DAC_CR_DMAUDRIE1   0x00002000U
 
#define DAC_CR_EN2   0x00010000U
 
#define DAC_CR_BOFF2   0x00020000U
 
#define DAC_CR_TEN2   0x00040000U
 
#define DAC_CR_TSEL2   0x00380000U
 
#define DAC_CR_TSEL2_0   0x00080000U
 
#define DAC_CR_TSEL2_1   0x00100000U
 
#define DAC_CR_TSEL2_2   0x00200000U
 
#define DAC_CR_WAVE2   0x00C00000U
 
#define DAC_CR_WAVE2_0   0x00400000U
 
#define DAC_CR_WAVE2_1   0x00800000U
 
#define DAC_CR_MAMP2   0x0F000000U
 
#define DAC_CR_MAMP2_0   0x01000000U
 
#define DAC_CR_MAMP2_1   0x02000000U
 
#define DAC_CR_MAMP2_2   0x04000000U
 
#define DAC_CR_MAMP2_3   0x08000000U
 
#define DAC_CR_DMAEN2   0x10000000U
 
#define DAC_CR_DMAUDRIE2   0x20000000U
 
#define DAC_SWTRIGR_SWTRIG1   0x01U
 
#define DAC_SWTRIGR_SWTRIG2   0x02U
 
#define DAC_DHR12R1_DACC1DHR   0x0FFFU
 
#define DAC_DHR12L1_DACC1DHR   0xFFF0U
 
#define DAC_DHR8R1_DACC1DHR   0xFFU
 
#define DAC_DHR12R2_DACC2DHR   0x0FFFU
 
#define DAC_DHR12L2_DACC2DHR   0xFFF0U
 
#define DAC_DHR8R2_DACC2DHR   0xFFU
 
#define DAC_DHR12RD_DACC1DHR   0x00000FFFU
 
#define DAC_DHR12RD_DACC2DHR   0x0FFF0000U
 
#define DAC_DHR12LD_DACC1DHR   0x0000FFF0U
 
#define DAC_DHR12LD_DACC2DHR   0xFFF00000U
 
#define DAC_DHR8RD_DACC1DHR   0x00FFU
 
#define DAC_DHR8RD_DACC2DHR   0xFF00U
 
#define DAC_DOR1_DACC1DOR   0x0FFFU
 
#define DAC_DOR2_DACC2DOR   0x0FFFU
 
#define DAC_SR_DMAUDR1   0x00002000U
 
#define DAC_SR_DMAUDR2   0x20000000U
 
#define DCMI_CR_CAPTURE   0x00000001U
 
#define DCMI_CR_CM   0x00000002U
 
#define DCMI_CR_CROP   0x00000004U
 
#define DCMI_CR_JPEG   0x00000008U
 
#define DCMI_CR_ESS   0x00000010U
 
#define DCMI_CR_PCKPOL   0x00000020U
 
#define DCMI_CR_HSPOL   0x00000040U
 
#define DCMI_CR_VSPOL   0x00000080U
 
#define DCMI_CR_FCRC_0   0x00000100U
 
#define DCMI_CR_FCRC_1   0x00000200U
 
#define DCMI_CR_EDM_0   0x00000400U
 
#define DCMI_CR_EDM_1   0x00000800U
 
#define DCMI_CR_CRE   0x00001000U
 
#define DCMI_CR_ENABLE   0x00004000U
 
#define DCMI_CR_BSM   0x00030000U
 
#define DCMI_CR_BSM_0   0x00010000U
 
#define DCMI_CR_BSM_1   0x00020000U
 
#define DCMI_CR_OEBS   0x00040000U
 
#define DCMI_CR_LSM   0x00080000U
 
#define DCMI_CR_OELS   0x00100000U
 
#define DCMI_SR_HSYNC   0x00000001U
 
#define DCMI_SR_VSYNC   0x00000002U
 
#define DCMI_SR_FNE   0x00000004U
 
#define DCMI_RIS_FRAME_RIS   0x00000001U
 
#define DCMI_RIS_OVR_RIS   0x00000002U
 
#define DCMI_RIS_ERR_RIS   0x00000004U
 
#define DCMI_RIS_VSYNC_RIS   0x00000008U
 
#define DCMI_RIS_LINE_RIS   0x00000010U
 
#define DCMI_RISR_FRAME_RIS   DCMI_RIS_FRAME_RIS
 
#define DCMI_RISR_OVF_RIS   DCMI_RIS_OVR_RIS
 
#define DCMI_RISR_ERR_RIS   DCMI_RIS_ERR_RIS
 
#define DCMI_RISR_VSYNC_RIS   DCMI_RIS_VSYNC_RIS
 
#define DCMI_RISR_LINE_RIS   DCMI_RIS_LINE_RIS
 
#define DCMI_IER_FRAME_IE   0x00000001U
 
#define DCMI_IER_OVR_IE   0x00000002U
 
#define DCMI_IER_ERR_IE   0x00000004U
 
#define DCMI_IER_VSYNC_IE   0x00000008U
 
#define DCMI_IER_LINE_IE   0x00000010U
 
#define DCMI_IER_OVF_IE   DCMI_IER_OVR_IE
 
#define DCMI_MIS_FRAME_MIS   0x00000001U
 
#define DCMI_MIS_OVR_MIS   0x00000002U
 
#define DCMI_MIS_ERR_MIS   0x00000004U
 
#define DCMI_MIS_VSYNC_MIS   0x00000008U
 
#define DCMI_MIS_LINE_MIS   0x00000010U
 
#define DCMI_MISR_FRAME_MIS   DCMI_MIS_FRAME_MIS
 
#define DCMI_MISR_OVF_MIS   DCMI_MIS_OVR_MIS
 
#define DCMI_MISR_ERR_MIS   DCMI_MIS_ERR_MIS
 
#define DCMI_MISR_VSYNC_MIS   DCMI_MIS_VSYNC_MIS
 
#define DCMI_MISR_LINE_MIS   DCMI_MIS_LINE_MIS
 
#define DCMI_ICR_FRAME_ISC   0x00000001U
 
#define DCMI_ICR_OVR_ISC   0x00000002U
 
#define DCMI_ICR_ERR_ISC   0x00000004U
 
#define DCMI_ICR_VSYNC_ISC   0x00000008U
 
#define DCMI_ICR_LINE_ISC   0x00000010U
 
#define DCMI_ICR_OVF_ISC   DCMI_ICR_OVR_ISC
 
#define DCMI_ESCR_FSC   0x000000FFU
 
#define DCMI_ESCR_LSC   0x0000FF00U
 
#define DCMI_ESCR_LEC   0x00FF0000U
 
#define DCMI_ESCR_FEC   0xFF000000U
 
#define DCMI_ESUR_FSU   0x000000FFU
 
#define DCMI_ESUR_LSU   0x0000FF00U
 
#define DCMI_ESUR_LEU   0x00FF0000U
 
#define DCMI_ESUR_FEU   0xFF000000U
 
#define DCMI_CWSTRT_HOFFCNT   0x00003FFFU
 
#define DCMI_CWSTRT_VST   0x1FFF0000U
 
#define DCMI_CWSIZE_CAPCNT   0x00003FFFU
 
#define DCMI_CWSIZE_VLINE   0x3FFF0000U
 
#define DCMI_DR_BYTE0   0x000000FFU
 
#define DCMI_DR_BYTE1   0x0000FF00U
 
#define DCMI_DR_BYTE2   0x00FF0000U
 
#define DCMI_DR_BYTE3   0xFF000000U
 
#define DMA_SxCR_CHSEL   0x0E000000U
 
#define DMA_SxCR_CHSEL_0   0x02000000U
 
#define DMA_SxCR_CHSEL_1   0x04000000U
 
#define DMA_SxCR_CHSEL_2   0x08000000U
 
#define DMA_SxCR_MBURST   0x01800000U
 
#define DMA_SxCR_MBURST_0   0x00800000U
 
#define DMA_SxCR_MBURST_1   0x01000000U
 
#define DMA_SxCR_PBURST   0x00600000U
 
#define DMA_SxCR_PBURST_0   0x00200000U
 
#define DMA_SxCR_PBURST_1   0x00400000U
 
#define DMA_SxCR_CT   0x00080000U
 
#define DMA_SxCR_DBM   0x00040000U
 
#define DMA_SxCR_PL   0x00030000U
 
#define DMA_SxCR_PL_0   0x00010000U
 
#define DMA_SxCR_PL_1   0x00020000U
 
#define DMA_SxCR_PINCOS   0x00008000U
 
#define DMA_SxCR_MSIZE   0x00006000U
 
#define DMA_SxCR_MSIZE_0   0x00002000U
 
#define DMA_SxCR_MSIZE_1   0x00004000U
 
#define DMA_SxCR_PSIZE   0x00001800U
 
#define DMA_SxCR_PSIZE_0   0x00000800U
 
#define DMA_SxCR_PSIZE_1   0x00001000U
 
#define DMA_SxCR_MINC   0x00000400U
 
#define DMA_SxCR_PINC   0x00000200U
 
#define DMA_SxCR_CIRC   0x00000100U
 
#define DMA_SxCR_DIR   0x000000C0U
 
#define DMA_SxCR_DIR_0   0x00000040U
 
#define DMA_SxCR_DIR_1   0x00000080U
 
#define DMA_SxCR_PFCTRL   0x00000020U
 
#define DMA_SxCR_TCIE   0x00000010U
 
#define DMA_SxCR_HTIE   0x00000008U
 
#define DMA_SxCR_TEIE   0x00000004U
 
#define DMA_SxCR_DMEIE   0x00000002U
 
#define DMA_SxCR_EN   0x00000001U
 
#define DMA_SxNDT   0x0000FFFFU
 
#define DMA_SxNDT_0   0x00000001U
 
#define DMA_SxNDT_1   0x00000002U
 
#define DMA_SxNDT_2   0x00000004U
 
#define DMA_SxNDT_3   0x00000008U
 
#define DMA_SxNDT_4   0x00000010U
 
#define DMA_SxNDT_5   0x00000020U
 
#define DMA_SxNDT_6   0x00000040U
 
#define DMA_SxNDT_7   0x00000080U
 
#define DMA_SxNDT_8   0x00000100U
 
#define DMA_SxNDT_9   0x00000200U
 
#define DMA_SxNDT_10   0x00000400U
 
#define DMA_SxNDT_11   0x00000800U
 
#define DMA_SxNDT_12   0x00001000U
 
#define DMA_SxNDT_13   0x00002000U
 
#define DMA_SxNDT_14   0x00004000U
 
#define DMA_SxNDT_15   0x00008000U
 
#define DMA_SxFCR_FEIE   0x00000080U
 
#define DMA_SxFCR_FS   0x00000038U
 
#define DMA_SxFCR_FS_0   0x00000008U
 
#define DMA_SxFCR_FS_1   0x00000010U
 
#define DMA_SxFCR_FS_2   0x00000020U
 
#define DMA_SxFCR_DMDIS   0x00000004U
 
#define DMA_SxFCR_FTH   0x00000003U
 
#define DMA_SxFCR_FTH_0   0x00000001U
 
#define DMA_SxFCR_FTH_1   0x00000002U
 
#define DMA_LISR_TCIF3   0x08000000U
 
#define DMA_LISR_HTIF3   0x04000000U
 
#define DMA_LISR_TEIF3   0x02000000U
 
#define DMA_LISR_DMEIF3   0x01000000U
 
#define DMA_LISR_FEIF3   0x00400000U
 
#define DMA_LISR_TCIF2   0x00200000U
 
#define DMA_LISR_HTIF2   0x00100000U
 
#define DMA_LISR_TEIF2   0x00080000U
 
#define DMA_LISR_DMEIF2   0x00040000U
 
#define DMA_LISR_FEIF2   0x00010000U
 
#define DMA_LISR_TCIF1   0x00000800U
 
#define DMA_LISR_HTIF1   0x00000400U
 
#define DMA_LISR_TEIF1   0x00000200U
 
#define DMA_LISR_DMEIF1   0x00000100U
 
#define DMA_LISR_FEIF1   0x00000040U
 
#define DMA_LISR_TCIF0   0x00000020U
 
#define DMA_LISR_HTIF0   0x00000010U
 
#define DMA_LISR_TEIF0   0x00000008U
 
#define DMA_LISR_DMEIF0   0x00000004U
 
#define DMA_LISR_FEIF0   0x00000001U
 
#define DMA_HISR_TCIF7   0x08000000U
 
#define DMA_HISR_HTIF7   0x04000000U
 
#define DMA_HISR_TEIF7   0x02000000U
 
#define DMA_HISR_DMEIF7   0x01000000U
 
#define DMA_HISR_FEIF7   0x00400000U
 
#define DMA_HISR_TCIF6   0x00200000U
 
#define DMA_HISR_HTIF6   0x00100000U
 
#define DMA_HISR_TEIF6   0x00080000U
 
#define DMA_HISR_DMEIF6   0x00040000U
 
#define DMA_HISR_FEIF6   0x00010000U
 
#define DMA_HISR_TCIF5   0x00000800U
 
#define DMA_HISR_HTIF5   0x00000400U
 
#define DMA_HISR_TEIF5   0x00000200U
 
#define DMA_HISR_DMEIF5   0x00000100U
 
#define DMA_HISR_FEIF5   0x00000040U
 
#define DMA_HISR_TCIF4   0x00000020U
 
#define DMA_HISR_HTIF4   0x00000010U
 
#define DMA_HISR_TEIF4   0x00000008U
 
#define DMA_HISR_DMEIF4   0x00000004U
 
#define DMA_HISR_FEIF4   0x00000001U
 
#define DMA_LIFCR_CTCIF3   0x08000000U
 
#define DMA_LIFCR_CHTIF3   0x04000000U
 
#define DMA_LIFCR_CTEIF3   0x02000000U
 
#define DMA_LIFCR_CDMEIF3   0x01000000U
 
#define DMA_LIFCR_CFEIF3   0x00400000U
 
#define DMA_LIFCR_CTCIF2   0x00200000U
 
#define DMA_LIFCR_CHTIF2   0x00100000U
 
#define DMA_LIFCR_CTEIF2   0x00080000U
 
#define DMA_LIFCR_CDMEIF2   0x00040000U
 
#define DMA_LIFCR_CFEIF2   0x00010000U
 
#define DMA_LIFCR_CTCIF1   0x00000800U
 
#define DMA_LIFCR_CHTIF1   0x00000400U
 
#define DMA_LIFCR_CTEIF1   0x00000200U
 
#define DMA_LIFCR_CDMEIF1   0x00000100U
 
#define DMA_LIFCR_CFEIF1   0x00000040U
 
#define DMA_LIFCR_CTCIF0   0x00000020U
 
#define DMA_LIFCR_CHTIF0   0x00000010U
 
#define DMA_LIFCR_CTEIF0   0x00000008U
 
#define DMA_LIFCR_CDMEIF0   0x00000004U
 
#define DMA_LIFCR_CFEIF0   0x00000001U
 
#define DMA_HIFCR_CTCIF7   0x08000000U
 
#define DMA_HIFCR_CHTIF7   0x04000000U
 
#define DMA_HIFCR_CTEIF7   0x02000000U
 
#define DMA_HIFCR_CDMEIF7   0x01000000U
 
#define DMA_HIFCR_CFEIF7   0x00400000U
 
#define DMA_HIFCR_CTCIF6   0x00200000U
 
#define DMA_HIFCR_CHTIF6   0x00100000U
 
#define DMA_HIFCR_CTEIF6   0x00080000U
 
#define DMA_HIFCR_CDMEIF6   0x00040000U
 
#define DMA_HIFCR_CFEIF6   0x00010000U
 
#define DMA_HIFCR_CTCIF5   0x00000800U
 
#define DMA_HIFCR_CHTIF5   0x00000400U
 
#define DMA_HIFCR_CTEIF5   0x00000200U
 
#define DMA_HIFCR_CDMEIF5   0x00000100U
 
#define DMA_HIFCR_CFEIF5   0x00000040U
 
#define DMA_HIFCR_CTCIF4   0x00000020U
 
#define DMA_HIFCR_CHTIF4   0x00000010U
 
#define DMA_HIFCR_CTEIF4   0x00000008U
 
#define DMA_HIFCR_CDMEIF4   0x00000004U
 
#define DMA_HIFCR_CFEIF4   0x00000001U
 
#define DMA2D_CR_START   0x00000001U
 
#define DMA2D_CR_SUSP   0x00000002U
 
#define DMA2D_CR_ABORT   0x00000004U
 
#define DMA2D_CR_TEIE   0x00000100U
 
#define DMA2D_CR_TCIE   0x00000200U
 
#define DMA2D_CR_TWIE   0x00000400U
 
#define DMA2D_CR_CAEIE   0x00000800U
 
#define DMA2D_CR_CTCIE   0x00001000U
 
#define DMA2D_CR_CEIE   0x00002000U
 
#define DMA2D_CR_MODE   0x00030000U
 
#define DMA2D_CR_MODE_0   0x00010000U
 
#define DMA2D_CR_MODE_1   0x00020000U
 
#define DMA2D_ISR_TEIF   0x00000001U
 
#define DMA2D_ISR_TCIF   0x00000002U
 
#define DMA2D_ISR_TWIF   0x00000004U
 
#define DMA2D_ISR_CAEIF   0x00000008U
 
#define DMA2D_ISR_CTCIF   0x00000010U
 
#define DMA2D_ISR_CEIF   0x00000020U
 
#define DMA2D_IFCR_CTEIF   0x00000001U
 
#define DMA2D_IFCR_CTCIF   0x00000002U
 
#define DMA2D_IFCR_CTWIF   0x00000004U
 
#define DMA2D_IFCR_CAECIF   0x00000008U
 
#define DMA2D_IFCR_CCTCIF   0x00000010U
 
#define DMA2D_IFCR_CCEIF   0x00000020U
 
#define DMA2D_IFSR_CTEIF   DMA2D_IFCR_CTEIF
 
#define DMA2D_IFSR_CTCIF   DMA2D_IFCR_CTCIF
 
#define DMA2D_IFSR_CTWIF   DMA2D_IFCR_CTWIF
 
#define DMA2D_IFSR_CCAEIF   DMA2D_IFCR_CAECIF
 
#define DMA2D_IFSR_CCTCIF   DMA2D_IFCR_CCTCIF
 
#define DMA2D_IFSR_CCEIF   DMA2D_IFCR_CCEIF
 
#define DMA2D_FGMAR_MA   0xFFFFFFFFU
 
#define DMA2D_FGOR_LO   0x00003FFFU
 
#define DMA2D_BGMAR_MA   0xFFFFFFFFU
 
#define DMA2D_BGOR_LO   0x00003FFFU
 
#define DMA2D_FGPFCCR_CM   0x0000000FU
 
#define DMA2D_FGPFCCR_CM_0   0x00000001U
 
#define DMA2D_FGPFCCR_CM_1   0x00000002U
 
#define DMA2D_FGPFCCR_CM_2   0x00000004U
 
#define DMA2D_FGPFCCR_CM_3   0x00000008U
 
#define DMA2D_FGPFCCR_CM_3   0x00000008U
 
#define DMA2D_FGPFCCR_CCM   0x00000010U
 
#define DMA2D_FGPFCCR_START   0x00000020U
 
#define DMA2D_FGPFCCR_CS   0x0000FF00U
 
#define DMA2D_FGPFCCR_AM   0x00030000U
 
#define DMA2D_FGPFCCR_AM_0   0x00010000U
 
#define DMA2D_FGPFCCR_AM_1   0x00020000U
 
#define DMA2D_FGPFCCR_ALPHA   0xFF000000U
 
#define DMA2D_FGCOLR_BLUE   0x000000FFU
 
#define DMA2D_FGCOLR_GREEN   0x0000FF00U
 
#define DMA2D_FGCOLR_RED   0x00FF0000U
 
#define DMA2D_BGPFCCR_CM   0x0000000FU
 
#define DMA2D_BGPFCCR_CM_0   0x00000001U
 
#define DMA2D_BGPFCCR_CM_1   0x00000002U
 
#define DMA2D_BGPFCCR_CM_2   0x00000004U
 
#define DMA2D_BGPFCCR_CCM   0x00000010U
 
#define DMA2D_BGPFCCR_START   0x00000020U
 
#define DMA2D_BGPFCCR_CS   0x0000FF00U
 
#define DMA2D_BGPFCCR_AM   0x00030000U
 
#define DMA2D_BGPFCCR_AM_0   0x00010000U
 
#define DMA2D_BGPFCCR_AM_1   0x00020000U
 
#define DMA2D_BGPFCCR_ALPHA   0xFF000000U
 
#define DMA2D_BGCOLR_BLUE   0x000000FFU
 
#define DMA2D_BGCOLR_GREEN   0x0000FF00U
 
#define DMA2D_BGCOLR_RED   0x00FF0000U
 
#define DMA2D_FGCMAR_MA   0xFFFFFFFFU
 
#define DMA2D_BGCMAR_MA   0xFFFFFFFFU
 
#define DMA2D_OPFCCR_CM   0x00000007U
 
#define DMA2D_OPFCCR_CM_0   0x00000001U
 
#define DMA2D_OPFCCR_CM_1   0x00000002U
 
#define DMA2D_OPFCCR_CM_2   0x00000004U
 
#define DMA2D_OCOLR_BLUE_1   0x000000FFU
 
#define DMA2D_OCOLR_GREEN_1   0x0000FF00U
 
#define DMA2D_OCOLR_RED_1   0x00FF0000U
 
#define DMA2D_OCOLR_ALPHA_1   0xFF000000U
 
#define DMA2D_OCOLR_BLUE_2   0x0000001FU
 
#define DMA2D_OCOLR_GREEN_2   0x000007E0U
 
#define DMA2D_OCOLR_RED_2   0x0000F800U
 
#define DMA2D_OCOLR_BLUE_3   0x0000001FU
 
#define DMA2D_OCOLR_GREEN_3   0x000003E0U
 
#define DMA2D_OCOLR_RED_3   0x00007C00U
 
#define DMA2D_OCOLR_ALPHA_3   0x00008000U
 
#define DMA2D_OCOLR_BLUE_4   0x0000000FU
 
#define DMA2D_OCOLR_GREEN_4   0x000000F0U
 
#define DMA2D_OCOLR_RED_4   0x00000F00U
 
#define DMA2D_OCOLR_ALPHA_4   0x0000F000U
 
#define DMA2D_OMAR_MA   0xFFFFFFFFU
 
#define DMA2D_OOR_LO   0x00003FFFU
 
#define DMA2D_NLR_NL   0x0000FFFFU
 
#define DMA2D_NLR_PL   0x3FFF0000U
 
#define DMA2D_LWR_LW   0x0000FFFFU
 
#define DMA2D_AMTCR_EN   0x00000001U
 
#define DMA2D_AMTCR_DT   0x0000FF00U
 
#define EXTI_IMR_MR0   0x00000001U
 
#define EXTI_IMR_MR1   0x00000002U
 
#define EXTI_IMR_MR2   0x00000004U
 
#define EXTI_IMR_MR3   0x00000008U
 
#define EXTI_IMR_MR4   0x00000010U
 
#define EXTI_IMR_MR5   0x00000020U
 
#define EXTI_IMR_MR6   0x00000040U
 
#define EXTI_IMR_MR7   0x00000080U
 
#define EXTI_IMR_MR8   0x00000100U
 
#define EXTI_IMR_MR9   0x00000200U
 
#define EXTI_IMR_MR10   0x00000400U
 
#define EXTI_IMR_MR11   0x00000800U
 
#define EXTI_IMR_MR12   0x00001000U
 
#define EXTI_IMR_MR13   0x00002000U
 
#define EXTI_IMR_MR14   0x00004000U
 
#define EXTI_IMR_MR15   0x00008000U
 
#define EXTI_IMR_MR16   0x00010000U
 
#define EXTI_IMR_MR17   0x00020000U
 
#define EXTI_IMR_MR18   0x00040000U
 
#define EXTI_IMR_MR19   0x00080000U
 
#define EXTI_IMR_MR20   0x00100000U
 
#define EXTI_IMR_MR21   0x00200000U
 
#define EXTI_IMR_MR22   0x00400000U
 
#define EXTI_IMR_MR23   0x00800000U
 
#define EXTI_IMR_IM0   EXTI_IMR_MR0
 
#define EXTI_IMR_IM1   EXTI_IMR_MR1
 
#define EXTI_IMR_IM2   EXTI_IMR_MR2
 
#define EXTI_IMR_IM3   EXTI_IMR_MR3
 
#define EXTI_IMR_IM4   EXTI_IMR_MR4
 
#define EXTI_IMR_IM5   EXTI_IMR_MR5
 
#define EXTI_IMR_IM6   EXTI_IMR_MR6
 
#define EXTI_IMR_IM7   EXTI_IMR_MR7
 
#define EXTI_IMR_IM8   EXTI_IMR_MR8
 
#define EXTI_IMR_IM9   EXTI_IMR_MR9
 
#define EXTI_IMR_IM10   EXTI_IMR_MR10
 
#define EXTI_IMR_IM11   EXTI_IMR_MR11
 
#define EXTI_IMR_IM12   EXTI_IMR_MR12
 
#define EXTI_IMR_IM13   EXTI_IMR_MR13
 
#define EXTI_IMR_IM14   EXTI_IMR_MR14
 
#define EXTI_IMR_IM15   EXTI_IMR_MR15
 
#define EXTI_IMR_IM16   EXTI_IMR_MR16
 
#define EXTI_IMR_IM17   EXTI_IMR_MR17
 
#define EXTI_IMR_IM18   EXTI_IMR_MR18
 
#define EXTI_IMR_IM19   EXTI_IMR_MR19
 
#define EXTI_IMR_IM20   EXTI_IMR_MR20
 
#define EXTI_IMR_IM21   EXTI_IMR_MR21
 
#define EXTI_IMR_IM22   EXTI_IMR_MR22
 
#define EXTI_IMR_IM23   EXTI_IMR_MR23
 
#define EXTI_IMR_IM   0x00FFFFFFU
 
#define EXTI_EMR_MR0   0x00000001U
 
#define EXTI_EMR_MR1   0x00000002U
 
#define EXTI_EMR_MR2   0x00000004U
 
#define EXTI_EMR_MR3   0x00000008U
 
#define EXTI_EMR_MR4   0x00000010U
 
#define EXTI_EMR_MR5   0x00000020U
 
#define EXTI_EMR_MR6   0x00000040U
 
#define EXTI_EMR_MR7   0x00000080U
 
#define EXTI_EMR_MR8   0x00000100U
 
#define EXTI_EMR_MR9   0x00000200U
 
#define EXTI_EMR_MR10   0x00000400U
 
#define EXTI_EMR_MR11   0x00000800U
 
#define EXTI_EMR_MR12   0x00001000U
 
#define EXTI_EMR_MR13   0x00002000U
 
#define EXTI_EMR_MR14   0x00004000U
 
#define EXTI_EMR_MR15   0x00008000U
 
#define EXTI_EMR_MR16   0x00010000U
 
#define EXTI_EMR_MR17   0x00020000U
 
#define EXTI_EMR_MR18   0x00040000U
 
#define EXTI_EMR_MR19   0x00080000U
 
#define EXTI_EMR_MR20   0x00100000U
 
#define EXTI_EMR_MR21   0x00200000U
 
#define EXTI_EMR_MR22   0x00400000U
 
#define EXTI_EMR_MR23   0x00800000U
 
#define EXTI_EMR_EM0   EXTI_EMR_MR0
 
#define EXTI_EMR_EM1   EXTI_EMR_MR1
 
#define EXTI_EMR_EM2   EXTI_EMR_MR2
 
#define EXTI_EMR_EM3   EXTI_EMR_MR3
 
#define EXTI_EMR_EM4   EXTI_EMR_MR4
 
#define EXTI_EMR_EM5   EXTI_EMR_MR5
 
#define EXTI_EMR_EM6   EXTI_EMR_MR6
 
#define EXTI_EMR_EM7   EXTI_EMR_MR7
 
#define EXTI_EMR_EM8   EXTI_EMR_MR8
 
#define EXTI_EMR_EM9   EXTI_EMR_MR9
 
#define EXTI_EMR_EM10   EXTI_EMR_MR10
 
#define EXTI_EMR_EM11   EXTI_EMR_MR11
 
#define EXTI_EMR_EM12   EXTI_EMR_MR12
 
#define EXTI_EMR_EM13   EXTI_EMR_MR13
 
#define EXTI_EMR_EM14   EXTI_EMR_MR14
 
#define EXTI_EMR_EM15   EXTI_EMR_MR15
 
#define EXTI_EMR_EM16   EXTI_EMR_MR16
 
#define EXTI_EMR_EM17   EXTI_EMR_MR17
 
#define EXTI_EMR_EM18   EXTI_EMR_MR18
 
#define EXTI_EMR_EM19   EXTI_EMR_MR19
 
#define EXTI_EMR_EM20   EXTI_EMR_MR20
 
#define EXTI_EMR_EM21   EXTI_EMR_MR21
 
#define EXTI_EMR_EM22   EXTI_EMR_MR22
 
#define EXTI_EMR_EM23   EXTI_EMR_MR23
 
#define EXTI_RTSR_TR0   0x00000001U
 
#define EXTI_RTSR_TR1   0x00000002U
 
#define EXTI_RTSR_TR2   0x00000004U
 
#define EXTI_RTSR_TR3   0x00000008U
 
#define EXTI_RTSR_TR4   0x00000010U
 
#define EXTI_RTSR_TR5   0x00000020U
 
#define EXTI_RTSR_TR6   0x00000040U
 
#define EXTI_RTSR_TR7   0x00000080U
 
#define EXTI_RTSR_TR8   0x00000100U
 
#define EXTI_RTSR_TR9   0x00000200U
 
#define EXTI_RTSR_TR10   0x00000400U
 
#define EXTI_RTSR_TR11   0x00000800U
 
#define EXTI_RTSR_TR12   0x00001000U
 
#define EXTI_RTSR_TR13   0x00002000U
 
#define EXTI_RTSR_TR14   0x00004000U
 
#define EXTI_RTSR_TR15   0x00008000U
 
#define EXTI_RTSR_TR16   0x00010000U
 
#define EXTI_RTSR_TR17   0x00020000U
 
#define EXTI_RTSR_TR18   0x00040000U
 
#define EXTI_RTSR_TR19   0x00080000U
 
#define EXTI_RTSR_TR20   0x00100000U
 
#define EXTI_RTSR_TR21   0x00200000U
 
#define EXTI_RTSR_TR22   0x00400000U
 
#define EXTI_RTSR_TR23   0x00800000U
 
#define EXTI_FTSR_TR0   0x00000001U
 
#define EXTI_FTSR_TR1   0x00000002U
 
#define EXTI_FTSR_TR2   0x00000004U
 
#define EXTI_FTSR_TR3   0x00000008U
 
#define EXTI_FTSR_TR4   0x00000010U
 
#define EXTI_FTSR_TR5   0x00000020U
 
#define EXTI_FTSR_TR6   0x00000040U
 
#define EXTI_FTSR_TR7   0x00000080U
 
#define EXTI_FTSR_TR8   0x00000100U
 
#define EXTI_FTSR_TR9   0x00000200U
 
#define EXTI_FTSR_TR10   0x00000400U
 
#define EXTI_FTSR_TR11   0x00000800U
 
#define EXTI_FTSR_TR12   0x00001000U
 
#define EXTI_FTSR_TR13   0x00002000U
 
#define EXTI_FTSR_TR14   0x00004000U
 
#define EXTI_FTSR_TR15   0x00008000U
 
#define EXTI_FTSR_TR16   0x00010000U
 
#define EXTI_FTSR_TR17   0x00020000U
 
#define EXTI_FTSR_TR18   0x00040000U
 
#define EXTI_FTSR_TR19   0x00080000U
 
#define EXTI_FTSR_TR20   0x00100000U
 
#define EXTI_FTSR_TR21   0x00200000U
 
#define EXTI_FTSR_TR22   0x00400000U
 
#define EXTI_FTSR_TR23   0x00800000U
 
#define EXTI_SWIER_SWIER0   0x00000001U
 
#define EXTI_SWIER_SWIER1   0x00000002U
 
#define EXTI_SWIER_SWIER2   0x00000004U
 
#define EXTI_SWIER_SWIER3   0x00000008U
 
#define EXTI_SWIER_SWIER4   0x00000010U
 
#define EXTI_SWIER_SWIER5   0x00000020U
 
#define EXTI_SWIER_SWIER6   0x00000040U
 
#define EXTI_SWIER_SWIER7   0x00000080U
 
#define EXTI_SWIER_SWIER8   0x00000100U
 
#define EXTI_SWIER_SWIER9   0x00000200U
 
#define EXTI_SWIER_SWIER10   0x00000400U
 
#define EXTI_SWIER_SWIER11   0x00000800U
 
#define EXTI_SWIER_SWIER12   0x00001000U
 
#define EXTI_SWIER_SWIER13   0x00002000U
 
#define EXTI_SWIER_SWIER14   0x00004000U
 
#define EXTI_SWIER_SWIER15   0x00008000U
 
#define EXTI_SWIER_SWIER16   0x00010000U
 
#define EXTI_SWIER_SWIER17   0x00020000U
 
#define EXTI_SWIER_SWIER18   0x00040000U
 
#define EXTI_SWIER_SWIER19   0x00080000U
 
#define EXTI_SWIER_SWIER20   0x00100000U
 
#define EXTI_SWIER_SWIER21   0x00200000U
 
#define EXTI_SWIER_SWIER22   0x00400000U
 
#define EXTI_SWIER_SWIER23   0x00800000U
 
#define EXTI_PR_PR0   0x00000001U
 
#define EXTI_PR_PR1   0x00000002U
 
#define EXTI_PR_PR2   0x00000004U
 
#define EXTI_PR_PR3   0x00000008U
 
#define EXTI_PR_PR4   0x00000010U
 
#define EXTI_PR_PR5   0x00000020U
 
#define EXTI_PR_PR6   0x00000040U
 
#define EXTI_PR_PR7   0x00000080U
 
#define EXTI_PR_PR8   0x00000100U
 
#define EXTI_PR_PR9   0x00000200U
 
#define EXTI_PR_PR10   0x00000400U
 
#define EXTI_PR_PR11   0x00000800U
 
#define EXTI_PR_PR12   0x00001000U
 
#define EXTI_PR_PR13   0x00002000U
 
#define EXTI_PR_PR14   0x00004000U
 
#define EXTI_PR_PR15   0x00008000U
 
#define EXTI_PR_PR16   0x00010000U
 
#define EXTI_PR_PR17   0x00020000U
 
#define EXTI_PR_PR18   0x00040000U
 
#define EXTI_PR_PR19   0x00080000U
 
#define EXTI_PR_PR20   0x00100000U
 
#define EXTI_PR_PR21   0x00200000U
 
#define EXTI_PR_PR22   0x00400000U
 
#define EXTI_PR_PR23   0x00800000U
 
#define FLASH_SECTOR_TOTAL   8
 
#define FLASH_ACR_LATENCY   0x0000000FU
 
#define FLASH_ACR_LATENCY_0WS   0x00000000U
 
#define FLASH_ACR_LATENCY_1WS   0x00000001U
 
#define FLASH_ACR_LATENCY_2WS   0x00000002U
 
#define FLASH_ACR_LATENCY_3WS   0x00000003U
 
#define FLASH_ACR_LATENCY_4WS   0x00000004U
 
#define FLASH_ACR_LATENCY_5WS   0x00000005U
 
#define FLASH_ACR_LATENCY_6WS   0x00000006U
 
#define FLASH_ACR_LATENCY_7WS   0x00000007U
 
#define FLASH_ACR_LATENCY_8WS   0x00000008U
 
#define FLASH_ACR_LATENCY_9WS   0x00000009U
 
#define FLASH_ACR_LATENCY_10WS   0x0000000AU
 
#define FLASH_ACR_LATENCY_11WS   0x0000000BU
 
#define FLASH_ACR_LATENCY_12WS   0x0000000CU
 
#define FLASH_ACR_LATENCY_13WS   0x0000000DU
 
#define FLASH_ACR_LATENCY_14WS   0x0000000EU
 
#define FLASH_ACR_LATENCY_15WS   0x0000000FU
 
#define FLASH_ACR_PRFTEN   0x00000100U
 
#define FLASH_ACR_ARTEN   0x00000200U
 
#define FLASH_ACR_ARTRST   0x00000800U
 
#define FLASH_SR_EOP   0x00000001U
 
#define FLASH_SR_OPERR   0x00000002U
 
#define FLASH_SR_WRPERR   0x00000010U
 
#define FLASH_SR_PGAERR   0x00000020U
 
#define FLASH_SR_PGPERR   0x00000040U
 
#define FLASH_SR_ERSERR   0x00000080U
 
#define FLASH_SR_BSY   0x00010000U
 
#define FLASH_CR_PG   0x00000001U
 
#define FLASH_CR_SER   0x00000002U
 
#define FLASH_CR_MER   0x00000004U
 
#define FLASH_CR_SNB   0x00000078U
 
#define FLASH_CR_SNB_0   0x00000008U
 
#define FLASH_CR_SNB_1   0x00000010U
 
#define FLASH_CR_SNB_2   0x00000020U
 
#define FLASH_CR_SNB_3   0x00000040U
 
#define FLASH_CR_PSIZE   0x00000300U
 
#define FLASH_CR_PSIZE_0   0x00000100U
 
#define FLASH_CR_PSIZE_1   0x00000200U
 
#define FLASH_CR_STRT   0x00010000U
 
#define FLASH_CR_EOPIE   0x01000000U
 
#define FLASH_CR_ERRIE   0x02000000U
 
#define FLASH_CR_LOCK   0x80000000U
 
#define FLASH_OPTCR_OPTLOCK   0x00000001U
 
#define FLASH_OPTCR_OPTSTRT   0x00000002U
 
#define FLASH_OPTCR_BOR_LEV   0x0000000CU
 
#define FLASH_OPTCR_BOR_LEV_0   0x00000004U
 
#define FLASH_OPTCR_BOR_LEV_1   0x00000008U
 
#define FLASH_OPTCR_WWDG_SW   0x00000010U
 
#define FLASH_OPTCR_IWDG_SW   0x00000020U
 
#define FLASH_OPTCR_nRST_STOP   0x00000040U
 
#define FLASH_OPTCR_nRST_STDBY   0x00000080U
 
#define FLASH_OPTCR_RDP   0x0000FF00U
 
#define FLASH_OPTCR_RDP_0   0x00000100U
 
#define FLASH_OPTCR_RDP_1   0x00000200U
 
#define FLASH_OPTCR_RDP_2   0x00000400U
 
#define FLASH_OPTCR_RDP_3   0x00000800U
 
#define FLASH_OPTCR_RDP_4   0x00001000U
 
#define FLASH_OPTCR_RDP_5   0x00002000U
 
#define FLASH_OPTCR_RDP_6   0x00004000U
 
#define FLASH_OPTCR_RDP_7   0x00008000U
 
#define FLASH_OPTCR_nWRP   0x00FF0000U
 
#define FLASH_OPTCR_nWRP_0   0x00010000U
 
#define FLASH_OPTCR_nWRP_1   0x00020000U
 
#define FLASH_OPTCR_nWRP_2   0x00040000U
 
#define FLASH_OPTCR_nWRP_3   0x00080000U
 
#define FLASH_OPTCR_nWRP_4   0x00100000U
 
#define FLASH_OPTCR_nWRP_5   0x00200000U
 
#define FLASH_OPTCR_nWRP_6   0x00400000U
 
#define FLASH_OPTCR_nWRP_7   0x00800000U
 
#define FLASH_OPTCR_IWDG_STDBY   0x40000000U
 
#define FLASH_OPTCR_IWDG_STOP   0x80000000U
 
#define FLASH_OPTCR1_BOOT_ADD0   0x0000FFFFU
 
#define FLASH_OPTCR1_BOOT_ADD1   0xFFFF0000U
 
#define FMC_BCR1_MBKEN   0x00000001U
 
#define FMC_BCR1_MUXEN   0x00000002U
 
#define FMC_BCR1_MTYP   0x0000000CU
 
#define FMC_BCR1_MTYP_0   0x00000004U
 
#define FMC_BCR1_MTYP_1   0x00000008U
 
#define FMC_BCR1_MWID   0x00000030U
 
#define FMC_BCR1_MWID_0   0x00000010U
 
#define FMC_BCR1_MWID_1   0x00000020U
 
#define FMC_BCR1_FACCEN   0x00000040U
 
#define FMC_BCR1_BURSTEN   0x00000100U
 
#define FMC_BCR1_WAITPOL   0x00000200U
 
#define FMC_BCR1_WRAPMOD   0x00000400U
 
#define FMC_BCR1_WAITCFG   0x00000800U
 
#define FMC_BCR1_WREN   0x00001000U
 
#define FMC_BCR1_WAITEN   0x00002000U
 
#define FMC_BCR1_EXTMOD   0x00004000U
 
#define FMC_BCR1_ASYNCWAIT   0x00008000U
 
#define FMC_BCR1_CPSIZE   0x00070000U
 
#define FMC_BCR1_CPSIZE_0   0x00010000U
 
#define FMC_BCR1_CPSIZE_1   0x00020000U
 
#define FMC_BCR1_CPSIZE_2   0x00040000U
 
#define FMC_BCR1_CBURSTRW   0x00080000U
 
#define FMC_BCR1_CCLKEN   0x00100000U
 
#define FMC_BCR1_WFDIS   0x00200000U
 
#define FMC_BCR2_MBKEN   0x00000001U
 
#define FMC_BCR2_MUXEN   0x00000002U
 
#define FMC_BCR2_MTYP   0x0000000CU
 
#define FMC_BCR2_MTYP_0   0x00000004U
 
#define FMC_BCR2_MTYP_1   0x00000008U
 
#define FMC_BCR2_MWID   0x00000030U
 
#define FMC_BCR2_MWID_0   0x00000010U
 
#define FMC_BCR2_MWID_1   0x00000020U
 
#define FMC_BCR2_FACCEN   0x00000040U
 
#define FMC_BCR2_BURSTEN   0x00000100U
 
#define FMC_BCR2_WAITPOL   0x00000200U
 
#define FMC_BCR2_WRAPMOD   0x00000400U
 
#define FMC_BCR2_WAITCFG   0x00000800U
 
#define FMC_BCR2_WREN   0x00001000U
 
#define FMC_BCR2_WAITEN   0x00002000U
 
#define FMC_BCR2_EXTMOD   0x00004000U
 
#define FMC_BCR2_ASYNCWAIT   0x00008000U
 
#define FMC_BCR2_CPSIZE   0x00070000U
 
#define FMC_BCR2_CPSIZE_0   0x00010000U
 
#define FMC_BCR2_CPSIZE_1   0x00020000U
 
#define FMC_BCR2_CPSIZE_2   0x00040000U
 
#define FMC_BCR2_CBURSTRW   0x00080000U
 
#define FMC_BCR3_MBKEN   0x00000001U
 
#define FMC_BCR3_MUXEN   0x00000002U
 
#define FMC_BCR3_MTYP   0x0000000CU
 
#define FMC_BCR3_MTYP_0   0x00000004U
 
#define FMC_BCR3_MTYP_1   0x00000008U
 
#define FMC_BCR3_MWID   0x00000030U
 
#define FMC_BCR3_MWID_0   0x00000010U
 
#define FMC_BCR3_MWID_1   0x00000020U
 
#define FMC_BCR3_FACCEN   0x00000040U
 
#define FMC_BCR3_BURSTEN   0x00000100U
 
#define FMC_BCR3_WAITPOL   0x00000200U
 
#define FMC_BCR3_WRAPMOD   0x00000400U
 
#define FMC_BCR3_WAITCFG   0x00000800U
 
#define FMC_BCR3_WREN   0x00001000U
 
#define FMC_BCR3_WAITEN   0x00002000U
 
#define FMC_BCR3_EXTMOD   0x00004000U
 
#define FMC_BCR3_ASYNCWAIT   0x00008000U
 
#define FMC_BCR3_CPSIZE   0x00070000U
 
#define FMC_BCR3_CPSIZE_0   0x00010000U
 
#define FMC_BCR3_CPSIZE_1   0x00020000U
 
#define FMC_BCR3_CPSIZE_2   0x00040000U
 
#define FMC_BCR3_CBURSTRW   0x00080000U
 
#define FMC_BCR4_MBKEN   0x00000001U
 
#define FMC_BCR4_MUXEN   0x00000002U
 
#define FMC_BCR4_MTYP   0x0000000CU
 
#define FMC_BCR4_MTYP_0   0x00000004U
 
#define FMC_BCR4_MTYP_1   0x00000008U
 
#define FMC_BCR4_MWID   0x00000030U
 
#define FMC_BCR4_MWID_0   0x00000010U
 
#define FMC_BCR4_MWID_1   0x00000020U
 
#define FMC_BCR4_FACCEN   0x00000040U
 
#define FMC_BCR4_BURSTEN   0x00000100U
 
#define FMC_BCR4_WAITPOL   0x00000200U
 
#define FMC_BCR4_WRAPMOD   0x00000400U
 
#define FMC_BCR4_WAITCFG   0x00000800U
 
#define FMC_BCR4_WREN   0x00001000U
 
#define FMC_BCR4_WAITEN   0x00002000U
 
#define FMC_BCR4_EXTMOD   0x00004000U
 
#define FMC_BCR4_ASYNCWAIT   0x00008000U
 
#define FMC_BCR4_CPSIZE   0x00070000U
 
#define FMC_BCR4_CPSIZE_0   0x00010000U
 
#define FMC_BCR4_CPSIZE_1   0x00020000U
 
#define FMC_BCR4_CPSIZE_2   0x00040000U
 
#define FMC_BCR4_CBURSTRW   0x00080000U
 
#define FMC_BTR1_ADDSET   0x0000000FU
 
#define FMC_BTR1_ADDSET_0   0x00000001U
 
#define FMC_BTR1_ADDSET_1   0x00000002U
 
#define FMC_BTR1_ADDSET_2   0x00000004U
 
#define FMC_BTR1_ADDSET_3   0x00000008U
 
#define FMC_BTR1_ADDHLD   0x000000F0U
 
#define FMC_BTR1_ADDHLD_0   0x00000010U
 
#define FMC_BTR1_ADDHLD_1   0x00000020U
 
#define FMC_BTR1_ADDHLD_2   0x00000040U
 
#define FMC_BTR1_ADDHLD_3   0x00000080U
 
#define FMC_BTR1_DATAST   0x0000FF00U
 
#define FMC_BTR1_DATAST_0   0x00000100U
 
#define FMC_BTR1_DATAST_1   0x00000200U
 
#define FMC_BTR1_DATAST_2   0x00000400U
 
#define FMC_BTR1_DATAST_3   0x00000800U
 
#define FMC_BTR1_DATAST_4   0x00001000U
 
#define FMC_BTR1_DATAST_5   0x00002000U
 
#define FMC_BTR1_DATAST_6   0x00004000U
 
#define FMC_BTR1_DATAST_7   0x00008000U
 
#define FMC_BTR1_BUSTURN   0x000F0000U
 
#define FMC_BTR1_BUSTURN_0   0x00010000U
 
#define FMC_BTR1_BUSTURN_1   0x00020000U
 
#define FMC_BTR1_BUSTURN_2   0x00040000U
 
#define FMC_BTR1_BUSTURN_3   0x00080000U
 
#define FMC_BTR1_CLKDIV   0x00F00000U
 
#define FMC_BTR1_CLKDIV_0   0x00100000U
 
#define FMC_BTR1_CLKDIV_1   0x00200000U
 
#define FMC_BTR1_CLKDIV_2   0x00400000U
 
#define FMC_BTR1_CLKDIV_3   0x00800000U
 
#define FMC_BTR1_DATLAT   0x0F000000U
 
#define FMC_BTR1_DATLAT_0   0x01000000U
 
#define FMC_BTR1_DATLAT_1   0x02000000U
 
#define FMC_BTR1_DATLAT_2   0x04000000U
 
#define FMC_BTR1_DATLAT_3   0x08000000U
 
#define FMC_BTR1_ACCMOD   0x30000000U
 
#define FMC_BTR1_ACCMOD_0   0x10000000U
 
#define FMC_BTR1_ACCMOD_1   0x20000000U
 
#define FMC_BTR2_ADDSET   0x0000000FU
 
#define FMC_BTR2_ADDSET_0   0x00000001U
 
#define FMC_BTR2_ADDSET_1   0x00000002U
 
#define FMC_BTR2_ADDSET_2   0x00000004U
 
#define FMC_BTR2_ADDSET_3   0x00000008U
 
#define FMC_BTR2_ADDHLD   0x000000F0U
 
#define FMC_BTR2_ADDHLD_0   0x00000010U
 
#define FMC_BTR2_ADDHLD_1   0x00000020U
 
#define FMC_BTR2_ADDHLD_2   0x00000040U
 
#define FMC_BTR2_ADDHLD_3   0x00000080U
 
#define FMC_BTR2_DATAST   0x0000FF00U
 
#define FMC_BTR2_DATAST_0   0x00000100U
 
#define FMC_BTR2_DATAST_1   0x00000200U
 
#define FMC_BTR2_DATAST_2   0x00000400U
 
#define FMC_BTR2_DATAST_3   0x00000800U
 
#define FMC_BTR2_DATAST_4   0x00001000U
 
#define FMC_BTR2_DATAST_5   0x00002000U
 
#define FMC_BTR2_DATAST_6   0x00004000U
 
#define FMC_BTR2_DATAST_7   0x00008000U
 
#define FMC_BTR2_BUSTURN   0x000F0000U
 
#define FMC_BTR2_BUSTURN_0   0x00010000U
 
#define FMC_BTR2_BUSTURN_1   0x00020000U
 
#define FMC_BTR2_BUSTURN_2   0x00040000U
 
#define FMC_BTR2_BUSTURN_3   0x00080000U
 
#define FMC_BTR2_CLKDIV   0x00F00000U
 
#define FMC_BTR2_CLKDIV_0   0x00100000U
 
#define FMC_BTR2_CLKDIV_1   0x00200000U
 
#define FMC_BTR2_CLKDIV_2   0x00400000U
 
#define FMC_BTR2_CLKDIV_3   0x00800000U
 
#define FMC_BTR2_DATLAT   0x0F000000U
 
#define FMC_BTR2_DATLAT_0   0x01000000U
 
#define FMC_BTR2_DATLAT_1   0x02000000U
 
#define FMC_BTR2_DATLAT_2   0x04000000U
 
#define FMC_BTR2_DATLAT_3   0x08000000U
 
#define FMC_BTR2_ACCMOD   0x30000000U
 
#define FMC_BTR2_ACCMOD_0   0x10000000U
 
#define FMC_BTR2_ACCMOD_1   0x20000000U
 
#define FMC_BTR3_ADDSET   0x0000000FU
 
#define FMC_BTR3_ADDSET_0   0x00000001U
 
#define FMC_BTR3_ADDSET_1   0x00000002U
 
#define FMC_BTR3_ADDSET_2   0x00000004U
 
#define FMC_BTR3_ADDSET_3   0x00000008U
 
#define FMC_BTR3_ADDHLD   0x000000F0U
 
#define FMC_BTR3_ADDHLD_0   0x00000010U
 
#define FMC_BTR3_ADDHLD_1   0x00000020U
 
#define FMC_BTR3_ADDHLD_2   0x00000040U
 
#define FMC_BTR3_ADDHLD_3   0x00000080U
 
#define FMC_BTR3_DATAST   0x0000FF00U
 
#define FMC_BTR3_DATAST_0   0x00000100U
 
#define FMC_BTR3_DATAST_1   0x00000200U
 
#define FMC_BTR3_DATAST_2   0x00000400U
 
#define FMC_BTR3_DATAST_3   0x00000800U
 
#define FMC_BTR3_DATAST_4   0x00001000U
 
#define FMC_BTR3_DATAST_5   0x00002000U
 
#define FMC_BTR3_DATAST_6   0x00004000U
 
#define FMC_BTR3_DATAST_7   0x00008000U
 
#define FMC_BTR3_BUSTURN   0x000F0000U
 
#define FMC_BTR3_BUSTURN_0   0x00010000U
 
#define FMC_BTR3_BUSTURN_1   0x00020000U
 
#define FMC_BTR3_BUSTURN_2   0x00040000U
 
#define FMC_BTR3_BUSTURN_3   0x00080000U
 
#define FMC_BTR3_CLKDIV   0x00F00000U
 
#define FMC_BTR3_CLKDIV_0   0x00100000U
 
#define FMC_BTR3_CLKDIV_1   0x00200000U
 
#define FMC_BTR3_CLKDIV_2   0x00400000U
 
#define FMC_BTR3_CLKDIV_3   0x00800000U
 
#define FMC_BTR3_DATLAT   0x0F000000U
 
#define FMC_BTR3_DATLAT_0   0x01000000U
 
#define FMC_BTR3_DATLAT_1   0x02000000U
 
#define FMC_BTR3_DATLAT_2   0x04000000U
 
#define FMC_BTR3_DATLAT_3   0x08000000U
 
#define FMC_BTR3_ACCMOD   0x30000000U
 
#define FMC_BTR3_ACCMOD_0   0x10000000U
 
#define FMC_BTR3_ACCMOD_1   0x20000000U
 
#define FMC_BTR4_ADDSET   0x0000000FU
 
#define FMC_BTR4_ADDSET_0   0x00000001U
 
#define FMC_BTR4_ADDSET_1   0x00000002U
 
#define FMC_BTR4_ADDSET_2   0x00000004U
 
#define FMC_BTR4_ADDSET_3   0x00000008U
 
#define FMC_BTR4_ADDHLD   0x000000F0U
 
#define FMC_BTR4_ADDHLD_0   0x00000010U
 
#define FMC_BTR4_ADDHLD_1   0x00000020U
 
#define FMC_BTR4_ADDHLD_2   0x00000040U
 
#define FMC_BTR4_ADDHLD_3   0x00000080U
 
#define FMC_BTR4_DATAST   0x0000FF00U
 
#define FMC_BTR4_DATAST_0   0x00000100U
 
#define FMC_BTR4_DATAST_1   0x00000200U
 
#define FMC_BTR4_DATAST_2   0x00000400U
 
#define FMC_BTR4_DATAST_3   0x00000800U
 
#define FMC_BTR4_DATAST_4   0x00001000U
 
#define FMC_BTR4_DATAST_5   0x00002000U
 
#define FMC_BTR4_DATAST_6   0x00004000U
 
#define FMC_BTR4_DATAST_7   0x00008000U
 
#define FMC_BTR4_BUSTURN   0x000F0000U
 
#define FMC_BTR4_BUSTURN_0   0x00010000U
 
#define FMC_BTR4_BUSTURN_1   0x00020000U
 
#define FMC_BTR4_BUSTURN_2   0x00040000U
 
#define FMC_BTR4_BUSTURN_3   0x00080000U
 
#define FMC_BTR4_CLKDIV   0x00F00000U
 
#define FMC_BTR4_CLKDIV_0   0x00100000U
 
#define FMC_BTR4_CLKDIV_1   0x00200000U
 
#define FMC_BTR4_CLKDIV_2   0x00400000U
 
#define FMC_BTR4_CLKDIV_3   0x00800000U
 
#define FMC_BTR4_DATLAT   0x0F000000U
 
#define FMC_BTR4_DATLAT_0   0x01000000U
 
#define FMC_BTR4_DATLAT_1   0x02000000U
 
#define FMC_BTR4_DATLAT_2   0x04000000U
 
#define FMC_BTR4_DATLAT_3   0x08000000U
 
#define FMC_BTR4_ACCMOD   0x30000000U
 
#define FMC_BTR4_ACCMOD_0   0x10000000U
 
#define FMC_BTR4_ACCMOD_1   0x20000000U
 
#define FMC_BWTR1_ADDSET   0x0000000FU
 
#define FMC_BWTR1_ADDSET_0   0x00000001U
 
#define FMC_BWTR1_ADDSET_1   0x00000002U
 
#define FMC_BWTR1_ADDSET_2   0x00000004U
 
#define FMC_BWTR1_ADDSET_3   0x00000008U
 
#define FMC_BWTR1_ADDHLD   0x000000F0U
 
#define FMC_BWTR1_ADDHLD_0   0x00000010U
 
#define FMC_BWTR1_ADDHLD_1   0x00000020U
 
#define FMC_BWTR1_ADDHLD_2   0x00000040U
 
#define FMC_BWTR1_ADDHLD_3   0x00000080U
 
#define FMC_BWTR1_DATAST   0x0000FF00U
 
#define FMC_BWTR1_DATAST_0   0x00000100U
 
#define FMC_BWTR1_DATAST_1   0x00000200U
 
#define FMC_BWTR1_DATAST_2   0x00000400U
 
#define FMC_BWTR1_DATAST_3   0x00000800U
 
#define FMC_BWTR1_DATAST_4   0x00001000U
 
#define FMC_BWTR1_DATAST_5   0x00002000U
 
#define FMC_BWTR1_DATAST_6   0x00004000U
 
#define FMC_BWTR1_DATAST_7   0x00008000U
 
#define FMC_BWTR1_BUSTURN   0x000F0000U
 
#define FMC_BWTR1_BUSTURN_0   0x00010000U
 
#define FMC_BWTR1_BUSTURN_1   0x00020000U
 
#define FMC_BWTR1_BUSTURN_2   0x00040000U
 
#define FMC_BWTR1_BUSTURN_3   0x00080000U
 
#define FMC_BWTR1_ACCMOD   0x30000000U
 
#define FMC_BWTR1_ACCMOD_0   0x10000000U
 
#define FMC_BWTR1_ACCMOD_1   0x20000000U
 
#define FMC_BWTR2_ADDSET   0x0000000FU
 
#define FMC_BWTR2_ADDSET_0   0x00000001U
 
#define FMC_BWTR2_ADDSET_1   0x00000002U
 
#define FMC_BWTR2_ADDSET_2   0x00000004U
 
#define FMC_BWTR2_ADDSET_3   0x00000008U
 
#define FMC_BWTR2_ADDHLD   0x000000F0U
 
#define FMC_BWTR2_ADDHLD_0   0x00000010U
 
#define FMC_BWTR2_ADDHLD_1   0x00000020U
 
#define FMC_BWTR2_ADDHLD_2   0x00000040U
 
#define FMC_BWTR2_ADDHLD_3   0x00000080U
 
#define FMC_BWTR2_DATAST   0x0000FF00U
 
#define FMC_BWTR2_DATAST_0   0x00000100U
 
#define FMC_BWTR2_DATAST_1   0x00000200U
 
#define FMC_BWTR2_DATAST_2   0x00000400U
 
#define FMC_BWTR2_DATAST_3   0x00000800U
 
#define FMC_BWTR2_DATAST_4   0x00001000U
 
#define FMC_BWTR2_DATAST_5   0x00002000U
 
#define FMC_BWTR2_DATAST_6   0x00004000U
 
#define FMC_BWTR2_DATAST_7   0x00008000U
 
#define FMC_BWTR2_BUSTURN   0x000F0000U
 
#define FMC_BWTR2_BUSTURN_0   0x00010000U
 
#define FMC_BWTR2_BUSTURN_1   0x00020000U
 
#define FMC_BWTR2_BUSTURN_2   0x00040000U
 
#define FMC_BWTR2_BUSTURN_3   0x00080000U
 
#define FMC_BWTR2_ACCMOD   0x30000000U
 
#define FMC_BWTR2_ACCMOD_0   0x10000000U
 
#define FMC_BWTR2_ACCMOD_1   0x20000000U
 
#define FMC_BWTR3_ADDSET   0x0000000FU
 
#define FMC_BWTR3_ADDSET_0   0x00000001U
 
#define FMC_BWTR3_ADDSET_1   0x00000002U
 
#define FMC_BWTR3_ADDSET_2   0x00000004U
 
#define FMC_BWTR3_ADDSET_3   0x00000008U
 
#define FMC_BWTR3_ADDHLD   0x000000F0U
 
#define FMC_BWTR3_ADDHLD_0   0x00000010U
 
#define FMC_BWTR3_ADDHLD_1   0x00000020U
 
#define FMC_BWTR3_ADDHLD_2   0x00000040U
 
#define FMC_BWTR3_ADDHLD_3   0x00000080U
 
#define FMC_BWTR3_DATAST   0x0000FF00U
 
#define FMC_BWTR3_DATAST_0   0x00000100U
 
#define FMC_BWTR3_DATAST_1   0x00000200U
 
#define FMC_BWTR3_DATAST_2   0x00000400U
 
#define FMC_BWTR3_DATAST_3   0x00000800U
 
#define FMC_BWTR3_DATAST_4   0x00001000U
 
#define FMC_BWTR3_DATAST_5   0x00002000U
 
#define FMC_BWTR3_DATAST_6   0x00004000U
 
#define FMC_BWTR3_DATAST_7   0x00008000U
 
#define FMC_BWTR3_BUSTURN   0x000F0000U
 
#define FMC_BWTR3_BUSTURN_0   0x00010000U
 
#define FMC_BWTR3_BUSTURN_1   0x00020000U
 
#define FMC_BWTR3_BUSTURN_2   0x00040000U
 
#define FMC_BWTR3_BUSTURN_3   0x00080000U
 
#define FMC_BWTR3_ACCMOD   0x30000000U
 
#define FMC_BWTR3_ACCMOD_0   0x10000000U
 
#define FMC_BWTR3_ACCMOD_1   0x20000000U
 
#define FMC_BWTR4_ADDSET   0x0000000FU
 
#define FMC_BWTR4_ADDSET_0   0x00000001U
 
#define FMC_BWTR4_ADDSET_1   0x00000002U
 
#define FMC_BWTR4_ADDSET_2   0x00000004U
 
#define FMC_BWTR4_ADDSET_3   0x00000008U
 
#define FMC_BWTR4_ADDHLD   0x000000F0U
 
#define FMC_BWTR4_ADDHLD_0   0x00000010U
 
#define FMC_BWTR4_ADDHLD_1   0x00000020U
 
#define FMC_BWTR4_ADDHLD_2   0x00000040U
 
#define FMC_BWTR4_ADDHLD_3   0x00000080U
 
#define FMC_BWTR4_DATAST   0x0000FF00U
 
#define FMC_BWTR4_DATAST_0   0x00000100U
 
#define FMC_BWTR4_DATAST_1   0x00000200U
 
#define FMC_BWTR4_DATAST_2   0x00000400U
 
#define FMC_BWTR4_DATAST_3   0x00000800U
 
#define FMC_BWTR4_DATAST_4   0x00001000U
 
#define FMC_BWTR4_DATAST_5   0x00002000U
 
#define FMC_BWTR4_DATAST_6   0x00004000U
 
#define FMC_BWTR4_DATAST_7   0x00008000U
 
#define FMC_BWTR4_BUSTURN   0x000F0000U
 
#define FMC_BWTR4_BUSTURN_0   0x00010000U
 
#define FMC_BWTR4_BUSTURN_1   0x00020000U
 
#define FMC_BWTR4_BUSTURN_2   0x00040000U
 
#define FMC_BWTR4_BUSTURN_3   0x00080000U
 
#define FMC_BWTR4_ACCMOD   0x30000000U
 
#define FMC_BWTR4_ACCMOD_0   0x10000000U
 
#define FMC_BWTR4_ACCMOD_1   0x20000000U
 
#define FMC_PCR_PWAITEN   0x00000002U
 
#define FMC_PCR_PBKEN   0x00000004U
 
#define FMC_PCR_PTYP   0x00000008U
 
#define FMC_PCR_PWID   0x00000030U
 
#define FMC_PCR_PWID_0   0x00000010U
 
#define FMC_PCR_PWID_1   0x00000020U
 
#define FMC_PCR_ECCEN   0x00000040U
 
#define FMC_PCR_TCLR   0x00001E00U
 
#define FMC_PCR_TCLR_0   0x00000200U
 
#define FMC_PCR_TCLR_1   0x00000400U
 
#define FMC_PCR_TCLR_2   0x00000800U
 
#define FMC_PCR_TCLR_3   0x00001000U
 
#define FMC_PCR_TAR   0x0001E000U
 
#define FMC_PCR_TAR_0   0x00002000U
 
#define FMC_PCR_TAR_1   0x00004000U
 
#define FMC_PCR_TAR_2   0x00008000U
 
#define FMC_PCR_TAR_3   0x00010000U
 
#define FMC_PCR_ECCPS   0x000E0000U
 
#define FMC_PCR_ECCPS_0   0x00020000U
 
#define FMC_PCR_ECCPS_1   0x00040000U
 
#define FMC_PCR_ECCPS_2   0x00080000U
 
#define FMC_SR_IRS   0x01U
 
#define FMC_SR_ILS   0x02U
 
#define FMC_SR_IFS   0x04U
 
#define FMC_SR_IREN   0x08U
 
#define FMC_SR_ILEN   0x10U
 
#define FMC_SR_IFEN   0x20U
 
#define FMC_SR_FEMPT   0x40U
 
#define FMC_PMEM_MEMSET3   0x000000FFU
 
#define FMC_PMEM_MEMSET3_0   0x00000001U
 
#define FMC_PMEM_MEMSET3_1   0x00000002U
 
#define FMC_PMEM_MEMSET3_2   0x00000004U
 
#define FMC_PMEM_MEMSET3_3   0x00000008U
 
#define FMC_PMEM_MEMSET3_4   0x00000010U
 
#define FMC_PMEM_MEMSET3_5   0x00000020U
 
#define FMC_PMEM_MEMSET3_6   0x00000040U
 
#define FMC_PMEM_MEMSET3_7   0x00000080U
 
#define FMC_PMEM_MEMWAIT3   0x0000FF00U
 
#define FMC_PMEM_MEMWAIT3_0   0x00000100U
 
#define FMC_PMEM_MEMWAIT3_1   0x00000200U
 
#define FMC_PMEM_MEMWAIT3_2   0x00000400U
 
#define FMC_PMEM_MEMWAIT3_3   0x00000800U
 
#define FMC_PMEM_MEMWAIT3_4   0x00001000U
 
#define FMC_PMEM_MEMWAIT3_5   0x00002000U
 
#define FMC_PMEM_MEMWAIT3_6   0x00004000U
 
#define FMC_PMEM_MEMWAIT3_7   0x00008000U
 
#define FMC_PMEM_MEMHOLD3   0x00FF0000U
 
#define FMC_PMEM_MEMHOLD3_0   0x00010000U
 
#define FMC_PMEM_MEMHOLD3_1   0x00020000U
 
#define FMC_PMEM_MEMHOLD3_2   0x00040000U
 
#define FMC_PMEM_MEMHOLD3_3   0x00080000U
 
#define FMC_PMEM_MEMHOLD3_4   0x00100000U
 
#define FMC_PMEM_MEMHOLD3_5   0x00200000U
 
#define FMC_PMEM_MEMHOLD3_6   0x00400000U
 
#define FMC_PMEM_MEMHOLD3_7   0x00800000U
 
#define FMC_PMEM_MEMHIZ3   0xFF000000U
 
#define FMC_PMEM_MEMHIZ3_0   0x01000000U
 
#define FMC_PMEM_MEMHIZ3_1   0x02000000U
 
#define FMC_PMEM_MEMHIZ3_2   0x04000000U
 
#define FMC_PMEM_MEMHIZ3_3   0x08000000U
 
#define FMC_PMEM_MEMHIZ3_4   0x10000000U
 
#define FMC_PMEM_MEMHIZ3_5   0x20000000U
 
#define FMC_PMEM_MEMHIZ3_6   0x40000000U
 
#define FMC_PMEM_MEMHIZ3_7   0x80000000U
 
#define FMC_PATT_ATTSET3   0x000000FFU
 
#define FMC_PATT_ATTSET3_0   0x00000001U
 
#define FMC_PATT_ATTSET3_1   0x00000002U
 
#define FMC_PATT_ATTSET3_2   0x00000004U
 
#define FMC_PATT_ATTSET3_3   0x00000008U
 
#define FMC_PATT_ATTSET3_4   0x00000010U
 
#define FMC_PATT_ATTSET3_5   0x00000020U
 
#define FMC_PATT_ATTSET3_6   0x00000040U
 
#define FMC_PATT_ATTSET3_7   0x00000080U
 
#define FMC_PATT_ATTWAIT3   0x0000FF00U
 
#define FMC_PATT_ATTWAIT3_0   0x00000100U
 
#define FMC_PATT_ATTWAIT3_1   0x00000200U
 
#define FMC_PATT_ATTWAIT3_2   0x00000400U
 
#define FMC_PATT_ATTWAIT3_3   0x00000800U
 
#define FMC_PATT_ATTWAIT3_4   0x00001000U
 
#define FMC_PATT_ATTWAIT3_5   0x00002000U
 
#define FMC_PATT_ATTWAIT3_6   0x00004000U
 
#define FMC_PATT_ATTWAIT3_7   0x00008000U
 
#define FMC_PATT_ATTHOLD3   0x00FF0000U
 
#define FMC_PATT_ATTHOLD3_0   0x00010000U
 
#define FMC_PATT_ATTHOLD3_1   0x00020000U
 
#define FMC_PATT_ATTHOLD3_2   0x00040000U
 
#define FMC_PATT_ATTHOLD3_3   0x00080000U
 
#define FMC_PATT_ATTHOLD3_4   0x00100000U
 
#define FMC_PATT_ATTHOLD3_5   0x00200000U
 
#define FMC_PATT_ATTHOLD3_6   0x00400000U
 
#define FMC_PATT_ATTHOLD3_7   0x00800000U
 
#define FMC_PATT_ATTHIZ3   0xFF000000U
 
#define FMC_PATT_ATTHIZ3_0   0x01000000U
 
#define FMC_PATT_ATTHIZ3_1   0x02000000U
 
#define FMC_PATT_ATTHIZ3_2   0x04000000U
 
#define FMC_PATT_ATTHIZ3_3   0x08000000U
 
#define FMC_PATT_ATTHIZ3_4   0x10000000U
 
#define FMC_PATT_ATTHIZ3_5   0x20000000U
 
#define FMC_PATT_ATTHIZ3_6   0x40000000U
 
#define FMC_PATT_ATTHIZ3_7   0x80000000U
 
#define FMC_ECCR_ECC3   0xFFFFFFFFU
 
#define FMC_SDCR1_NC   0x00000003U
 
#define FMC_SDCR1_NC_0   0x00000001U
 
#define FMC_SDCR1_NC_1   0x00000002U
 
#define FMC_SDCR1_NR   0x0000000CU
 
#define FMC_SDCR1_NR_0   0x00000004U
 
#define FMC_SDCR1_NR_1   0x00000008U
 
#define FMC_SDCR1_MWID   0x00000030U
 
#define FMC_SDCR1_MWID_0   0x00000010U
 
#define FMC_SDCR1_MWID_1   0x00000020U
 
#define FMC_SDCR1_NB   0x00000040U
 
#define FMC_SDCR1_CAS   0x00000180U
 
#define FMC_SDCR1_CAS_0   0x00000080U
 
#define FMC_SDCR1_CAS_1   0x00000100U
 
#define FMC_SDCR1_WP   0x00000200U
 
#define FMC_SDCR1_SDCLK   0x00000C00U
 
#define FMC_SDCR1_SDCLK_0   0x00000400U
 
#define FMC_SDCR1_SDCLK_1   0x00000800U
 
#define FMC_SDCR1_RBURST   0x00001000U
 
#define FMC_SDCR1_RPIPE   0x00006000U
 
#define FMC_SDCR1_RPIPE_0   0x00002000U
 
#define FMC_SDCR1_RPIPE_1   0x00004000U
 
#define FMC_SDCR2_NC   0x00000003U
 
#define FMC_SDCR2_NC_0   0x00000001U
 
#define FMC_SDCR2_NC_1   0x00000002U
 
#define FMC_SDCR2_NR   0x0000000CU
 
#define FMC_SDCR2_NR_0   0x00000004U
 
#define FMC_SDCR2_NR_1   0x00000008U
 
#define FMC_SDCR2_MWID   0x00000030U
 
#define FMC_SDCR2_MWID_0   0x00000010U
 
#define FMC_SDCR2_MWID_1   0x00000020U
 
#define FMC_SDCR2_NB   0x00000040U
 
#define FMC_SDCR2_CAS   0x00000180U
 
#define FMC_SDCR2_CAS_0   0x00000080U
 
#define FMC_SDCR2_CAS_1   0x00000100U
 
#define FMC_SDCR2_WP   0x00000200U
 
#define FMC_SDCR2_SDCLK   0x00000C00U
 
#define FMC_SDCR2_SDCLK_0   0x00000400U
 
#define FMC_SDCR2_SDCLK_1   0x00000800U
 
#define FMC_SDCR2_RBURST   0x00001000U
 
#define FMC_SDCR2_RPIPE   0x00006000U
 
#define FMC_SDCR2_RPIPE_0   0x00002000U
 
#define FMC_SDCR2_RPIPE_1   0x00004000U
 
#define FMC_SDTR1_TMRD   0x0000000FU
 
#define FMC_SDTR1_TMRD_0   0x00000001U
 
#define FMC_SDTR1_TMRD_1   0x00000002U
 
#define FMC_SDTR1_TMRD_2   0x00000004U
 
#define FMC_SDTR1_TMRD_3   0x00000008U
 
#define FMC_SDTR1_TXSR   0x000000F0U
 
#define FMC_SDTR1_TXSR_0   0x00000010U
 
#define FMC_SDTR1_TXSR_1   0x00000020U
 
#define FMC_SDTR1_TXSR_2   0x00000040U
 
#define FMC_SDTR1_TXSR_3   0x00000080U
 
#define FMC_SDTR1_TRAS   0x00000F00U
 
#define FMC_SDTR1_TRAS_0   0x00000100U
 
#define FMC_SDTR1_TRAS_1   0x00000200U
 
#define FMC_SDTR1_TRAS_2   0x00000400U
 
#define FMC_SDTR1_TRAS_3   0x00000800U
 
#define FMC_SDTR1_TRC   0x0000F000U
 
#define FMC_SDTR1_TRC_0   0x00001000U
 
#define FMC_SDTR1_TRC_1   0x00002000U
 
#define FMC_SDTR1_TRC_2   0x00004000U
 
#define FMC_SDTR1_TWR   0x000F0000U
 
#define FMC_SDTR1_TWR_0   0x00010000U
 
#define FMC_SDTR1_TWR_1   0x00020000U
 
#define FMC_SDTR1_TWR_2   0x00040000U
 
#define FMC_SDTR1_TRP   0x00F00000U
 
#define FMC_SDTR1_TRP_0   0x00100000U
 
#define FMC_SDTR1_TRP_1   0x00200000U
 
#define FMC_SDTR1_TRP_2   0x00400000U
 
#define FMC_SDTR1_TRCD   0x0F000000U
 
#define FMC_SDTR1_TRCD_0   0x01000000U
 
#define FMC_SDTR1_TRCD_1   0x02000000U
 
#define FMC_SDTR1_TRCD_2   0x04000000U
 
#define FMC_SDTR2_TMRD   0x0000000FU
 
#define FMC_SDTR2_TMRD_0   0x00000001U
 
#define FMC_SDTR2_TMRD_1   0x00000002U
 
#define FMC_SDTR2_TMRD_2   0x00000004U
 
#define FMC_SDTR2_TMRD_3   0x00000008U
 
#define FMC_SDTR2_TXSR   0x000000F0U
 
#define FMC_SDTR2_TXSR_0   0x00000010U
 
#define FMC_SDTR2_TXSR_1   0x00000020U
 
#define FMC_SDTR2_TXSR_2   0x00000040U
 
#define FMC_SDTR2_TXSR_3   0x00000080U
 
#define FMC_SDTR2_TRAS   0x00000F00U
 
#define FMC_SDTR2_TRAS_0   0x00000100U
 
#define FMC_SDTR2_TRAS_1   0x00000200U
 
#define FMC_SDTR2_TRAS_2   0x00000400U
 
#define FMC_SDTR2_TRAS_3   0x00000800U
 
#define FMC_SDTR2_TRC   0x0000F000U
 
#define FMC_SDTR2_TRC_0   0x00001000U
 
#define FMC_SDTR2_TRC_1   0x00002000U
 
#define FMC_SDTR2_TRC_2   0x00004000U
 
#define FMC_SDTR2_TWR   0x000F0000U
 
#define FMC_SDTR2_TWR_0   0x00010000U
 
#define FMC_SDTR2_TWR_1   0x00020000U
 
#define FMC_SDTR2_TWR_2   0x00040000U
 
#define FMC_SDTR2_TRP   0x00F00000U
 
#define FMC_SDTR2_TRP_0   0x00100000U
 
#define FMC_SDTR2_TRP_1   0x00200000U
 
#define FMC_SDTR2_TRP_2   0x00400000U
 
#define FMC_SDTR2_TRCD   0x0F000000U
 
#define FMC_SDTR2_TRCD_0   0x01000000U
 
#define FMC_SDTR2_TRCD_1   0x02000000U
 
#define FMC_SDTR2_TRCD_2   0x04000000U
 
#define FMC_SDCMR_MODE   0x00000007U
 
#define FMC_SDCMR_MODE_0   0x00000001U
 
#define FMC_SDCMR_MODE_1   0x00000002U
 
#define FMC_SDCMR_MODE_2   0x00000003U
 
#define FMC_SDCMR_CTB2   0x00000008U
 
#define FMC_SDCMR_CTB1   0x00000010U
 
#define FMC_SDCMR_NRFS   0x000001E0U
 
#define FMC_SDCMR_NRFS_0   0x00000020U
 
#define FMC_SDCMR_NRFS_1   0x00000040U
 
#define FMC_SDCMR_NRFS_2   0x00000080U
 
#define FMC_SDCMR_NRFS_3   0x00000100U
 
#define FMC_SDCMR_MRD   0x003FFE00U
 
#define FMC_SDRTR_CRE   0x00000001U
 
#define FMC_SDRTR_COUNT   0x00003FFEU
 
#define FMC_SDRTR_REIE   0x00004000U
 
#define FMC_SDSR_RE   0x00000001U
 
#define FMC_SDSR_MODES1   0x00000006U
 
#define FMC_SDSR_MODES1_0   0x00000002U
 
#define FMC_SDSR_MODES1_1   0x00000004U
 
#define FMC_SDSR_MODES2   0x00000018U
 
#define FMC_SDSR_MODES2_0   0x00000008U
 
#define FMC_SDSR_MODES2_1   0x00000010U
 
#define FMC_SDSR_BUSY   0x00000020U
 
#define GPIO_MODER_MODER0   0x00000003U
 
#define GPIO_MODER_MODER0_0   0x00000001U
 
#define GPIO_MODER_MODER0_1   0x00000002U
 
#define GPIO_MODER_MODER1   0x0000000CU
 
#define GPIO_MODER_MODER1_0   0x00000004U
 
#define GPIO_MODER_MODER1_1   0x00000008U
 
#define GPIO_MODER_MODER2   0x00000030U
 
#define GPIO_MODER_MODER2_0   0x00000010U
 
#define GPIO_MODER_MODER2_1   0x00000020U
 
#define GPIO_MODER_MODER3   0x000000C0U
 
#define GPIO_MODER_MODER3_0   0x00000040U
 
#define GPIO_MODER_MODER3_1   0x00000080U
 
#define GPIO_MODER_MODER4   0x00000300U
 
#define GPIO_MODER_MODER4_0   0x00000100U
 
#define GPIO_MODER_MODER4_1   0x00000200U
 
#define GPIO_MODER_MODER5   0x00000C00U
 
#define GPIO_MODER_MODER5_0   0x00000400U
 
#define GPIO_MODER_MODER5_1   0x00000800U
 
#define GPIO_MODER_MODER6   0x00003000U
 
#define GPIO_MODER_MODER6_0   0x00001000U
 
#define GPIO_MODER_MODER6_1   0x00002000U
 
#define GPIO_MODER_MODER7   0x0000C000U
 
#define GPIO_MODER_MODER7_0   0x00004000U
 
#define GPIO_MODER_MODER7_1   0x00008000U
 
#define GPIO_MODER_MODER8   0x00030000U
 
#define GPIO_MODER_MODER8_0   0x00010000U
 
#define GPIO_MODER_MODER8_1   0x00020000U
 
#define GPIO_MODER_MODER9   0x000C0000U
 
#define GPIO_MODER_MODER9_0   0x00040000U
 
#define GPIO_MODER_MODER9_1   0x00080000U
 
#define GPIO_MODER_MODER10   0x00300000U
 
#define GPIO_MODER_MODER10_0   0x00100000U
 
#define GPIO_MODER_MODER10_1   0x00200000U
 
#define GPIO_MODER_MODER11   0x00C00000U
 
#define GPIO_MODER_MODER11_0   0x00400000U
 
#define GPIO_MODER_MODER11_1   0x00800000U
 
#define GPIO_MODER_MODER12   0x03000000U
 
#define GPIO_MODER_MODER12_0   0x01000000U
 
#define GPIO_MODER_MODER12_1   0x02000000U
 
#define GPIO_MODER_MODER13   0x0C000000U
 
#define GPIO_MODER_MODER13_0   0x04000000U
 
#define GPIO_MODER_MODER13_1   0x08000000U
 
#define GPIO_MODER_MODER14   0x30000000U
 
#define GPIO_MODER_MODER14_0   0x10000000U
 
#define GPIO_MODER_MODER14_1   0x20000000U
 
#define GPIO_MODER_MODER15   0xC0000000U
 
#define GPIO_MODER_MODER15_0   0x40000000U
 
#define GPIO_MODER_MODER15_1   0x80000000U
 
#define GPIO_OTYPER_OT_0   0x00000001U
 
#define GPIO_OTYPER_OT_1   0x00000002U
 
#define GPIO_OTYPER_OT_2   0x00000004U
 
#define GPIO_OTYPER_OT_3   0x00000008U
 
#define GPIO_OTYPER_OT_4   0x00000010U
 
#define GPIO_OTYPER_OT_5   0x00000020U
 
#define GPIO_OTYPER_OT_6   0x00000040U
 
#define GPIO_OTYPER_OT_7   0x00000080U
 
#define GPIO_OTYPER_OT_8   0x00000100U
 
#define GPIO_OTYPER_OT_9   0x00000200U
 
#define GPIO_OTYPER_OT_10   0x00000400U
 
#define GPIO_OTYPER_OT_11   0x00000800U
 
#define GPIO_OTYPER_OT_12   0x00001000U
 
#define GPIO_OTYPER_OT_13   0x00002000U
 
#define GPIO_OTYPER_OT_14   0x00004000U
 
#define GPIO_OTYPER_OT_15   0x00008000U
 
#define GPIO_OSPEEDER_OSPEEDR0   0x00000003U
 
#define GPIO_OSPEEDER_OSPEEDR0_0   0x00000001U
 
#define GPIO_OSPEEDER_OSPEEDR0_1   0x00000002U
 
#define GPIO_OSPEEDER_OSPEEDR1   0x0000000CU
 
#define GPIO_OSPEEDER_OSPEEDR1_0   0x00000004U
 
#define GPIO_OSPEEDER_OSPEEDR1_1   0x00000008U
 
#define GPIO_OSPEEDER_OSPEEDR2   0x00000030U
 
#define GPIO_OSPEEDER_OSPEEDR2_0   0x00000010U
 
#define GPIO_OSPEEDER_OSPEEDR2_1   0x00000020U
 
#define GPIO_OSPEEDER_OSPEEDR3   0x000000C0U
 
#define GPIO_OSPEEDER_OSPEEDR3_0   0x00000040U
 
#define GPIO_OSPEEDER_OSPEEDR3_1   0x00000080U
 
#define GPIO_OSPEEDER_OSPEEDR4   0x00000300U
 
#define GPIO_OSPEEDER_OSPEEDR4_0   0x00000100U
 
#define GPIO_OSPEEDER_OSPEEDR4_1   0x00000200U
 
#define GPIO_OSPEEDER_OSPEEDR5   0x00000C00U
 
#define GPIO_OSPEEDER_OSPEEDR5_0   0x00000400U
 
#define GPIO_OSPEEDER_OSPEEDR5_1   0x00000800U
 
#define GPIO_OSPEEDER_OSPEEDR6   0x00003000U
 
#define GPIO_OSPEEDER_OSPEEDR6_0   0x00001000U
 
#define GPIO_OSPEEDER_OSPEEDR6_1   0x00002000U
 
#define GPIO_OSPEEDER_OSPEEDR7   0x0000C000U
 
#define GPIO_OSPEEDER_OSPEEDR7_0   0x00004000U
 
#define GPIO_OSPEEDER_OSPEEDR7_1   0x00008000U
 
#define GPIO_OSPEEDER_OSPEEDR8   0x00030000U
 
#define GPIO_OSPEEDER_OSPEEDR8_0   0x00010000U
 
#define GPIO_OSPEEDER_OSPEEDR8_1   0x00020000U
 
#define GPIO_OSPEEDER_OSPEEDR9   0x000C0000U
 
#define GPIO_OSPEEDER_OSPEEDR9_0   0x00040000U
 
#define GPIO_OSPEEDER_OSPEEDR9_1   0x00080000U
 
#define GPIO_OSPEEDER_OSPEEDR10   0x00300000U
 
#define GPIO_OSPEEDER_OSPEEDR10_0   0x00100000U
 
#define GPIO_OSPEEDER_OSPEEDR10_1   0x00200000U
 
#define GPIO_OSPEEDER_OSPEEDR11   0x00C00000U
 
#define GPIO_OSPEEDER_OSPEEDR11_0   0x00400000U
 
#define GPIO_OSPEEDER_OSPEEDR11_1   0x00800000U
 
#define GPIO_OSPEEDER_OSPEEDR12   0x03000000U
 
#define GPIO_OSPEEDER_OSPEEDR12_0   0x01000000U
 
#define GPIO_OSPEEDER_OSPEEDR12_1   0x02000000U
 
#define GPIO_OSPEEDER_OSPEEDR13   0x0C000000U
 
#define GPIO_OSPEEDER_OSPEEDR13_0   0x04000000U
 
#define GPIO_OSPEEDER_OSPEEDR13_1   0x08000000U
 
#define GPIO_OSPEEDER_OSPEEDR14   0x30000000U
 
#define GPIO_OSPEEDER_OSPEEDR14_0   0x10000000U
 
#define GPIO_OSPEEDER_OSPEEDR14_1   0x20000000U
 
#define GPIO_OSPEEDER_OSPEEDR15   0xC0000000U
 
#define GPIO_OSPEEDER_OSPEEDR15_0   0x40000000U
 
#define GPIO_OSPEEDER_OSPEEDR15_1   0x80000000U
 
#define GPIO_PUPDR_PUPDR0   0x00000003U
 
#define GPIO_PUPDR_PUPDR0_0   0x00000001U
 
#define GPIO_PUPDR_PUPDR0_1   0x00000002U
 
#define GPIO_PUPDR_PUPDR1   0x0000000CU
 
#define GPIO_PUPDR_PUPDR1_0   0x00000004U
 
#define GPIO_PUPDR_PUPDR1_1   0x00000008U
 
#define GPIO_PUPDR_PUPDR2   0x00000030U
 
#define GPIO_PUPDR_PUPDR2_0   0x00000010U
 
#define GPIO_PUPDR_PUPDR2_1   0x00000020U
 
#define GPIO_PUPDR_PUPDR3   0x000000C0U
 
#define GPIO_PUPDR_PUPDR3_0   0x00000040U
 
#define GPIO_PUPDR_PUPDR3_1   0x00000080U
 
#define GPIO_PUPDR_PUPDR4   0x00000300U
 
#define GPIO_PUPDR_PUPDR4_0   0x00000100U
 
#define GPIO_PUPDR_PUPDR4_1   0x00000200U
 
#define GPIO_PUPDR_PUPDR5   0x00000C00U
 
#define GPIO_PUPDR_PUPDR5_0   0x00000400U
 
#define GPIO_PUPDR_PUPDR5_1   0x00000800U
 
#define GPIO_PUPDR_PUPDR6   0x00003000U
 
#define GPIO_PUPDR_PUPDR6_0   0x00001000U
 
#define GPIO_PUPDR_PUPDR6_1   0x00002000U
 
#define GPIO_PUPDR_PUPDR7   0x0000C000U
 
#define GPIO_PUPDR_PUPDR7_0   0x00004000U
 
#define GPIO_PUPDR_PUPDR7_1   0x00008000U
 
#define GPIO_PUPDR_PUPDR8   0x00030000U
 
#define GPIO_PUPDR_PUPDR8_0   0x00010000U
 
#define GPIO_PUPDR_PUPDR8_1   0x00020000U
 
#define GPIO_PUPDR_PUPDR9   0x000C0000U
 
#define GPIO_PUPDR_PUPDR9_0   0x00040000U
 
#define GPIO_PUPDR_PUPDR9_1   0x00080000U
 
#define GPIO_PUPDR_PUPDR10   0x00300000U
 
#define GPIO_PUPDR_PUPDR10_0   0x00100000U
 
#define GPIO_PUPDR_PUPDR10_1   0x00200000U
 
#define GPIO_PUPDR_PUPDR11   0x00C00000U
 
#define GPIO_PUPDR_PUPDR11_0   0x00400000U
 
#define GPIO_PUPDR_PUPDR11_1   0x00800000U
 
#define GPIO_PUPDR_PUPDR12   0x03000000U
 
#define GPIO_PUPDR_PUPDR12_0   0x01000000U
 
#define GPIO_PUPDR_PUPDR12_1   0x02000000U
 
#define GPIO_PUPDR_PUPDR13   0x0C000000U
 
#define GPIO_PUPDR_PUPDR13_0   0x04000000U
 
#define GPIO_PUPDR_PUPDR13_1   0x08000000U
 
#define GPIO_PUPDR_PUPDR14   0x30000000U
 
#define GPIO_PUPDR_PUPDR14_0   0x10000000U
 
#define GPIO_PUPDR_PUPDR14_1   0x20000000U
 
#define GPIO_PUPDR_PUPDR15   0xC0000000U
 
#define GPIO_PUPDR_PUPDR15_0   0x40000000U
 
#define GPIO_PUPDR_PUPDR15_1   0x80000000U
 
#define GPIO_IDR_IDR_0   0x00000001U
 
#define GPIO_IDR_IDR_1   0x00000002U
 
#define GPIO_IDR_IDR_2   0x00000004U
 
#define GPIO_IDR_IDR_3   0x00000008U
 
#define GPIO_IDR_IDR_4   0x00000010U
 
#define GPIO_IDR_IDR_5   0x00000020U
 
#define GPIO_IDR_IDR_6   0x00000040U
 
#define GPIO_IDR_IDR_7   0x00000080U
 
#define GPIO_IDR_IDR_8   0x00000100U
 
#define GPIO_IDR_IDR_9   0x00000200U
 
#define GPIO_IDR_IDR_10   0x00000400U
 
#define GPIO_IDR_IDR_11   0x00000800U
 
#define GPIO_IDR_IDR_12   0x00001000U
 
#define GPIO_IDR_IDR_13   0x00002000U
 
#define GPIO_IDR_IDR_14   0x00004000U
 
#define GPIO_IDR_IDR_15   0x00008000U
 
#define GPIO_ODR_ODR_0   0x00000001U
 
#define GPIO_ODR_ODR_1   0x00000002U
 
#define GPIO_ODR_ODR_2   0x00000004U
 
#define GPIO_ODR_ODR_3   0x00000008U
 
#define GPIO_ODR_ODR_4   0x00000010U
 
#define GPIO_ODR_ODR_5   0x00000020U
 
#define GPIO_ODR_ODR_6   0x00000040U
 
#define GPIO_ODR_ODR_7   0x00000080U
 
#define GPIO_ODR_ODR_8   0x00000100U
 
#define GPIO_ODR_ODR_9   0x00000200U
 
#define GPIO_ODR_ODR_10   0x00000400U
 
#define GPIO_ODR_ODR_11   0x00000800U
 
#define GPIO_ODR_ODR_12   0x00001000U
 
#define GPIO_ODR_ODR_13   0x00002000U
 
#define GPIO_ODR_ODR_14   0x00004000U
 
#define GPIO_ODR_ODR_15   0x00008000U
 
#define GPIO_BSRR_BS_0   0x00000001U
 
#define GPIO_BSRR_BS_1   0x00000002U
 
#define GPIO_BSRR_BS_2   0x00000004U
 
#define GPIO_BSRR_BS_3   0x00000008U
 
#define GPIO_BSRR_BS_4   0x00000010U
 
#define GPIO_BSRR_BS_5   0x00000020U
 
#define GPIO_BSRR_BS_6   0x00000040U
 
#define GPIO_BSRR_BS_7   0x00000080U
 
#define GPIO_BSRR_BS_8   0x00000100U
 
#define GPIO_BSRR_BS_9   0x00000200U
 
#define GPIO_BSRR_BS_10   0x00000400U
 
#define GPIO_BSRR_BS_11   0x00000800U
 
#define GPIO_BSRR_BS_12   0x00001000U
 
#define GPIO_BSRR_BS_13   0x00002000U
 
#define GPIO_BSRR_BS_14   0x00004000U
 
#define GPIO_BSRR_BS_15   0x00008000U
 
#define GPIO_BSRR_BR_0   0x00010000U
 
#define GPIO_BSRR_BR_1   0x00020000U
 
#define GPIO_BSRR_BR_2   0x00040000U
 
#define GPIO_BSRR_BR_3   0x00080000U
 
#define GPIO_BSRR_BR_4   0x00100000U
 
#define GPIO_BSRR_BR_5   0x00200000U
 
#define GPIO_BSRR_BR_6   0x00400000U
 
#define GPIO_BSRR_BR_7   0x00800000U
 
#define GPIO_BSRR_BR_8   0x01000000U
 
#define GPIO_BSRR_BR_9   0x02000000U
 
#define GPIO_BSRR_BR_10   0x04000000U
 
#define GPIO_BSRR_BR_11   0x08000000U
 
#define GPIO_BSRR_BR_12   0x10000000U
 
#define GPIO_BSRR_BR_13   0x20000000U
 
#define GPIO_BSRR_BR_14   0x40000000U
 
#define GPIO_BSRR_BR_15   0x80000000U
 
#define GPIO_LCKR_LCK0   0x00000001U
 
#define GPIO_LCKR_LCK1   0x00000002U
 
#define GPIO_LCKR_LCK2   0x00000004U
 
#define GPIO_LCKR_LCK3   0x00000008U
 
#define GPIO_LCKR_LCK4   0x00000010U
 
#define GPIO_LCKR_LCK5   0x00000020U
 
#define GPIO_LCKR_LCK6   0x00000040U
 
#define GPIO_LCKR_LCK7   0x00000080U
 
#define GPIO_LCKR_LCK8   0x00000100U
 
#define GPIO_LCKR_LCK9   0x00000200U
 
#define GPIO_LCKR_LCK10   0x00000400U
 
#define GPIO_LCKR_LCK11   0x00000800U
 
#define GPIO_LCKR_LCK12   0x00001000U
 
#define GPIO_LCKR_LCK13   0x00002000U
 
#define GPIO_LCKR_LCK14   0x00004000U
 
#define GPIO_LCKR_LCK15   0x00008000U
 
#define GPIO_LCKR_LCKK   0x00010000U
 
#define I2C_CR1_PE   0x00000001U
 
#define I2C_CR1_TXIE   0x00000002U
 
#define I2C_CR1_RXIE   0x00000004U
 
#define I2C_CR1_ADDRIE   0x00000008U
 
#define I2C_CR1_NACKIE   0x00000010U
 
#define I2C_CR1_STOPIE   0x00000020U
 
#define I2C_CR1_TCIE   0x00000040U
 
#define I2C_CR1_ERRIE   0x00000080U
 
#define I2C_CR1_DNF   0x00000F00U
 
#define I2C_CR1_ANFOFF   0x00001000U
 
#define I2C_CR1_TXDMAEN   0x00004000U
 
#define I2C_CR1_RXDMAEN   0x00008000U
 
#define I2C_CR1_SBC   0x00010000U
 
#define I2C_CR1_NOSTRETCH   0x00020000U
 
#define I2C_CR1_GCEN   0x00080000U
 
#define I2C_CR1_SMBHEN   0x00100000U
 
#define I2C_CR1_SMBDEN   0x00200000U
 
#define I2C_CR1_ALERTEN   0x00400000U
 
#define I2C_CR1_PECEN   0x00800000U
 
#define I2C_CR1_DFN   I2C_CR1_DNF
 
#define I2C_CR2_SADD   0x000003FFU
 
#define I2C_CR2_RD_WRN   0x00000400U
 
#define I2C_CR2_ADD10   0x00000800U
 
#define I2C_CR2_HEAD10R   0x00001000U
 
#define I2C_CR2_START   0x00002000U
 
#define I2C_CR2_STOP   0x00004000U
 
#define I2C_CR2_NACK   0x00008000U
 
#define I2C_CR2_NBYTES   0x00FF0000U
 
#define I2C_CR2_RELOAD   0x01000000U
 
#define I2C_CR2_AUTOEND   0x02000000U
 
#define I2C_CR2_PECBYTE   0x04000000U
 
#define I2C_OAR1_OA1   0x000003FFU
 
#define I2C_OAR1_OA1MODE   0x00000400U
 
#define I2C_OAR1_OA1EN   0x00008000U
 
#define I2C_OAR2_OA2   0x000000FEU
 
#define I2C_OAR2_OA2MSK   0x00000700U
 
#define I2C_OAR2_OA2NOMASK   0x00000000U
 
#define I2C_OAR2_OA2MASK01   0x00000100U
 
#define I2C_OAR2_OA2MASK02   0x00000200U
 
#define I2C_OAR2_OA2MASK03   0x00000300U
 
#define I2C_OAR2_OA2MASK04   0x00000400U
 
#define I2C_OAR2_OA2MASK05   0x00000500U
 
#define I2C_OAR2_OA2MASK06   0x00000600U
 
#define I2C_OAR2_OA2MASK07   0x00000700U
 
#define I2C_OAR2_OA2EN   0x00008000U
 
#define I2C_TIMINGR_SCLL   0x000000FFU
 
#define I2C_TIMINGR_SCLH   0x0000FF00U
 
#define I2C_TIMINGR_SDADEL   0x000F0000U
 
#define I2C_TIMINGR_SCLDEL   0x00F00000U
 
#define I2C_TIMINGR_PRESC   0xF0000000U
 
#define I2C_TIMEOUTR_TIMEOUTA   0x00000FFFU
 
#define I2C_TIMEOUTR_TIDLE   0x00001000U
 
#define I2C_TIMEOUTR_TIMOUTEN   0x00008000U
 
#define I2C_TIMEOUTR_TIMEOUTB   0x0FFF0000U
 
#define I2C_TIMEOUTR_TEXTEN   0x80000000U
 
#define I2C_ISR_TXE   0x00000001U
 
#define I2C_ISR_TXIS   0x00000002U
 
#define I2C_ISR_RXNE   0x00000004U
 
#define I2C_ISR_ADDR   0x00000008U
 
#define I2C_ISR_NACKF   0x00000010U
 
#define I2C_ISR_STOPF   0x00000020U
 
#define I2C_ISR_TC   0x00000040U
 
#define I2C_ISR_TCR   0x00000080U
 
#define I2C_ISR_BERR   0x00000100U
 
#define I2C_ISR_ARLO   0x00000200U
 
#define I2C_ISR_OVR   0x00000400U
 
#define I2C_ISR_PECERR   0x00000800U
 
#define I2C_ISR_TIMEOUT   0x00001000U
 
#define I2C_ISR_ALERT   0x00002000U
 
#define I2C_ISR_BUSY   0x00008000U
 
#define I2C_ISR_DIR   0x00010000U
 
#define I2C_ISR_ADDCODE   0x00FE0000U
 
#define I2C_ICR_ADDRCF   0x00000008U
 
#define I2C_ICR_NACKCF   0x00000010U
 
#define I2C_ICR_STOPCF   0x00000020U
 
#define I2C_ICR_BERRCF   0x00000100U
 
#define I2C_ICR_ARLOCF   0x00000200U
 
#define I2C_ICR_OVRCF   0x00000400U
 
#define I2C_ICR_PECCF   0x00000800U
 
#define I2C_ICR_TIMOUTCF   0x00001000U
 
#define I2C_ICR_ALERTCF   0x00002000U
 
#define I2C_PECR_PEC   0x000000FFU
 
#define I2C_RXDR_RXDATA   0x000000FFU
 
#define I2C_TXDR_TXDATA   0x000000FFU
 
#define IWDG_KR_KEY   0xFFFFU
 
#define IWDG_PR_PR   0x07U
 
#define IWDG_PR_PR_0   0x01U
 
#define IWDG_PR_PR_1   0x02U
 
#define IWDG_PR_PR_2   0x04U
 
#define IWDG_RLR_RL   0x0FFFU
 
#define IWDG_SR_PVU   0x01U
 
#define IWDG_SR_RVU   0x02U
 
#define IWDG_SR_WVU   0x04U
 
#define IWDG_WINR_WIN   0x0FFFU
 
#define LTDC_SSCR_VSH   0x000007FFU
 
#define LTDC_SSCR_HSW   0x0FFF0000U
 
#define LTDC_BPCR_AVBP   0x000007FFU
 
#define LTDC_BPCR_AHBP   0x0FFF0000U
 
#define LTDC_AWCR_AAH   0x000007FFU
 
#define LTDC_AWCR_AAW   0x0FFF0000U
 
#define LTDC_TWCR_TOTALH   0x000007FFU
 
#define LTDC_TWCR_TOTALW   0x0FFF0000U
 
#define LTDC_GCR_LTDCEN   0x00000001U
 
#define LTDC_GCR_DBW   0x00000070U
 
#define LTDC_GCR_DGW   0x00000700U
 
#define LTDC_GCR_DRW   0x00007000U
 
#define LTDC_GCR_DEN   0x00010000U
 
#define LTDC_GCR_PCPOL   0x10000000U
 
#define LTDC_GCR_DEPOL   0x20000000U
 
#define LTDC_GCR_VSPOL   0x40000000U
 
#define LTDC_GCR_HSPOL   0x80000000U
 
#define LTDC_GCR_DTEN   LTDC_GCR_DEN
 
#define LTDC_SRCR_IMR   0x00000001U
 
#define LTDC_SRCR_VBR   0x00000002U
 
#define LTDC_BCCR_BCBLUE   0x000000FFU
 
#define LTDC_BCCR_BCGREEN   0x0000FF00U
 
#define LTDC_BCCR_BCRED   0x00FF0000U
 
#define LTDC_IER_LIE   0x00000001U
 
#define LTDC_IER_FUIE   0x00000002U
 
#define LTDC_IER_TERRIE   0x00000004U
 
#define LTDC_IER_RRIE   0x00000008U
 
#define LTDC_ISR_LIF   0x00000001U
 
#define LTDC_ISR_FUIF   0x00000002U
 
#define LTDC_ISR_TERRIF   0x00000004U
 
#define LTDC_ISR_RRIF   0x00000008U
 
#define LTDC_ICR_CLIF   0x00000001U
 
#define LTDC_ICR_CFUIF   0x00000002U
 
#define LTDC_ICR_CTERRIF   0x00000004U
 
#define LTDC_ICR_CRRIF   0x00000008U
 
#define LTDC_LIPCR_LIPOS   0x000007FFU
 
#define LTDC_CPSR_CYPOS   0x0000FFFFU
 
#define LTDC_CPSR_CXPOS   0xFFFF0000U
 
#define LTDC_CDSR_VDES   0x00000001U
 
#define LTDC_CDSR_HDES   0x00000002U
 
#define LTDC_CDSR_VSYNCS   0x00000004U
 
#define LTDC_CDSR_HSYNCS   0x00000008U
 
#define LTDC_LxCR_LEN   0x00000001U
 
#define LTDC_LxCR_COLKEN   0x00000002U
 
#define LTDC_LxCR_CLUTEN   0x00000010U
 
#define LTDC_LxWHPCR_WHSTPOS   0x00000FFFU
 
#define LTDC_LxWHPCR_WHSPPOS   0xFFFF0000U
 
#define LTDC_LxWVPCR_WVSTPOS   0x00000FFFU
 
#define LTDC_LxWVPCR_WVSPPOS   0xFFFF0000U
 
#define LTDC_LxCKCR_CKBLUE   0x000000FFU
 
#define LTDC_LxCKCR_CKGREEN   0x0000FF00U
 
#define LTDC_LxCKCR_CKRED   0x00FF0000U
 
#define LTDC_LxPFCR_PF   0x00000007U
 
#define LTDC_LxCACR_CONSTA   0x000000FFU
 
#define LTDC_LxDCCR_DCBLUE   0x000000FFU
 
#define LTDC_LxDCCR_DCGREEN   0x0000FF00U
 
#define LTDC_LxDCCR_DCRED   0x00FF0000U
 
#define LTDC_LxDCCR_DCALPHA   0xFF000000U
 
#define LTDC_LxBFCR_BF2   0x00000007U
 
#define LTDC_LxBFCR_BF1   0x00000700U
 
#define LTDC_LxCFBAR_CFBADD   0xFFFFFFFFU
 
#define LTDC_LxCFBLR_CFBLL   0x00001FFFU
 
#define LTDC_LxCFBLR_CFBP   0x1FFF0000U
 
#define LTDC_LxCFBLNR_CFBLNBR   0x000007FFU
 
#define LTDC_LxCLUTWR_BLUE   0x000000FFU
 
#define LTDC_LxCLUTWR_GREEN   0x0000FF00U
 
#define LTDC_LxCLUTWR_RED   0x00FF0000U
 
#define LTDC_LxCLUTWR_CLUTADD   0xFF000000U
 
#define PWR_CR1_LPDS   0x00000001U
 
#define PWR_CR1_PDDS   0x00000002U
 
#define PWR_CR1_CSBF   0x00000008U
 
#define PWR_CR1_PVDE   0x00000010U
 
#define PWR_CR1_PLS   0x000000E0U
 
#define PWR_CR1_PLS_0   0x00000020U
 
#define PWR_CR1_PLS_1   0x00000040U
 
#define PWR_CR1_PLS_2   0x00000080U
 
#define PWR_CR1_PLS_LEV0   0x00000000U
 
#define PWR_CR1_PLS_LEV1   0x00000020U
 
#define PWR_CR1_PLS_LEV2   0x00000040U
 
#define PWR_CR1_PLS_LEV3   0x00000060U
 
#define PWR_CR1_PLS_LEV4   0x00000080U
 
#define PWR_CR1_PLS_LEV5   0x000000A0U
 
#define PWR_CR1_PLS_LEV6   0x000000C0U
 
#define PWR_CR1_PLS_LEV7   0x000000E0U
 
#define PWR_CR1_DBP   0x00000100U
 
#define PWR_CR1_FPDS   0x00000200U
 
#define PWR_CR1_LPUDS   0x00000400U
 
#define PWR_CR1_MRUDS   0x00000800U
 
#define PWR_CR1_ADCDC1   0x00002000U
 
#define PWR_CR1_VOS   0x0000C000U
 
#define PWR_CR1_VOS_0   0x00004000U
 
#define PWR_CR1_VOS_1   0x00008000U
 
#define PWR_CR1_ODEN   0x00010000U
 
#define PWR_CR1_ODSWEN   0x00020000U
 
#define PWR_CR1_UDEN   0x000C0000U
 
#define PWR_CR1_UDEN_0   0x00040000U
 
#define PWR_CR1_UDEN_1   0x00080000U
 
#define PWR_CSR1_WUIF   0x00000001U
 
#define PWR_CSR1_SBF   0x00000002U
 
#define PWR_CSR1_PVDO   0x00000004U
 
#define PWR_CSR1_BRR   0x00000008U
 
#define PWR_CSR1_EIWUP   0x00000100U
 
#define PWR_CSR1_BRE   0x00000200U
 
#define PWR_CSR1_VOSRDY   0x00004000U
 
#define PWR_CSR1_ODRDY   0x00010000U
 
#define PWR_CSR1_ODSWRDY   0x00020000U
 
#define PWR_CSR1_UDRDY   0x000C0000U
 
#define PWR_CSR1_UDSWRDY   PWR_CSR1_UDRDY
 
#define PWR_CR2_CWUPF1   0x00000001U
 
#define PWR_CR2_CWUPF2   0x00000002U
 
#define PWR_CR2_CWUPF3   0x00000004U
 
#define PWR_CR2_CWUPF4   0x00000008U
 
#define PWR_CR2_CWUPF5   0x00000010U
 
#define PWR_CR2_CWUPF6   0x00000020U
 
#define PWR_CR2_WUPP1   0x00000100U
 
#define PWR_CR2_WUPP2   0x00000200U
 
#define PWR_CR2_WUPP3   0x00000400U
 
#define PWR_CR2_WUPP4   0x00000800U
 
#define PWR_CR2_WUPP5   0x00001000U
 
#define PWR_CR2_WUPP6   0x00002000U
 
#define PWR_CSR2_WUPF1   0x00000001U
 
#define PWR_CSR2_WUPF2   0x00000002U
 
#define PWR_CSR2_WUPF3   0x00000004U
 
#define PWR_CSR2_WUPF4   0x00000008U
 
#define PWR_CSR2_WUPF5   0x00000010U
 
#define PWR_CSR2_WUPF6   0x00000020U
 
#define PWR_CSR2_EWUP1   0x00000100U
 
#define PWR_CSR2_EWUP2   0x00000200U
 
#define PWR_CSR2_EWUP3   0x00000400U
 
#define PWR_CSR2_EWUP4   0x00000800U
 
#define PWR_CSR2_EWUP5   0x00001000U
 
#define PWR_CSR2_EWUP6   0x00002000U
 
#define QSPI1_V1_0
 
#define QUADSPI_CR_EN   0x00000001U
 
#define QUADSPI_CR_ABORT   0x00000002U
 
#define QUADSPI_CR_DMAEN   0x00000004U
 
#define QUADSPI_CR_TCEN   0x00000008U
 
#define QUADSPI_CR_SSHIFT   0x00000010U
 
#define QUADSPI_CR_DFM   0x00000040U
 
#define QUADSPI_CR_FSEL   0x00000080U
 
#define QUADSPI_CR_FTHRES   0x00001F00U
 
#define QUADSPI_CR_FTHRES_0   0x00000100U
 
#define QUADSPI_CR_FTHRES_1   0x00000200U
 
#define QUADSPI_CR_FTHRES_2   0x00000400U
 
#define QUADSPI_CR_FTHRES_3   0x00000800U
 
#define QUADSPI_CR_FTHRES_4   0x00001000U
 
#define QUADSPI_CR_TEIE   0x00010000U
 
#define QUADSPI_CR_TCIE   0x00020000U
 
#define QUADSPI_CR_FTIE   0x00040000U
 
#define QUADSPI_CR_SMIE   0x00080000U
 
#define QUADSPI_CR_TOIE   0x00100000U
 
#define QUADSPI_CR_APMS   0x00400000U
 
#define QUADSPI_CR_PMM   0x00800000U
 
#define QUADSPI_CR_PRESCALER   0xFF000000U
 
#define QUADSPI_CR_PRESCALER_0   0x01000000U
 
#define QUADSPI_CR_PRESCALER_1   0x02000000U
 
#define QUADSPI_CR_PRESCALER_2   0x04000000U
 
#define QUADSPI_CR_PRESCALER_3   0x08000000U
 
#define QUADSPI_CR_PRESCALER_4   0x10000000U
 
#define QUADSPI_CR_PRESCALER_5   0x20000000U
 
#define QUADSPI_CR_PRESCALER_6   0x40000000U
 
#define QUADSPI_CR_PRESCALER_7   0x80000000U
 
#define QUADSPI_DCR_CKMODE   0x00000001U
 
#define QUADSPI_DCR_CSHT   0x00000700U
 
#define QUADSPI_DCR_CSHT_0   0x00000100U
 
#define QUADSPI_DCR_CSHT_1   0x00000200U
 
#define QUADSPI_DCR_CSHT_2   0x00000400U
 
#define QUADSPI_DCR_FSIZE   0x001F0000U
 
#define QUADSPI_DCR_FSIZE_0   0x00010000U
 
#define QUADSPI_DCR_FSIZE_1   0x00020000U
 
#define QUADSPI_DCR_FSIZE_2   0x00040000U
 
#define QUADSPI_DCR_FSIZE_3   0x00080000U
 
#define QUADSPI_DCR_FSIZE_4   0x00100000U
 
#define QUADSPI_SR_TEF   0x00000001U
 
#define QUADSPI_SR_TCF   0x00000002U
 
#define QUADSPI_SR_FTF   0x00000004U
 
#define QUADSPI_SR_SMF   0x00000008U
 
#define QUADSPI_SR_TOF   0x00000010U
 
#define QUADSPI_SR_BUSY   0x00000020U
 
#define QUADSPI_SR_FLEVEL   0x00001F00U
 
#define QUADSPI_SR_FLEVEL_0   0x00000100U
 
#define QUADSPI_SR_FLEVEL_1   0x00000200U
 
#define QUADSPI_SR_FLEVEL_2   0x00000400U
 
#define QUADSPI_SR_FLEVEL_3   0x00000800U
 
#define QUADSPI_SR_FLEVEL_4   0x00001000U
 
#define QUADSPI_FCR_CTEF   0x00000001U
 
#define QUADSPI_FCR_CTCF   0x00000002U
 
#define QUADSPI_FCR_CSMF   0x00000008U
 
#define QUADSPI_FCR_CTOF   0x00000010U
 
#define QUADSPI_DLR_DL   0xFFFFFFFFU
 
#define QUADSPI_CCR_INSTRUCTION   0x000000FFU
 
#define QUADSPI_CCR_INSTRUCTION_0   0x00000001U
 
#define QUADSPI_CCR_INSTRUCTION_1   0x00000002U
 
#define QUADSPI_CCR_INSTRUCTION_2   0x00000004U
 
#define QUADSPI_CCR_INSTRUCTION_3   0x00000008U
 
#define QUADSPI_CCR_INSTRUCTION_4   0x00000010U
 
#define QUADSPI_CCR_INSTRUCTION_5   0x00000020U
 
#define QUADSPI_CCR_INSTRUCTION_6   0x00000040U
 
#define QUADSPI_CCR_INSTRUCTION_7   0x00000080U
 
#define QUADSPI_CCR_IMODE   0x00000300U
 
#define QUADSPI_CCR_IMODE_0   0x00000100U
 
#define QUADSPI_CCR_IMODE_1   0x00000200U
 
#define QUADSPI_CCR_ADMODE   0x00000C00U
 
#define QUADSPI_CCR_ADMODE_0   0x00000400U
 
#define QUADSPI_CCR_ADMODE_1   0x00000800U
 
#define QUADSPI_CCR_ADSIZE   0x00003000U
 
#define QUADSPI_CCR_ADSIZE_0   0x00001000U
 
#define QUADSPI_CCR_ADSIZE_1   0x00002000U
 
#define QUADSPI_CCR_ABMODE   0x0000C000U
 
#define QUADSPI_CCR_ABMODE_0   0x00004000U
 
#define QUADSPI_CCR_ABMODE_1   0x00008000U
 
#define QUADSPI_CCR_ABSIZE   0x00030000U
 
#define QUADSPI_CCR_ABSIZE_0   0x00010000U
 
#define QUADSPI_CCR_ABSIZE_1   0x00020000U
 
#define QUADSPI_CCR_DCYC   0x007C0000U
 
#define QUADSPI_CCR_DCYC_0   0x00040000U
 
#define QUADSPI_CCR_DCYC_1   0x00080000U
 
#define QUADSPI_CCR_DCYC_2   0x00100000U
 
#define QUADSPI_CCR_DCYC_3   0x00200000U
 
#define QUADSPI_CCR_DCYC_4   0x00400000U
 
#define QUADSPI_CCR_DMODE   0x03000000U
 
#define QUADSPI_CCR_DMODE_0   0x01000000U
 
#define QUADSPI_CCR_DMODE_1   0x02000000U
 
#define QUADSPI_CCR_FMODE   0x0C000000U
 
#define QUADSPI_CCR_FMODE_0   0x04000000U
 
#define QUADSPI_CCR_FMODE_1   0x08000000U
 
#define QUADSPI_CCR_SIOO   0x10000000U
 
#define QUADSPI_CCR_DHHC   0x40000000U
 
#define QUADSPI_CCR_DDRM   0x80000000U
 
#define QUADSPI_AR_ADDRESS   0xFFFFFFFFU
 
#define QUADSPI_ABR_ALTERNATE   0xFFFFFFFFU
 
#define QUADSPI_DR_DATA   0xFFFFFFFFU
 
#define QUADSPI_PSMKR_MASK   0xFFFFFFFFU
 
#define QUADSPI_PSMAR_MATCH   0xFFFFFFFFU
 
#define QUADSPI_PIR_INTERVAL   0x0000FFFFU
 
#define QUADSPI_LPTR_TIMEOUT   0x0000FFFFU
 
#define RCC_CR_HSION   0x00000001U
 
#define RCC_CR_HSIRDY   0x00000002U
 
#define RCC_CR_HSITRIM   0x000000F8U
 
#define RCC_CR_HSITRIM_0   0x00000008U
 
#define RCC_CR_HSITRIM_1   0x00000010U
 
#define RCC_CR_HSITRIM_2   0x00000020U
 
#define RCC_CR_HSITRIM_3   0x00000040U
 
#define RCC_CR_HSITRIM_4   0x00000080U
 
#define RCC_CR_HSICAL   0x0000FF00U
 
#define RCC_CR_HSICAL_0   0x00000100U
 
#define RCC_CR_HSICAL_1   0x00000200U
 
#define RCC_CR_HSICAL_2   0x00000400U
 
#define RCC_CR_HSICAL_3   0x00000800U
 
#define RCC_CR_HSICAL_4   0x00001000U
 
#define RCC_CR_HSICAL_5   0x00002000U
 
#define RCC_CR_HSICAL_6   0x00004000U
 
#define RCC_CR_HSICAL_7   0x00008000U
 
#define RCC_CR_HSEON   0x00010000U
 
#define RCC_CR_HSERDY   0x00020000U
 
#define RCC_CR_HSEBYP   0x00040000U
 
#define RCC_CR_CSSON   0x00080000U
 
#define RCC_CR_PLLON   0x01000000U
 
#define RCC_CR_PLLRDY   0x02000000U
 
#define RCC_CR_PLLI2SON   0x04000000U
 
#define RCC_CR_PLLI2SRDY   0x08000000U
 
#define RCC_CR_PLLSAION   0x10000000U
 
#define RCC_CR_PLLSAIRDY   0x20000000U
 
#define RCC_PLLCFGR_PLLM   0x0000003FU
 
#define RCC_PLLCFGR_PLLM_0   0x00000001U
 
#define RCC_PLLCFGR_PLLM_1   0x00000002U
 
#define RCC_PLLCFGR_PLLM_2   0x00000004U
 
#define RCC_PLLCFGR_PLLM_3   0x00000008U
 
#define RCC_PLLCFGR_PLLM_4   0x00000010U
 
#define RCC_PLLCFGR_PLLM_5   0x00000020U
 
#define RCC_PLLCFGR_PLLN   0x00007FC0U
 
#define RCC_PLLCFGR_PLLN_0   0x00000040U
 
#define RCC_PLLCFGR_PLLN_1   0x00000080U
 
#define RCC_PLLCFGR_PLLN_2   0x00000100U
 
#define RCC_PLLCFGR_PLLN_3   0x00000200U
 
#define RCC_PLLCFGR_PLLN_4   0x00000400U
 
#define RCC_PLLCFGR_PLLN_5   0x00000800U
 
#define RCC_PLLCFGR_PLLN_6   0x00001000U
 
#define RCC_PLLCFGR_PLLN_7   0x00002000U
 
#define RCC_PLLCFGR_PLLN_8   0x00004000U
 
#define RCC_PLLCFGR_PLLP   0x00030000U
 
#define RCC_PLLCFGR_PLLP_0   0x00010000U
 
#define RCC_PLLCFGR_PLLP_1   0x00020000U
 
#define RCC_PLLCFGR_PLLSRC   0x00400000U
 
#define RCC_PLLCFGR_PLLSRC_HSE   0x00400000U
 
#define RCC_PLLCFGR_PLLSRC_HSI   0x00000000U
 
#define RCC_PLLCFGR_PLLQ   0x0F000000U
 
#define RCC_PLLCFGR_PLLQ_0   0x01000000U
 
#define RCC_PLLCFGR_PLLQ_1   0x02000000U
 
#define RCC_PLLCFGR_PLLQ_2   0x04000000U
 
#define RCC_PLLCFGR_PLLQ_3   0x08000000U
 
#define RCC_CFGR_SW   0x00000003U
 
#define RCC_CFGR_SW_0   0x00000001U
 
#define RCC_CFGR_SW_1   0x00000002U
 
#define RCC_CFGR_SW_HSI   0x00000000U
 
#define RCC_CFGR_SW_HSE   0x00000001U
 
#define RCC_CFGR_SW_PLL   0x00000002U
 
#define RCC_CFGR_SWS   0x0000000CU
 
#define RCC_CFGR_SWS_0   0x00000004U
 
#define RCC_CFGR_SWS_1   0x00000008U
 
#define RCC_CFGR_SWS_HSI   0x00000000U
 
#define RCC_CFGR_SWS_HSE   0x00000004U
 
#define RCC_CFGR_SWS_PLL   0x00000008U
 
#define RCC_CFGR_HPRE   0x000000F0U
 
#define RCC_CFGR_HPRE_0   0x00000010U
 
#define RCC_CFGR_HPRE_1   0x00000020U
 
#define RCC_CFGR_HPRE_2   0x00000040U
 
#define RCC_CFGR_HPRE_3   0x00000080U
 
#define RCC_CFGR_HPRE_DIV1   0x00000000U
 
#define RCC_CFGR_HPRE_DIV2   0x00000080U
 
#define RCC_CFGR_HPRE_DIV4   0x00000090U
 
#define RCC_CFGR_HPRE_DIV8   0x000000A0U
 
#define RCC_CFGR_HPRE_DIV16   0x000000B0U
 
#define RCC_CFGR_HPRE_DIV64   0x000000C0U
 
#define RCC_CFGR_HPRE_DIV128   0x000000D0U
 
#define RCC_CFGR_HPRE_DIV256   0x000000E0U
 
#define RCC_CFGR_HPRE_DIV512   0x000000F0U
 
#define RCC_CFGR_PPRE1   0x00001C00U
 
#define RCC_CFGR_PPRE1_0   0x00000400U
 
#define RCC_CFGR_PPRE1_1   0x00000800U
 
#define RCC_CFGR_PPRE1_2   0x00001000U
 
#define RCC_CFGR_PPRE1_DIV1   0x00000000U
 
#define RCC_CFGR_PPRE1_DIV2   0x00001000U
 
#define RCC_CFGR_PPRE1_DIV4   0x00001400U
 
#define RCC_CFGR_PPRE1_DIV8   0x00001800U
 
#define RCC_CFGR_PPRE1_DIV16   0x00001C00U
 
#define RCC_CFGR_PPRE2   0x0000E000U
 
#define RCC_CFGR_PPRE2_0   0x00002000U
 
#define RCC_CFGR_PPRE2_1   0x00004000U
 
#define RCC_CFGR_PPRE2_2   0x00008000U
 
#define RCC_CFGR_PPRE2_DIV1   0x00000000U
 
#define RCC_CFGR_PPRE2_DIV2   0x00008000U
 
#define RCC_CFGR_PPRE2_DIV4   0x0000A000U
 
#define RCC_CFGR_PPRE2_DIV8   0x0000C000U
 
#define RCC_CFGR_PPRE2_DIV16   0x0000E000U
 
#define RCC_CFGR_RTCPRE   0x001F0000U
 
#define RCC_CFGR_RTCPRE_0   0x00010000U
 
#define RCC_CFGR_RTCPRE_1   0x00020000U
 
#define RCC_CFGR_RTCPRE_2   0x00040000U
 
#define RCC_CFGR_RTCPRE_3   0x00080000U
 
#define RCC_CFGR_RTCPRE_4   0x00100000U
 
#define RCC_CFGR_MCO1   0x00600000U
 
#define RCC_CFGR_MCO1_0   0x00200000U
 
#define RCC_CFGR_MCO1_1   0x00400000U
 
#define RCC_CFGR_I2SSRC   0x00800000U
 
#define RCC_CFGR_MCO1PRE   0x07000000U
 
#define RCC_CFGR_MCO1PRE_0   0x01000000U
 
#define RCC_CFGR_MCO1PRE_1   0x02000000U
 
#define RCC_CFGR_MCO1PRE_2   0x04000000U
 
#define RCC_CFGR_MCO2PRE   0x38000000U
 
#define RCC_CFGR_MCO2PRE_0   0x08000000U
 
#define RCC_CFGR_MCO2PRE_1   0x10000000U
 
#define RCC_CFGR_MCO2PRE_2   0x20000000U
 
#define RCC_CFGR_MCO2   0xC0000000U
 
#define RCC_CFGR_MCO2_0   0x40000000U
 
#define RCC_CFGR_MCO2_1   0x80000000U
 
#define RCC_CIR_LSIRDYF   0x00000001U
 
#define RCC_CIR_LSERDYF   0x00000002U
 
#define RCC_CIR_HSIRDYF   0x00000004U
 
#define RCC_CIR_HSERDYF   0x00000008U
 
#define RCC_CIR_PLLRDYF   0x00000010U
 
#define RCC_CIR_PLLI2SRDYF   0x00000020U
 
#define RCC_CIR_PLLSAIRDYF   0x00000040U
 
#define RCC_CIR_CSSF   0x00000080U
 
#define RCC_CIR_LSIRDYIE   0x00000100U
 
#define RCC_CIR_LSERDYIE   0x00000200U
 
#define RCC_CIR_HSIRDYIE   0x00000400U
 
#define RCC_CIR_HSERDYIE   0x00000800U
 
#define RCC_CIR_PLLRDYIE   0x00001000U
 
#define RCC_CIR_PLLI2SRDYIE   0x00002000U
 
#define RCC_CIR_PLLSAIRDYIE   0x00004000U
 
#define RCC_CIR_LSIRDYC   0x00010000U
 
#define RCC_CIR_LSERDYC   0x00020000U
 
#define RCC_CIR_HSIRDYC   0x00040000U
 
#define RCC_CIR_HSERDYC   0x00080000U
 
#define RCC_CIR_PLLRDYC   0x00100000U
 
#define RCC_CIR_PLLI2SRDYC   0x00200000U
 
#define RCC_CIR_PLLSAIRDYC   0x00400000U
 
#define RCC_CIR_CSSC   0x00800000U
 
#define RCC_AHB1RSTR_GPIOARST   0x00000001U
 
#define RCC_AHB1RSTR_GPIOBRST   0x00000002U
 
#define RCC_AHB1RSTR_GPIOCRST   0x00000004U
 
#define RCC_AHB1RSTR_GPIODRST   0x00000008U
 
#define RCC_AHB1RSTR_GPIOERST   0x00000010U
 
#define RCC_AHB1RSTR_GPIOFRST   0x00000020U
 
#define RCC_AHB1RSTR_GPIOGRST   0x00000040U
 
#define RCC_AHB1RSTR_GPIOHRST   0x00000080U
 
#define RCC_AHB1RSTR_GPIOIRST   0x00000100U
 
#define RCC_AHB1RSTR_GPIOJRST   0x00000200U
 
#define RCC_AHB1RSTR_GPIOKRST   0x00000400U
 
#define RCC_AHB1RSTR_CRCRST   0x00001000U
 
#define RCC_AHB1RSTR_DMA1RST   0x00200000U
 
#define RCC_AHB1RSTR_DMA2RST   0x00400000U
 
#define RCC_AHB1RSTR_DMA2DRST   0x00800000U
 
#define RCC_AHB1RSTR_ETHMACRST   0x02000000U
 
#define RCC_AHB1RSTR_OTGHRST   0x20000000U
 
#define RCC_AHB2RSTR_DCMIRST   0x00000001U
 
#define RCC_AHB2RSTR_RNGRST   0x00000040U
 
#define RCC_AHB2RSTR_OTGFSRST   0x00000080U
 
#define RCC_AHB3RSTR_FMCRST   0x00000001U
 
#define RCC_AHB3RSTR_QSPIRST   0x00000002U
 
#define RCC_APB1RSTR_TIM2RST   0x00000001U
 
#define RCC_APB1RSTR_TIM3RST   0x00000002U
 
#define RCC_APB1RSTR_TIM4RST   0x00000004U
 
#define RCC_APB1RSTR_TIM5RST   0x00000008U
 
#define RCC_APB1RSTR_TIM6RST   0x00000010U
 
#define RCC_APB1RSTR_TIM7RST   0x00000020U
 
#define RCC_APB1RSTR_TIM12RST   0x00000040U
 
#define RCC_APB1RSTR_TIM13RST   0x00000080U
 
#define RCC_APB1RSTR_TIM14RST   0x00000100U
 
#define RCC_APB1RSTR_LPTIM1RST   0x00000200U
 
#define RCC_APB1RSTR_WWDGRST   0x00000800U
 
#define RCC_APB1RSTR_SPI2RST   0x00004000U
 
#define RCC_APB1RSTR_SPI3RST   0x00008000U
 
#define RCC_APB1RSTR_SPDIFRXRST   0x00010000U
 
#define RCC_APB1RSTR_USART2RST   0x00020000U
 
#define RCC_APB1RSTR_USART3RST   0x00040000U
 
#define RCC_APB1RSTR_UART4RST   0x00080000U
 
#define RCC_APB1RSTR_UART5RST   0x00100000U
 
#define RCC_APB1RSTR_I2C1RST   0x00200000U
 
#define RCC_APB1RSTR_I2C2RST   0x00400000U
 
#define RCC_APB1RSTR_I2C3RST   0x00800000U
 
#define RCC_APB1RSTR_I2C4RST   0x01000000U
 
#define RCC_APB1RSTR_CAN1RST   0x02000000U
 
#define RCC_APB1RSTR_CAN2RST   0x04000000U
 
#define RCC_APB1RSTR_CECRST   0x08000000U
 
#define RCC_APB1RSTR_PWRRST   0x10000000U
 
#define RCC_APB1RSTR_DACRST   0x20000000U
 
#define RCC_APB1RSTR_UART7RST   0x40000000U
 
#define RCC_APB1RSTR_UART8RST   0x80000000U
 
#define RCC_APB2RSTR_TIM1RST   0x00000001U
 
#define RCC_APB2RSTR_TIM8RST   0x00000002U
 
#define RCC_APB2RSTR_USART1RST   0x00000010U
 
#define RCC_APB2RSTR_USART6RST   0x00000020U
 
#define RCC_APB2RSTR_ADCRST   0x00000100U
 
#define RCC_APB2RSTR_SDMMC1RST   0x00000800U
 
#define RCC_APB2RSTR_SPI1RST   0x00001000U
 
#define RCC_APB2RSTR_SPI4RST   0x00002000U
 
#define RCC_APB2RSTR_SYSCFGRST   0x00004000U
 
#define RCC_APB2RSTR_TIM9RST   0x00010000U
 
#define RCC_APB2RSTR_TIM10RST   0x00020000U
 
#define RCC_APB2RSTR_TIM11RST   0x00040000U
 
#define RCC_APB2RSTR_SPI5RST   0x00100000U
 
#define RCC_APB2RSTR_SPI6RST   0x00200000U
 
#define RCC_APB2RSTR_SAI1RST   0x00400000U
 
#define RCC_APB2RSTR_SAI2RST   0x00800000U
 
#define RCC_APB2RSTR_LTDCRST   0x04000000U
 
#define RCC_AHB1ENR_GPIOAEN   0x00000001U
 
#define RCC_AHB1ENR_GPIOBEN   0x00000002U
 
#define RCC_AHB1ENR_GPIOCEN   0x00000004U
 
#define RCC_AHB1ENR_GPIODEN   0x00000008U
 
#define RCC_AHB1ENR_GPIOEEN   0x00000010U
 
#define RCC_AHB1ENR_GPIOFEN   0x00000020U
 
#define RCC_AHB1ENR_GPIOGEN   0x00000040U
 
#define RCC_AHB1ENR_GPIOHEN   0x00000080U
 
#define RCC_AHB1ENR_GPIOIEN   0x00000100U
 
#define RCC_AHB1ENR_GPIOJEN   0x00000200U
 
#define RCC_AHB1ENR_GPIOKEN   0x00000400U
 
#define RCC_AHB1ENR_CRCEN   0x00001000U
 
#define RCC_AHB1ENR_BKPSRAMEN   0x00040000U
 
#define RCC_AHB1ENR_DTCMRAMEN   0x00100000U
 
#define RCC_AHB1ENR_DMA1EN   0x00200000U
 
#define RCC_AHB1ENR_DMA2EN   0x00400000U
 
#define RCC_AHB1ENR_DMA2DEN   0x00800000U
 
#define RCC_AHB1ENR_ETHMACEN   0x02000000U
 
#define RCC_AHB1ENR_ETHMACTXEN   0x04000000U
 
#define RCC_AHB1ENR_ETHMACRXEN   0x08000000U
 
#define RCC_AHB1ENR_ETHMACPTPEN   0x10000000U
 
#define RCC_AHB1ENR_OTGHSEN   0x20000000U
 
#define RCC_AHB1ENR_OTGHSULPIEN   0x40000000U
 
#define RCC_AHB2ENR_DCMIEN   0x00000001U
 
#define RCC_AHB2ENR_RNGEN   0x00000040U
 
#define RCC_AHB2ENR_OTGFSEN   0x00000080U
 
#define RCC_AHB3ENR_FMCEN   0x00000001U
 
#define RCC_AHB3ENR_QSPIEN   0x00000002U
 
#define RCC_APB1ENR_TIM2EN   0x00000001U
 
#define RCC_APB1ENR_TIM3EN   0x00000002U
 
#define RCC_APB1ENR_TIM4EN   0x00000004U
 
#define RCC_APB1ENR_TIM5EN   0x00000008U
 
#define RCC_APB1ENR_TIM6EN   0x00000010U
 
#define RCC_APB1ENR_TIM7EN   0x00000020U
 
#define RCC_APB1ENR_TIM12EN   0x00000040U
 
#define RCC_APB1ENR_TIM13EN   0x00000080U
 
#define RCC_APB1ENR_TIM14EN   0x00000100U
 
#define RCC_APB1ENR_LPTIM1EN   0x00000200U
 
#define RCC_APB1ENR_WWDGEN   0x00000800U
 
#define RCC_APB1ENR_SPI2EN   0x00004000U
 
#define RCC_APB1ENR_SPI3EN   0x00008000U
 
#define RCC_APB1ENR_SPDIFRXEN   0x00010000U
 
#define RCC_APB1ENR_USART2EN   0x00020000U
 
#define RCC_APB1ENR_USART3EN   0x00040000U
 
#define RCC_APB1ENR_UART4EN   0x00080000U
 
#define RCC_APB1ENR_UART5EN   0x00100000U
 
#define RCC_APB1ENR_I2C1EN   0x00200000U
 
#define RCC_APB1ENR_I2C2EN   0x00400000U
 
#define RCC_APB1ENR_I2C3EN   0x00800000U
 
#define RCC_APB1ENR_I2C4EN   0x01000000U
 
#define RCC_APB1ENR_CAN1EN   0x02000000U
 
#define RCC_APB1ENR_CAN2EN   0x04000000U
 
#define RCC_APB1ENR_CECEN   0x08000000U
 
#define RCC_APB1ENR_PWREN   0x10000000U
 
#define RCC_APB1ENR_DACEN   0x20000000U
 
#define RCC_APB1ENR_UART7EN   0x40000000U
 
#define RCC_APB1ENR_UART8EN   0x80000000U
 
#define RCC_APB2ENR_TIM1EN   0x00000001U
 
#define RCC_APB2ENR_TIM8EN   0x00000002U
 
#define RCC_APB2ENR_USART1EN   0x00000010U
 
#define RCC_APB2ENR_USART6EN   0x00000020U
 
#define RCC_APB2ENR_ADC1EN   0x00000100U
 
#define RCC_APB2ENR_ADC2EN   0x00000200U
 
#define RCC_APB2ENR_ADC3EN   0x00000400U
 
#define RCC_APB2ENR_SDMMC1EN   0x00000800U
 
#define RCC_APB2ENR_SPI1EN   0x00001000U
 
#define RCC_APB2ENR_SPI4EN   0x00002000U
 
#define RCC_APB2ENR_SYSCFGEN   0x00004000U
 
#define RCC_APB2ENR_TIM9EN   0x00010000U
 
#define RCC_APB2ENR_TIM10EN   0x00020000U
 
#define RCC_APB2ENR_TIM11EN   0x00040000U
 
#define RCC_APB2ENR_SPI5EN   0x00100000U
 
#define RCC_APB2ENR_SPI6EN   0x00200000U
 
#define RCC_APB2ENR_SAI1EN   0x00400000U
 
#define RCC_APB2ENR_SAI2EN   0x00800000U
 
#define RCC_APB2ENR_LTDCEN   0x04000000U
 
#define RCC_AHB1LPENR_GPIOALPEN   0x00000001U
 
#define RCC_AHB1LPENR_GPIOBLPEN   0x00000002U
 
#define RCC_AHB1LPENR_GPIOCLPEN   0x00000004U
 
#define RCC_AHB1LPENR_GPIODLPEN   0x00000008U
 
#define RCC_AHB1LPENR_GPIOELPEN   0x00000010U
 
#define RCC_AHB1LPENR_GPIOFLPEN   0x00000020U
 
#define RCC_AHB1LPENR_GPIOGLPEN   0x00000040U
 
#define RCC_AHB1LPENR_GPIOHLPEN   0x00000080U
 
#define RCC_AHB1LPENR_GPIOILPEN   0x00000100U
 
#define RCC_AHB1LPENR_GPIOJLPEN   0x00000200U
 
#define RCC_AHB1LPENR_GPIOKLPEN   0x00000400U
 
#define RCC_AHB1LPENR_CRCLPEN   0x00001000U
 
#define RCC_AHB1LPENR_AXILPEN   0x00002000U
 
#define RCC_AHB1LPENR_FLITFLPEN   0x00008000U
 
#define RCC_AHB1LPENR_SRAM1LPEN   0x00010000U
 
#define RCC_AHB1LPENR_SRAM2LPEN   0x00020000U
 
#define RCC_AHB1LPENR_BKPSRAMLPEN   0x00040000U
 
#define RCC_AHB1LPENR_DTCMLPEN   0x00100000U
 
#define RCC_AHB1LPENR_DMA1LPEN   0x00200000U
 
#define RCC_AHB1LPENR_DMA2LPEN   0x00400000U
 
#define RCC_AHB1LPENR_DMA2DLPEN   0x00800000U
 
#define RCC_AHB1LPENR_ETHMACLPEN   0x02000000U
 
#define RCC_AHB1LPENR_ETHMACTXLPEN   0x04000000U
 
#define RCC_AHB1LPENR_ETHMACRXLPEN   0x08000000U
 
#define RCC_AHB1LPENR_ETHMACPTPLPEN   0x10000000U
 
#define RCC_AHB1LPENR_OTGHSLPEN   0x20000000U
 
#define RCC_AHB1LPENR_OTGHSULPILPEN   0x40000000U
 
#define RCC_AHB2LPENR_DCMILPEN   0x00000001U
 
#define RCC_AHB2LPENR_RNGLPEN   0x00000040U
 
#define RCC_AHB2LPENR_OTGFSLPEN   0x00000080U
 
#define RCC_AHB3LPENR_FMCLPEN   0x00000001U
 
#define RCC_AHB3LPENR_QSPILPEN   0x00000002U
 
#define RCC_APB1LPENR_TIM2LPEN   0x00000001U
 
#define RCC_APB1LPENR_TIM3LPEN   0x00000002U
 
#define RCC_APB1LPENR_TIM4LPEN   0x00000004U
 
#define RCC_APB1LPENR_TIM5LPEN   0x00000008U
 
#define RCC_APB1LPENR_TIM6LPEN   0x00000010U
 
#define RCC_APB1LPENR_TIM7LPEN   0x00000020U
 
#define RCC_APB1LPENR_TIM12LPEN   0x00000040U
 
#define RCC_APB1LPENR_TIM13LPEN   0x00000080U
 
#define RCC_APB1LPENR_TIM14LPEN   0x00000100U
 
#define RCC_APB1LPENR_LPTIM1LPEN   0x00000200U
 
#define RCC_APB1LPENR_WWDGLPEN   0x00000800U
 
#define RCC_APB1LPENR_SPI2LPEN   0x00004000U
 
#define RCC_APB1LPENR_SPI3LPEN   0x00008000U
 
#define RCC_APB1LPENR_SPDIFRXLPEN   0x00010000U
 
#define RCC_APB1LPENR_USART2LPEN   0x00020000U
 
#define RCC_APB1LPENR_USART3LPEN   0x00040000U
 
#define RCC_APB1LPENR_UART4LPEN   0x00080000U
 
#define RCC_APB1LPENR_UART5LPEN   0x00100000U
 
#define RCC_APB1LPENR_I2C1LPEN   0x00200000U
 
#define RCC_APB1LPENR_I2C2LPEN   0x00400000U
 
#define RCC_APB1LPENR_I2C3LPEN   0x00800000U
 
#define RCC_APB1LPENR_I2C4LPEN   0x01000000U
 
#define RCC_APB1LPENR_CAN1LPEN   0x02000000U
 
#define RCC_APB1LPENR_CAN2LPEN   0x04000000U
 
#define RCC_APB1LPENR_CECLPEN   0x08000000U
 
#define RCC_APB1LPENR_PWRLPEN   0x10000000U
 
#define RCC_APB1LPENR_DACLPEN   0x20000000U
 
#define RCC_APB1LPENR_UART7LPEN   0x40000000U
 
#define RCC_APB1LPENR_UART8LPEN   0x80000000U
 
#define RCC_APB2LPENR_TIM1LPEN   0x00000001U
 
#define RCC_APB2LPENR_TIM8LPEN   0x00000002U
 
#define RCC_APB2LPENR_USART1LPEN   0x00000010U
 
#define RCC_APB2LPENR_USART6LPEN   0x00000020U
 
#define RCC_APB2LPENR_ADC1LPEN   0x00000100U
 
#define RCC_APB2LPENR_ADC2LPEN   0x00000200U
 
#define RCC_APB2LPENR_ADC3LPEN   0x00000400U
 
#define RCC_APB2LPENR_SDMMC1LPEN   0x00000800U
 
#define RCC_APB2LPENR_SPI1LPEN   0x00001000U
 
#define RCC_APB2LPENR_SPI4LPEN   0x00002000U
 
#define RCC_APB2LPENR_SYSCFGLPEN   0x00004000U
 
#define RCC_APB2LPENR_TIM9LPEN   0x00010000U
 
#define RCC_APB2LPENR_TIM10LPEN   0x00020000U
 
#define RCC_APB2LPENR_TIM11LPEN   0x00040000U
 
#define RCC_APB2LPENR_SPI5LPEN   0x00100000U
 
#define RCC_APB2LPENR_SPI6LPEN   0x00200000U
 
#define RCC_APB2LPENR_SAI1LPEN   0x00400000U
 
#define RCC_APB2LPENR_SAI2LPEN   0x00800000U
 
#define RCC_APB2LPENR_LTDCLPEN   0x04000000U
 
#define RCC_BDCR_LSEON   0x00000001U
 
#define RCC_BDCR_LSERDY   0x00000002U
 
#define RCC_BDCR_LSEBYP   0x00000004U
 
#define RCC_BDCR_LSEDRV   0x00000018U
 
#define RCC_BDCR_LSEDRV_0   0x00000008U
 
#define RCC_BDCR_LSEDRV_1   0x00000010U
 
#define RCC_BDCR_RTCSEL   0x00000300U
 
#define RCC_BDCR_RTCSEL_0   0x00000100U
 
#define RCC_BDCR_RTCSEL_1   0x00000200U
 
#define RCC_BDCR_RTCEN   0x00008000U
 
#define RCC_BDCR_BDRST   0x00010000U
 
#define RCC_CSR_LSION   0x00000001U
 
#define RCC_CSR_LSIRDY   0x00000002U
 
#define RCC_CSR_RMVF   0x01000000U
 
#define RCC_CSR_BORRSTF   0x02000000U
 
#define RCC_CSR_PINRSTF   0x04000000U
 
#define RCC_CSR_PORRSTF   0x08000000U
 
#define RCC_CSR_SFTRSTF   0x10000000U
 
#define RCC_CSR_IWDGRSTF   0x20000000U
 
#define RCC_CSR_WWDGRSTF   0x40000000U
 
#define RCC_CSR_LPWRRSTF   0x80000000U
 
#define RCC_SSCGR_MODPER   0x00001FFFU
 
#define RCC_SSCGR_INCSTEP   0x0FFFE000U
 
#define RCC_SSCGR_SPREADSEL   0x40000000U
 
#define RCC_SSCGR_SSCGEN   0x80000000U
 
#define RCC_PLLI2SCFGR_PLLI2SN   0x00007FC0U
 
#define RCC_PLLI2SCFGR_PLLI2SN_0   0x00000040U
 
#define RCC_PLLI2SCFGR_PLLI2SN_1   0x00000080U
 
#define RCC_PLLI2SCFGR_PLLI2SN_2   0x00000100U
 
#define RCC_PLLI2SCFGR_PLLI2SN_3   0x00000200U
 
#define RCC_PLLI2SCFGR_PLLI2SN_4   0x00000400U
 
#define RCC_PLLI2SCFGR_PLLI2SN_5   0x00000800U
 
#define RCC_PLLI2SCFGR_PLLI2SN_6   0x00001000U
 
#define RCC_PLLI2SCFGR_PLLI2SN_7   0x00002000U
 
#define RCC_PLLI2SCFGR_PLLI2SN_8   0x00004000U
 
#define RCC_PLLI2SCFGR_PLLI2SP   0x00030000U
 
#define RCC_PLLI2SCFGR_PLLI2SP_0   0x00010000U
 
#define RCC_PLLI2SCFGR_PLLI2SP_1   0x00020000U
 
#define RCC_PLLI2SCFGR_PLLI2SQ   0x0F000000U
 
#define RCC_PLLI2SCFGR_PLLI2SQ_0   0x01000000U
 
#define RCC_PLLI2SCFGR_PLLI2SQ_1   0x02000000U
 
#define RCC_PLLI2SCFGR_PLLI2SQ_2   0x04000000U
 
#define RCC_PLLI2SCFGR_PLLI2SQ_3   0x08000000U
 
#define RCC_PLLI2SCFGR_PLLI2SR   0x70000000U
 
#define RCC_PLLI2SCFGR_PLLI2SR_0   0x10000000U
 
#define RCC_PLLI2SCFGR_PLLI2SR_1   0x20000000U
 
#define RCC_PLLI2SCFGR_PLLI2SR_2   0x40000000U
 
#define RCC_PLLSAICFGR_PLLSAIN   0x00007FC0U
 
#define RCC_PLLSAICFGR_PLLSAIN_0   0x00000040U
 
#define RCC_PLLSAICFGR_PLLSAIN_1   0x00000080U
 
#define RCC_PLLSAICFGR_PLLSAIN_2   0x00000100U
 
#define RCC_PLLSAICFGR_PLLSAIN_3   0x00000200U
 
#define RCC_PLLSAICFGR_PLLSAIN_4   0x00000400U
 
#define RCC_PLLSAICFGR_PLLSAIN_5   0x00000800U
 
#define RCC_PLLSAICFGR_PLLSAIN_6   0x00001000U
 
#define RCC_PLLSAICFGR_PLLSAIN_7   0x00002000U
 
#define RCC_PLLSAICFGR_PLLSAIN_8   0x00004000U
 
#define RCC_PLLSAICFGR_PLLSAIP   0x00030000U
 
#define RCC_PLLSAICFGR_PLLSAIP_0   0x00010000U
 
#define RCC_PLLSAICFGR_PLLSAIP_1   0x00020000U
 
#define RCC_PLLSAICFGR_PLLSAIQ   0x0F000000U
 
#define RCC_PLLSAICFGR_PLLSAIQ_0   0x01000000U
 
#define RCC_PLLSAICFGR_PLLSAIQ_1   0x02000000U
 
#define RCC_PLLSAICFGR_PLLSAIQ_2   0x04000000U
 
#define RCC_PLLSAICFGR_PLLSAIQ_3   0x08000000U
 
#define RCC_PLLSAICFGR_PLLSAIR   0x70000000U
 
#define RCC_PLLSAICFGR_PLLSAIR_0   0x10000000U
 
#define RCC_PLLSAICFGR_PLLSAIR_1   0x20000000U
 
#define RCC_PLLSAICFGR_PLLSAIR_2   0x40000000U
 
#define RCC_DCKCFGR1_PLLI2SDIVQ   0x0000001FU
 
#define RCC_DCKCFGR1_PLLI2SDIVQ_0   0x00000001U
 
#define RCC_DCKCFGR1_PLLI2SDIVQ_1   0x00000002U
 
#define RCC_DCKCFGR1_PLLI2SDIVQ_2   0x00000004U
 
#define RCC_DCKCFGR1_PLLI2SDIVQ_3   0x00000008U
 
#define RCC_DCKCFGR1_PLLI2SDIVQ_4   0x00000010U
 
#define RCC_DCKCFGR1_PLLSAIDIVQ   0x00001F00U
 
#define RCC_DCKCFGR1_PLLSAIDIVQ_0   0x00000100U
 
#define RCC_DCKCFGR1_PLLSAIDIVQ_1   0x00000200U
 
#define RCC_DCKCFGR1_PLLSAIDIVQ_2   0x00000400U
 
#define RCC_DCKCFGR1_PLLSAIDIVQ_3   0x00000800U
 
#define RCC_DCKCFGR1_PLLSAIDIVQ_4   0x00001000U
 
#define RCC_DCKCFGR1_PLLSAIDIVR   0x00030000U
 
#define RCC_DCKCFGR1_PLLSAIDIVR_0   0x00010000U
 
#define RCC_DCKCFGR1_PLLSAIDIVR_1   0x00020000U
 
#define RCC_DCKCFGR1_SAI1SEL   0x00300000U
 
#define RCC_DCKCFGR1_SAI1SEL_0   0x00100000U
 
#define RCC_DCKCFGR1_SAI1SEL_1   0x00200000U
 
#define RCC_DCKCFGR1_SAI2SEL   0x00C00000U
 
#define RCC_DCKCFGR1_SAI2SEL_0   0x00400000U
 
#define RCC_DCKCFGR1_SAI2SEL_1   0x00800000U
 
#define RCC_DCKCFGR1_TIMPRE   0x01000000U
 
#define RCC_DCKCFGR2_USART1SEL   0x00000003U
 
#define RCC_DCKCFGR2_USART1SEL_0   0x00000001U
 
#define RCC_DCKCFGR2_USART1SEL_1   0x00000002U
 
#define RCC_DCKCFGR2_USART2SEL   0x0000000CU
 
#define RCC_DCKCFGR2_USART2SEL_0   0x00000004U
 
#define RCC_DCKCFGR2_USART2SEL_1   0x00000008U
 
#define RCC_DCKCFGR2_USART3SEL   0x00000030U
 
#define RCC_DCKCFGR2_USART3SEL_0   0x00000010U
 
#define RCC_DCKCFGR2_USART3SEL_1   0x00000020U
 
#define RCC_DCKCFGR2_UART4SEL   0x000000C0U
 
#define RCC_DCKCFGR2_UART4SEL_0   0x00000040U
 
#define RCC_DCKCFGR2_UART4SEL_1   0x00000080U
 
#define RCC_DCKCFGR2_UART5SEL   0x00000300U
 
#define RCC_DCKCFGR2_UART5SEL_0   0x00000100U
 
#define RCC_DCKCFGR2_UART5SEL_1   0x00000200U
 
#define RCC_DCKCFGR2_USART6SEL   0x00000C00U
 
#define RCC_DCKCFGR2_USART6SEL_0   0x00000400U
 
#define RCC_DCKCFGR2_USART6SEL_1   0x00000800U
 
#define RCC_DCKCFGR2_UART7SEL   0x00003000U
 
#define RCC_DCKCFGR2_UART7SEL_0   0x00001000U
 
#define RCC_DCKCFGR2_UART7SEL_1   0x00002000U
 
#define RCC_DCKCFGR2_UART8SEL   0x0000C000U
 
#define RCC_DCKCFGR2_UART8SEL_0   0x00004000U
 
#define RCC_DCKCFGR2_UART8SEL_1   0x00008000U
 
#define RCC_DCKCFGR2_I2C1SEL   0x00030000U
 
#define RCC_DCKCFGR2_I2C1SEL_0   0x00010000U
 
#define RCC_DCKCFGR2_I2C1SEL_1   0x00020000U
 
#define RCC_DCKCFGR2_I2C2SEL   0x000C0000U
 
#define RCC_DCKCFGR2_I2C2SEL_0   0x00040000U
 
#define RCC_DCKCFGR2_I2C2SEL_1   0x00080000U
 
#define RCC_DCKCFGR2_I2C3SEL   0x00300000U
 
#define RCC_DCKCFGR2_I2C3SEL_0   0x00100000U
 
#define RCC_DCKCFGR2_I2C3SEL_1   0x00200000U
 
#define RCC_DCKCFGR2_I2C4SEL   0x00C00000U
 
#define RCC_DCKCFGR2_I2C4SEL_0   0x00400000U
 
#define RCC_DCKCFGR2_I2C4SEL_1   0x00800000U
 
#define RCC_DCKCFGR2_LPTIM1SEL   0x03000000U
 
#define RCC_DCKCFGR2_LPTIM1SEL_0   0x01000000U
 
#define RCC_DCKCFGR2_LPTIM1SEL_1   0x02000000U
 
#define RCC_DCKCFGR2_CECSEL   0x04000000U
 
#define RCC_DCKCFGR2_CK48MSEL   0x08000000U
 
#define RCC_DCKCFGR2_SDMMC1SEL   0x10000000U
 
#define RNG_CR_RNGEN   0x00000004U
 
#define RNG_CR_IE   0x00000008U
 
#define RNG_SR_DRDY   0x00000001U
 
#define RNG_SR_CECS   0x00000002U
 
#define RNG_SR_SECS   0x00000004U
 
#define RNG_SR_CEIS   0x00000020U
 
#define RNG_SR_SEIS   0x00000040U
 
#define RTC_TR_PM   0x00400000U
 
#define RTC_TR_HT   0x00300000U
 
#define RTC_TR_HT_0   0x00100000U
 
#define RTC_TR_HT_1   0x00200000U
 
#define RTC_TR_HU   0x000F0000U
 
#define RTC_TR_HU_0   0x00010000U
 
#define RTC_TR_HU_1   0x00020000U
 
#define RTC_TR_HU_2   0x00040000U
 
#define RTC_TR_HU_3   0x00080000U
 
#define RTC_TR_MNT   0x00007000U
 
#define RTC_TR_MNT_0   0x00001000U
 
#define RTC_TR_MNT_1   0x00002000U
 
#define RTC_TR_MNT_2   0x00004000U
 
#define RTC_TR_MNU   0x00000F00U
 
#define RTC_TR_MNU_0   0x00000100U
 
#define RTC_TR_MNU_1   0x00000200U
 
#define RTC_TR_MNU_2   0x00000400U
 
#define RTC_TR_MNU_3   0x00000800U
 
#define RTC_TR_ST   0x00000070U
 
#define RTC_TR_ST_0   0x00000010U
 
#define RTC_TR_ST_1   0x00000020U
 
#define RTC_TR_ST_2   0x00000040U
 
#define RTC_TR_SU   0x0000000FU
 
#define RTC_TR_SU_0   0x00000001U
 
#define RTC_TR_SU_1   0x00000002U
 
#define RTC_TR_SU_2   0x00000004U
 
#define RTC_TR_SU_3   0x00000008U
 
#define RTC_DR_YT   0x00F00000U
 
#define RTC_DR_YT_0   0x00100000U
 
#define RTC_DR_YT_1   0x00200000U
 
#define RTC_DR_YT_2   0x00400000U
 
#define RTC_DR_YT_3   0x00800000U
 
#define RTC_DR_YU   0x000F0000U
 
#define RTC_DR_YU_0   0x00010000U
 
#define RTC_DR_YU_1   0x00020000U
 
#define RTC_DR_YU_2   0x00040000U
 
#define RTC_DR_YU_3   0x00080000U
 
#define RTC_DR_WDU   0x0000E000U
 
#define RTC_DR_WDU_0   0x00002000U
 
#define RTC_DR_WDU_1   0x00004000U
 
#define RTC_DR_WDU_2   0x00008000U
 
#define RTC_DR_MT   0x00001000U
 
#define RTC_DR_MU   0x00000F00U
 
#define RTC_DR_MU_0   0x00000100U
 
#define RTC_DR_MU_1   0x00000200U
 
#define RTC_DR_MU_2   0x00000400U
 
#define RTC_DR_MU_3   0x00000800U
 
#define RTC_DR_DT   0x00000030U
 
#define RTC_DR_DT_0   0x00000010U
 
#define RTC_DR_DT_1   0x00000020U
 
#define RTC_DR_DU   0x0000000FU
 
#define RTC_DR_DU_0   0x00000001U
 
#define RTC_DR_DU_1   0x00000002U
 
#define RTC_DR_DU_2   0x00000004U
 
#define RTC_DR_DU_3   0x00000008U
 
#define RTC_CR_ITSE   0x01000000U
 
#define RTC_CR_COE   0x00800000U
 
#define RTC_CR_OSEL   0x00600000U
 
#define RTC_CR_OSEL_0   0x00200000U
 
#define RTC_CR_OSEL_1   0x00400000U
 
#define RTC_CR_POL   0x00100000U
 
#define RTC_CR_COSEL   0x00080000U
 
#define RTC_CR_BKP   0x00040000U
 
#define RTC_CR_SUB1H   0x00020000U
 
#define RTC_CR_ADD1H   0x00010000U
 
#define RTC_CR_TSIE   0x00008000U
 
#define RTC_CR_WUTIE   0x00004000U
 
#define RTC_CR_ALRBIE   0x00002000U
 
#define RTC_CR_ALRAIE   0x00001000U
 
#define RTC_CR_TSE   0x00000800U
 
#define RTC_CR_WUTE   0x00000400U
 
#define RTC_CR_ALRBE   0x00000200U
 
#define RTC_CR_ALRAE   0x00000100U
 
#define RTC_CR_FMT   0x00000040U
 
#define RTC_CR_BYPSHAD   0x00000020U
 
#define RTC_CR_REFCKON   0x00000010U
 
#define RTC_CR_TSEDGE   0x00000008U
 
#define RTC_CR_WUCKSEL   0x00000007U
 
#define RTC_CR_WUCKSEL_0   0x00000001U
 
#define RTC_CR_WUCKSEL_1   0x00000002U
 
#define RTC_CR_WUCKSEL_2   0x00000004U
 
#define RTC_CR_BCK   RTC_CR_BKP
 
#define RTC_ISR_ITSF   0x00020000U
 
#define RTC_ISR_RECALPF   0x00010000U
 
#define RTC_ISR_TAMP3F   0x00008000U
 
#define RTC_ISR_TAMP2F   0x00004000U
 
#define RTC_ISR_TAMP1F   0x00002000U
 
#define RTC_ISR_TSOVF   0x00001000U
 
#define RTC_ISR_TSF   0x00000800U
 
#define RTC_ISR_WUTF   0x00000400U
 
#define RTC_ISR_ALRBF   0x00000200U
 
#define RTC_ISR_ALRAF   0x00000100U
 
#define RTC_ISR_INIT   0x00000080U
 
#define RTC_ISR_INITF   0x00000040U
 
#define RTC_ISR_RSF   0x00000020U
 
#define RTC_ISR_INITS   0x00000010U
 
#define RTC_ISR_SHPF   0x00000008U
 
#define RTC_ISR_WUTWF   0x00000004U
 
#define RTC_ISR_ALRBWF   0x00000002U
 
#define RTC_ISR_ALRAWF   0x00000001U
 
#define RTC_PRER_PREDIV_A   0x007F0000U
 
#define RTC_PRER_PREDIV_S   0x00007FFFU
 
#define RTC_WUTR_WUT   0x0000FFFFU
 
#define RTC_ALRMAR_MSK4   0x80000000U
 
#define RTC_ALRMAR_WDSEL   0x40000000U
 
#define RTC_ALRMAR_DT   0x30000000U
 
#define RTC_ALRMAR_DT_0   0x10000000U
 
#define RTC_ALRMAR_DT_1   0x20000000U
 
#define RTC_ALRMAR_DU   0x0F000000U
 
#define RTC_ALRMAR_DU_0   0x01000000U
 
#define RTC_ALRMAR_DU_1   0x02000000U
 
#define RTC_ALRMAR_DU_2   0x04000000U
 
#define RTC_ALRMAR_DU_3   0x08000000U
 
#define RTC_ALRMAR_MSK3   0x00800000U
 
#define RTC_ALRMAR_PM   0x00400000U
 
#define RTC_ALRMAR_HT   0x00300000U
 
#define RTC_ALRMAR_HT_0   0x00100000U
 
#define RTC_ALRMAR_HT_1   0x00200000U
 
#define RTC_ALRMAR_HU   0x000F0000U
 
#define RTC_ALRMAR_HU_0   0x00010000U
 
#define RTC_ALRMAR_HU_1   0x00020000U
 
#define RTC_ALRMAR_HU_2   0x00040000U
 
#define RTC_ALRMAR_HU_3   0x00080000U
 
#define RTC_ALRMAR_MSK2   0x00008000U
 
#define RTC_ALRMAR_MNT   0x00007000U
 
#define RTC_ALRMAR_MNT_0   0x00001000U
 
#define RTC_ALRMAR_MNT_1   0x00002000U
 
#define RTC_ALRMAR_MNT_2   0x00004000U
 
#define RTC_ALRMAR_MNU   0x00000F00U
 
#define RTC_ALRMAR_MNU_0   0x00000100U
 
#define RTC_ALRMAR_MNU_1   0x00000200U
 
#define RTC_ALRMAR_MNU_2   0x00000400U
 
#define RTC_ALRMAR_MNU_3   0x00000800U
 
#define RTC_ALRMAR_MSK1   0x00000080U
 
#define RTC_ALRMAR_ST   0x00000070U
 
#define RTC_ALRMAR_ST_0   0x00000010U
 
#define RTC_ALRMAR_ST_1   0x00000020U
 
#define RTC_ALRMAR_ST_2   0x00000040U
 
#define RTC_ALRMAR_SU   0x0000000FU
 
#define RTC_ALRMAR_SU_0   0x00000001U
 
#define RTC_ALRMAR_SU_1   0x00000002U
 
#define RTC_ALRMAR_SU_2   0x00000004U
 
#define RTC_ALRMAR_SU_3   0x00000008U
 
#define RTC_ALRMBR_MSK4   0x80000000U
 
#define RTC_ALRMBR_WDSEL   0x40000000U
 
#define RTC_ALRMBR_DT   0x30000000U
 
#define RTC_ALRMBR_DT_0   0x10000000U
 
#define RTC_ALRMBR_DT_1   0x20000000U
 
#define RTC_ALRMBR_DU   0x0F000000U
 
#define RTC_ALRMBR_DU_0   0x01000000U
 
#define RTC_ALRMBR_DU_1   0x02000000U
 
#define RTC_ALRMBR_DU_2   0x04000000U
 
#define RTC_ALRMBR_DU_3   0x08000000U
 
#define RTC_ALRMBR_MSK3   0x00800000U
 
#define RTC_ALRMBR_PM   0x00400000U
 
#define RTC_ALRMBR_HT   0x00300000U
 
#define RTC_ALRMBR_HT_0   0x00100000U
 
#define RTC_ALRMBR_HT_1   0x00200000U
 
#define RTC_ALRMBR_HU   0x000F0000U
 
#define RTC_ALRMBR_HU_0   0x00010000U
 
#define RTC_ALRMBR_HU_1   0x00020000U
 
#define RTC_ALRMBR_HU_2   0x00040000U
 
#define RTC_ALRMBR_HU_3   0x00080000U
 
#define RTC_ALRMBR_MSK2   0x00008000U
 
#define RTC_ALRMBR_MNT   0x00007000U
 
#define RTC_ALRMBR_MNT_0   0x00001000U
 
#define RTC_ALRMBR_MNT_1   0x00002000U
 
#define RTC_ALRMBR_MNT_2   0x00004000U
 
#define RTC_ALRMBR_MNU   0x00000F00U
 
#define RTC_ALRMBR_MNU_0   0x00000100U
 
#define RTC_ALRMBR_MNU_1   0x00000200U
 
#define RTC_ALRMBR_MNU_2   0x00000400U
 
#define RTC_ALRMBR_MNU_3   0x00000800U
 
#define RTC_ALRMBR_MSK1   0x00000080U
 
#define RTC_ALRMBR_ST   0x00000070U
 
#define RTC_ALRMBR_ST_0   0x00000010U
 
#define RTC_ALRMBR_ST_1   0x00000020U
 
#define RTC_ALRMBR_ST_2   0x00000040U
 
#define RTC_ALRMBR_SU   0x0000000FU
 
#define RTC_ALRMBR_SU_0   0x00000001U
 
#define RTC_ALRMBR_SU_1   0x00000002U
 
#define RTC_ALRMBR_SU_2   0x00000004U
 
#define RTC_ALRMBR_SU_3   0x00000008U
 
#define RTC_WPR_KEY   0x000000FFU
 
#define RTC_SSR_SS   0x0000FFFFU
 
#define RTC_SHIFTR_SUBFS   0x00007FFFU
 
#define RTC_SHIFTR_ADD1S   0x80000000U
 
#define RTC_TSTR_PM   0x00400000U
 
#define RTC_TSTR_HT   0x00300000U
 
#define RTC_TSTR_HT_0   0x00100000U
 
#define RTC_TSTR_HT_1   0x00200000U
 
#define RTC_TSTR_HU   0x000F0000U
 
#define RTC_TSTR_HU_0   0x00010000U
 
#define RTC_TSTR_HU_1   0x00020000U
 
#define RTC_TSTR_HU_2   0x00040000U
 
#define RTC_TSTR_HU_3   0x00080000U
 
#define RTC_TSTR_MNT   0x00007000U
 
#define RTC_TSTR_MNT_0   0x00001000U
 
#define RTC_TSTR_MNT_1   0x00002000U
 
#define RTC_TSTR_MNT_2   0x00004000U
 
#define RTC_TSTR_MNU   0x00000F00U
 
#define RTC_TSTR_MNU_0   0x00000100U
 
#define RTC_TSTR_MNU_1   0x00000200U
 
#define RTC_TSTR_MNU_2   0x00000400U
 
#define RTC_TSTR_MNU_3   0x00000800U
 
#define RTC_TSTR_ST   0x00000070U
 
#define RTC_TSTR_ST_0   0x00000010U
 
#define RTC_TSTR_ST_1   0x00000020U
 
#define RTC_TSTR_ST_2   0x00000040U
 
#define RTC_TSTR_SU   0x0000000FU
 
#define RTC_TSTR_SU_0   0x00000001U
 
#define RTC_TSTR_SU_1   0x00000002U
 
#define RTC_TSTR_SU_2   0x00000004U
 
#define RTC_TSTR_SU_3   0x00000008U
 
#define RTC_TSDR_WDU   0x0000E000U
 
#define RTC_TSDR_WDU_0   0x00002000U
 
#define RTC_TSDR_WDU_1   0x00004000U
 
#define RTC_TSDR_WDU_2   0x00008000U
 
#define RTC_TSDR_MT   0x00001000U
 
#define RTC_TSDR_MU   0x00000F00U
 
#define RTC_TSDR_MU_0   0x00000100U
 
#define RTC_TSDR_MU_1   0x00000200U
 
#define RTC_TSDR_MU_2   0x00000400U
 
#define RTC_TSDR_MU_3   0x00000800U
 
#define RTC_TSDR_DT   0x00000030U
 
#define RTC_TSDR_DT_0   0x00000010U
 
#define RTC_TSDR_DT_1   0x00000020U
 
#define RTC_TSDR_DU   0x0000000FU
 
#define RTC_TSDR_DU_0   0x00000001U
 
#define RTC_TSDR_DU_1   0x00000002U
 
#define RTC_TSDR_DU_2   0x00000004U
 
#define RTC_TSDR_DU_3   0x00000008U
 
#define RTC_TSSSR_SS   0x0000FFFFU
 
#define RTC_CALR_CALP   0x00008000U
 
#define RTC_CALR_CALW8   0x00004000U
 
#define RTC_CALR_CALW16   0x00002000U
 
#define RTC_CALR_CALM   0x000001FFU
 
#define RTC_CALR_CALM_0   0x00000001U
 
#define RTC_CALR_CALM_1   0x00000002U
 
#define RTC_CALR_CALM_2   0x00000004U
 
#define RTC_CALR_CALM_3   0x00000008U
 
#define RTC_CALR_CALM_4   0x00000010U
 
#define RTC_CALR_CALM_5   0x00000020U
 
#define RTC_CALR_CALM_6   0x00000040U
 
#define RTC_CALR_CALM_7   0x00000080U
 
#define RTC_CALR_CALM_8   0x00000100U
 
#define RTC_TAMPCR_TAMP3MF   0x01000000U
 
#define RTC_TAMPCR_TAMP3NOERASE   0x00800000U
 
#define RTC_TAMPCR_TAMP3IE   0x00400000U
 
#define RTC_TAMPCR_TAMP2MF   0x00200000U
 
#define RTC_TAMPCR_TAMP2NOERASE   0x00100000U
 
#define RTC_TAMPCR_TAMP2IE   0x00080000U
 
#define RTC_TAMPCR_TAMP1MF   0x00040000U
 
#define RTC_TAMPCR_TAMP1NOERASE   0x00020000U
 
#define RTC_TAMPCR_TAMP1IE   0x00010000U
 
#define RTC_TAMPCR_TAMPPUDIS   0x00008000U
 
#define RTC_TAMPCR_TAMPPRCH   0x00006000U
 
#define RTC_TAMPCR_TAMPPRCH_0   0x00002000U
 
#define RTC_TAMPCR_TAMPPRCH_1   0x00004000U
 
#define RTC_TAMPCR_TAMPFLT   0x00001800U
 
#define RTC_TAMPCR_TAMPFLT_0   0x00000800U
 
#define RTC_TAMPCR_TAMPFLT_1   0x00001000U
 
#define RTC_TAMPCR_TAMPFREQ   0x00000700U
 
#define RTC_TAMPCR_TAMPFREQ_0   0x00000100U
 
#define RTC_TAMPCR_TAMPFREQ_1   0x00000200U
 
#define RTC_TAMPCR_TAMPFREQ_2   0x00000400U
 
#define RTC_TAMPCR_TAMPTS   0x00000080U
 
#define RTC_TAMPCR_TAMP3TRG   0x00000040U
 
#define RTC_TAMPCR_TAMP3E   0x00000020U
 
#define RTC_TAMPCR_TAMP2TRG   0x00000010U
 
#define RTC_TAMPCR_TAMP2E   0x00000008U
 
#define RTC_TAMPCR_TAMPIE   0x00000004U
 
#define RTC_TAMPCR_TAMP1TRG   0x00000002U
 
#define RTC_TAMPCR_TAMP1E   0x00000001U
 
#define RTC_TAMPCR_TAMP3_TRG   RTC_TAMPCR_TAMP3TRG
 
#define RTC_TAMPCR_TAMP2_TRG   RTC_TAMPCR_TAMP2TRG
 
#define RTC_TAMPCR_TAMP1_TRG   RTC_TAMPCR_TAMP1TRG
 
#define RTC_ALRMASSR_MASKSS   0x0F000000U
 
#define RTC_ALRMASSR_MASKSS_0   0x01000000U
 
#define RTC_ALRMASSR_MASKSS_1   0x02000000U
 
#define RTC_ALRMASSR_MASKSS_2   0x04000000U
 
#define RTC_ALRMASSR_MASKSS_3   0x08000000U
 
#define RTC_ALRMASSR_SS   0x00007FFFU
 
#define RTC_ALRMBSSR_MASKSS   0x0F000000U
 
#define RTC_ALRMBSSR_MASKSS_0   0x01000000U
 
#define RTC_ALRMBSSR_MASKSS_1   0x02000000U
 
#define RTC_ALRMBSSR_MASKSS_2   0x04000000U
 
#define RTC_ALRMBSSR_MASKSS_3   0x08000000U
 
#define RTC_ALRMBSSR_SS   0x00007FFFU
 
#define RTC_OR_TSINSEL   0x00000006U
 
#define RTC_OR_TSINSEL_0   0x00000002U
 
#define RTC_OR_TSINSEL_1   0x00000004U
 
#define RTC_OR_ALARMTYPE   0x00000008U
 
#define RTC_BKP0R   0xFFFFFFFFU
 
#define RTC_BKP1R   0xFFFFFFFFU
 
#define RTC_BKP2R   0xFFFFFFFFU
 
#define RTC_BKP3R   0xFFFFFFFFU
 
#define RTC_BKP4R   0xFFFFFFFFU
 
#define RTC_BKP5R   0xFFFFFFFFU
 
#define RTC_BKP6R   0xFFFFFFFFU
 
#define RTC_BKP7R   0xFFFFFFFFU
 
#define RTC_BKP8R   0xFFFFFFFFU
 
#define RTC_BKP9R   0xFFFFFFFFU
 
#define RTC_BKP10R   0xFFFFFFFFU
 
#define RTC_BKP11R   0xFFFFFFFFU
 
#define RTC_BKP12R   0xFFFFFFFFU
 
#define RTC_BKP13R   0xFFFFFFFFU
 
#define RTC_BKP14R   0xFFFFFFFFU
 
#define RTC_BKP15R   0xFFFFFFFFU
 
#define RTC_BKP16R   0xFFFFFFFFU
 
#define RTC_BKP17R   0xFFFFFFFFU
 
#define RTC_BKP18R   0xFFFFFFFFU
 
#define RTC_BKP19R   0xFFFFFFFFU
 
#define RTC_BKP20R   0xFFFFFFFFU
 
#define RTC_BKP21R   0xFFFFFFFFU
 
#define RTC_BKP22R   0xFFFFFFFFU
 
#define RTC_BKP23R   0xFFFFFFFFU
 
#define RTC_BKP24R   0xFFFFFFFFU
 
#define RTC_BKP25R   0xFFFFFFFFU
 
#define RTC_BKP26R   0xFFFFFFFFU
 
#define RTC_BKP27R   0xFFFFFFFFU
 
#define RTC_BKP28R   0xFFFFFFFFU
 
#define RTC_BKP29R   0xFFFFFFFFU
 
#define RTC_BKP30R   0xFFFFFFFFU
 
#define RTC_BKP31R   0xFFFFFFFFU
 
#define RTC_BKP_NUMBER   0x00000020U
 
#define SAI_GCR_SYNCIN   0x00000003U
 
#define SAI_GCR_SYNCIN_0   0x00000001U
 
#define SAI_GCR_SYNCIN_1   0x00000002U
 
#define SAI_GCR_SYNCOUT   0x00000030U
 
#define SAI_GCR_SYNCOUT_0   0x00000010U
 
#define SAI_GCR_SYNCOUT_1   0x00000020U
 
#define SAI_xCR1_MODE   0x00000003U
 
#define SAI_xCR1_MODE_0   0x00000001U
 
#define SAI_xCR1_MODE_1   0x00000002U
 
#define SAI_xCR1_PRTCFG   0x0000000CU
 
#define SAI_xCR1_PRTCFG_0   0x00000004U
 
#define SAI_xCR1_PRTCFG_1   0x00000008U
 
#define SAI_xCR1_DS   0x000000E0U
 
#define SAI_xCR1_DS_0   0x00000020U
 
#define SAI_xCR1_DS_1   0x00000040U
 
#define SAI_xCR1_DS_2   0x00000080U
 
#define SAI_xCR1_LSBFIRST   0x00000100U
 
#define SAI_xCR1_CKSTR   0x00000200U
 
#define SAI_xCR1_SYNCEN   0x00000C00U
 
#define SAI_xCR1_SYNCEN_0   0x00000400U
 
#define SAI_xCR1_SYNCEN_1   0x00000800U
 
#define SAI_xCR1_MONO   0x00001000U
 
#define SAI_xCR1_OUTDRIV   0x00002000U
 
#define SAI_xCR1_SAIEN   0x00010000U
 
#define SAI_xCR1_DMAEN   0x00020000U
 
#define SAI_xCR1_NODIV   0x00080000U
 
#define SAI_xCR1_MCKDIV   0x00F00000U
 
#define SAI_xCR1_MCKDIV_0   0x00100000U
 
#define SAI_xCR1_MCKDIV_1   0x00200000U
 
#define SAI_xCR1_MCKDIV_2   0x00400000U
 
#define SAI_xCR1_MCKDIV_3   0x00800000U
 
#define SAI_xCR2_FTH   0x00000007U
 
#define SAI_xCR2_FTH_0   0x00000001U
 
#define SAI_xCR2_FTH_1   0x00000002U
 
#define SAI_xCR2_FTH_2   0x00000004U
 
#define SAI_xCR2_FFLUSH   0x00000008U
 
#define SAI_xCR2_TRIS   0x00000010U
 
#define SAI_xCR2_MUTE   0x00000020U
 
#define SAI_xCR2_MUTEVAL   0x00000040U
 
#define SAI_xCR2_MUTECNT   0x00001F80U
 
#define SAI_xCR2_MUTECNT_0   0x00000080U
 
#define SAI_xCR2_MUTECNT_1   0x00000100U
 
#define SAI_xCR2_MUTECNT_2   0x00000200U
 
#define SAI_xCR2_MUTECNT_3   0x00000400U
 
#define SAI_xCR2_MUTECNT_4   0x00000800U
 
#define SAI_xCR2_MUTECNT_5   0x00001000U
 
#define SAI_xCR2_CPL   0x00002000U
 
#define SAI_xCR2_COMP   0x0000C000U
 
#define SAI_xCR2_COMP_0   0x00004000U
 
#define SAI_xCR2_COMP_1   0x00008000U
 
#define SAI_xFRCR_FRL   0x000000FFU
 
#define SAI_xFRCR_FRL_0   0x00000001U
 
#define SAI_xFRCR_FRL_1   0x00000002U
 
#define SAI_xFRCR_FRL_2   0x00000004U
 
#define SAI_xFRCR_FRL_3   0x00000008U
 
#define SAI_xFRCR_FRL_4   0x00000010U
 
#define SAI_xFRCR_FRL_5   0x00000020U
 
#define SAI_xFRCR_FRL_6   0x00000040U
 
#define SAI_xFRCR_FRL_7   0x00000080U
 
#define SAI_xFRCR_FSALL   0x00007F00U
 
#define SAI_xFRCR_FSALL_0   0x00000100U
 
#define SAI_xFRCR_FSALL_1   0x00000200U
 
#define SAI_xFRCR_FSALL_2   0x00000400U
 
#define SAI_xFRCR_FSALL_3   0x00000800U
 
#define SAI_xFRCR_FSALL_4   0x00001000U
 
#define SAI_xFRCR_FSALL_5   0x00002000U
 
#define SAI_xFRCR_FSALL_6   0x00004000U
 
#define SAI_xFRCR_FSDEF   0x00010000U
 
#define SAI_xFRCR_FSPOL   0x00020000U
 
#define SAI_xFRCR_FSOFF   0x00040000U
 
#define SAI_xFRCR_FSPO   SAI_xFRCR_FSPOL
 
#define SAI_xSLOTR_FBOFF   0x0000001FU
 
#define SAI_xSLOTR_FBOFF_0   0x00000001U
 
#define SAI_xSLOTR_FBOFF_1   0x00000002U
 
#define SAI_xSLOTR_FBOFF_2   0x00000004U
 
#define SAI_xSLOTR_FBOFF_3   0x00000008U
 
#define SAI_xSLOTR_FBOFF_4   0x00000010U
 
#define SAI_xSLOTR_SLOTSZ   0x000000C0U
 
#define SAI_xSLOTR_SLOTSZ_0   0x00000040U
 
#define SAI_xSLOTR_SLOTSZ_1   0x00000080U
 
#define SAI_xSLOTR_NBSLOT   0x00000F00U
 
#define SAI_xSLOTR_NBSLOT_0   0x00000100U
 
#define SAI_xSLOTR_NBSLOT_1   0x00000200U
 
#define SAI_xSLOTR_NBSLOT_2   0x00000400U
 
#define SAI_xSLOTR_NBSLOT_3   0x00000800U
 
#define SAI_xSLOTR_SLOTEN   0xFFFF0000U
 
#define SAI_xIMR_OVRUDRIE   0x00000001U
 
#define SAI_xIMR_MUTEDETIE   0x00000002U
 
#define SAI_xIMR_WCKCFGIE   0x00000004U
 
#define SAI_xIMR_FREQIE   0x00000008U
 
#define SAI_xIMR_CNRDYIE   0x00000010U
 
#define SAI_xIMR_AFSDETIE   0x00000020U
 
#define SAI_xIMR_LFSDETIE   0x00000040U
 
#define SAI_xSR_OVRUDR   0x00000001U
 
#define SAI_xSR_MUTEDET   0x00000002U
 
#define SAI_xSR_WCKCFG   0x00000004U
 
#define SAI_xSR_FREQ   0x00000008U
 
#define SAI_xSR_CNRDY   0x00000010U
 
#define SAI_xSR_AFSDET   0x00000020U
 
#define SAI_xSR_LFSDET   0x00000040U
 
#define SAI_xSR_FLVL   0x00070000U
 
#define SAI_xSR_FLVL_0   0x00010000U
 
#define SAI_xSR_FLVL_1   0x00020000U
 
#define SAI_xSR_FLVL_2   0x00040000U
 
#define SAI_xCLRFR_COVRUDR   0x00000001U
 
#define SAI_xCLRFR_CMUTEDET   0x00000002U
 
#define SAI_xCLRFR_CWCKCFG   0x00000004U
 
#define SAI_xCLRFR_CFREQ   0x00000008U
 
#define SAI_xCLRFR_CCNRDY   0x00000010U
 
#define SAI_xCLRFR_CAFSDET   0x00000020U
 
#define SAI_xCLRFR_CLFSDET   0x00000040U
 
#define SAI_xDR_DATA   0xFFFFFFFFU
 
#define SPDIFRX_CR_SPDIFEN   0x00000003U
 
#define SPDIFRX_CR_RXDMAEN   0x00000004U
 
#define SPDIFRX_CR_RXSTEO   0x00000008U
 
#define SPDIFRX_CR_DRFMT   0x00000030U
 
#define SPDIFRX_CR_PMSK   0x00000040U
 
#define SPDIFRX_CR_VMSK   0x00000080U
 
#define SPDIFRX_CR_CUMSK   0x00000100U
 
#define SPDIFRX_CR_PTMSK   0x00000200U
 
#define SPDIFRX_CR_CBDMAEN   0x00000400U
 
#define SPDIFRX_CR_CHSEL   0x00000800U
 
#define SPDIFRX_CR_NBTR   0x00003000U
 
#define SPDIFRX_CR_WFA   0x00004000U
 
#define SPDIFRX_CR_INSEL   0x00070000U
 
#define SPDIFRX_IMR_RXNEIE   0x00000001U
 
#define SPDIFRX_IMR_CSRNEIE   0x00000002U
 
#define SPDIFRX_IMR_PERRIE   0x00000004U
 
#define SPDIFRX_IMR_OVRIE   0x00000008U
 
#define SPDIFRX_IMR_SBLKIE   0x00000010U
 
#define SPDIFRX_IMR_SYNCDIE   0x00000020U
 
#define SPDIFRX_IMR_IFEIE   0x00000040U
 
#define SPDIFRX_SR_RXNE   0x00000001U
 
#define SPDIFRX_SR_CSRNE   0x00000002U
 
#define SPDIFRX_SR_PERR   0x00000004U
 
#define SPDIFRX_SR_OVR   0x00000008U
 
#define SPDIFRX_SR_SBD   0x00000010U
 
#define SPDIFRX_SR_SYNCD   0x00000020U
 
#define SPDIFRX_SR_FERR   0x00000040U
 
#define SPDIFRX_SR_SERR   0x00000080U
 
#define SPDIFRX_SR_TERR   0x00000100U
 
#define SPDIFRX_SR_WIDTH5   0x7FFF0000U
 
#define SPDIFRX_IFCR_PERRCF   0x00000004U
 
#define SPDIFRX_IFCR_OVRCF   0x00000008U
 
#define SPDIFRX_IFCR_SBDCF   0x00000010U
 
#define SPDIFRX_IFCR_SYNCDCF   0x00000020U
 
#define SPDIFRX_DR0_DR   0x00FFFFFFU
 
#define SPDIFRX_DR0_PE   0x01000000U
 
#define SPDIFRX_DR0_V   0x02000000U
 
#define SPDIFRX_DR0_U   0x04000000U
 
#define SPDIFRX_DR0_C   0x08000000U
 
#define SPDIFRX_DR0_PT   0x30000000U
 
#define SPDIFRX_DR1_DR   0xFFFFFF00U
 
#define SPDIFRX_DR1_PT   0x00000030U
 
#define SPDIFRX_DR1_C   0x00000008U
 
#define SPDIFRX_DR1_U   0x00000004U
 
#define SPDIFRX_DR1_V   0x00000002U
 
#define SPDIFRX_DR1_PE   0x00000001U
 
#define SPDIFRX_DR1_DRNL1   0xFFFF0000U
 
#define SPDIFRX_DR1_DRNL2   0x0000FFFFU
 
#define SPDIFRX_CSR_USR   0x0000FFFFU
 
#define SPDIFRX_CSR_CS   0x00FF0000U
 
#define SPDIFRX_CSR_SOB   0x01000000U
 
#define SPDIFRX_DIR_THI   0x000013FFU
 
#define SPDIFRX_DIR_TLO   0x1FFF0000U
 
#define SDMMC_POWER_PWRCTRL   0x03U
 
#define SDMMC_POWER_PWRCTRL_0   0x01U
 
#define SDMMC_POWER_PWRCTRL_1   0x02U
 
#define SDMMC_CLKCR_CLKDIV   0x00FFU
 
#define SDMMC_CLKCR_CLKEN   0x0100U
 
#define SDMMC_CLKCR_PWRSAV   0x0200U
 
#define SDMMC_CLKCR_BYPASS   0x0400U
 
#define SDMMC_CLKCR_WIDBUS   0x1800U
 
#define SDMMC_CLKCR_WIDBUS_0   0x0800U
 
#define SDMMC_CLKCR_WIDBUS_1   0x1000U
 
#define SDMMC_CLKCR_NEGEDGE   0x2000U
 
#define SDMMC_CLKCR_HWFC_EN   0x4000U
 
#define SDMMC_ARG_CMDARG   0xFFFFFFFFU
 
#define SDMMC_CMD_CMDINDEX   0x003FU
 
#define SDMMC_CMD_WAITRESP   0x00C0U
 
#define SDMMC_CMD_WAITRESP_0   0x0040U
 
#define SDMMC_CMD_WAITRESP_1   0x0080U
 
#define SDMMC_CMD_WAITINT   0x0100U
 
#define SDMMC_CMD_WAITPEND   0x0200U
 
#define SDMMC_CMD_CPSMEN   0x0400U
 
#define SDMMC_CMD_SDIOSUSPEND   0x0800U
 
#define SDMMC_RESPCMD_RESPCMD   0x3FU
 
#define SDMMC_RESP0_CARDSTATUS0   0xFFFFFFFFU
 
#define SDMMC_RESP1_CARDSTATUS1   0xFFFFFFFFU
 
#define SDMMC_RESP2_CARDSTATUS2   0xFFFFFFFFU
 
#define SDMMC_RESP3_CARDSTATUS3   0xFFFFFFFFU
 
#define SDMMC_RESP4_CARDSTATUS4   0xFFFFFFFFU
 
#define SDMMC_DTIMER_DATATIME   0xFFFFFFFFU
 
#define SDMMC_DLEN_DATALENGTH   0x01FFFFFFU
 
#define SDMMC_DCTRL_DTEN   0x0001U
 
#define SDMMC_DCTRL_DTDIR   0x0002U
 
#define SDMMC_DCTRL_DTMODE   0x0004U
 
#define SDMMC_DCTRL_DMAEN   0x0008U
 
#define SDMMC_DCTRL_DBLOCKSIZE   0x00F0U
 
#define SDMMC_DCTRL_DBLOCKSIZE_0   0x0010U
 
#define SDMMC_DCTRL_DBLOCKSIZE_1   0x0020U
 
#define SDMMC_DCTRL_DBLOCKSIZE_2   0x0040U
 
#define SDMMC_DCTRL_DBLOCKSIZE_3   0x0080U
 
#define SDMMC_DCTRL_RWSTART   0x0100U
 
#define SDMMC_DCTRL_RWSTOP   0x0200U
 
#define SDMMC_DCTRL_RWMOD   0x0400U
 
#define SDMMC_DCTRL_SDIOEN   0x0800U
 
#define SDMMC_DCOUNT_DATACOUNT   0x01FFFFFFU
 
#define SDMMC_STA_CCRCFAIL   0x00000001U
 
#define SDMMC_STA_DCRCFAIL   0x00000002U
 
#define SDMMC_STA_CTIMEOUT   0x00000004U
 
#define SDMMC_STA_DTIMEOUT   0x00000008U
 
#define SDMMC_STA_TXUNDERR   0x00000010U
 
#define SDMMC_STA_RXOVERR   0x00000020U
 
#define SDMMC_STA_CMDREND   0x00000040U
 
#define SDMMC_STA_CMDSENT   0x00000080U
 
#define SDMMC_STA_DATAEND   0x00000100U
 
#define SDMMC_STA_DBCKEND   0x00000400U
 
#define SDMMC_STA_CMDACT   0x00000800U
 
#define SDMMC_STA_TXACT   0x00001000U
 
#define SDMMC_STA_RXACT   0x00002000U
 
#define SDMMC_STA_TXFIFOHE   0x00004000U
 
#define SDMMC_STA_RXFIFOHF   0x00008000U
 
#define SDMMC_STA_TXFIFOF   0x00010000U
 
#define SDMMC_STA_RXFIFOF   0x00020000U
 
#define SDMMC_STA_TXFIFOE   0x00040000U
 
#define SDMMC_STA_RXFIFOE   0x00080000U
 
#define SDMMC_STA_TXDAVL   0x00100000U
 
#define SDMMC_STA_RXDAVL   0x00200000U
 
#define SDMMC_STA_SDIOIT   0x00400000U
 
#define SDMMC_ICR_CCRCFAILC   0x00000001U
 
#define SDMMC_ICR_DCRCFAILC   0x00000002U
 
#define SDMMC_ICR_CTIMEOUTC   0x00000004U
 
#define SDMMC_ICR_DTIMEOUTC   0x00000008U
 
#define SDMMC_ICR_TXUNDERRC   0x00000010U
 
#define SDMMC_ICR_RXOVERRC   0x00000020U
 
#define SDMMC_ICR_CMDRENDC   0x00000040U
 
#define SDMMC_ICR_CMDSENTC   0x00000080U
 
#define SDMMC_ICR_DATAENDC   0x00000100U
 
#define SDMMC_ICR_DBCKENDC   0x00000400U
 
#define SDMMC_ICR_SDIOITC   0x00400000U
 
#define SDMMC_MASK_CCRCFAILIE   0x00000001U
 
#define SDMMC_MASK_DCRCFAILIE   0x00000002U
 
#define SDMMC_MASK_CTIMEOUTIE   0x00000004U
 
#define SDMMC_MASK_DTIMEOUTIE   0x00000008U
 
#define SDMMC_MASK_TXUNDERRIE   0x00000010U
 
#define SDMMC_MASK_RXOVERRIE   0x00000020U
 
#define SDMMC_MASK_CMDRENDIE   0x00000040U
 
#define SDMMC_MASK_CMDSENTIE   0x00000080U
 
#define SDMMC_MASK_DATAENDIE   0x00000100U
 
#define SDMMC_MASK_DBCKENDIE   0x00000400U
 
#define SDMMC_MASK_CMDACTIE   0x00000800U
 
#define SDMMC_MASK_TXACTIE   0x00001000U
 
#define SDMMC_MASK_RXACTIE   0x00002000U
 
#define SDMMC_MASK_TXFIFOHEIE   0x00004000U
 
#define SDMMC_MASK_RXFIFOHFIE   0x00008000U
 
#define SDMMC_MASK_TXFIFOFIE   0x00010000U
 
#define SDMMC_MASK_RXFIFOFIE   0x00020000U
 
#define SDMMC_MASK_TXFIFOEIE   0x00040000U
 
#define SDMMC_MASK_RXFIFOEIE   0x00080000U
 
#define SDMMC_MASK_TXDAVLIE   0x00100000U
 
#define SDMMC_MASK_RXDAVLIE   0x00200000U
 
#define SDMMC_MASK_SDIOITIE   0x00400000U
 
#define SDMMC_FIFOCNT_FIFOCOUNT   0x00FFFFFFU
 
#define SDMMC_FIFO_FIFODATA   0xFFFFFFFFU
 
#define SPI_CR1_CPHA   0x00000001U
 
#define SPI_CR1_CPOL   0x00000002U
 
#define SPI_CR1_MSTR   0x00000004U
 
#define SPI_CR1_BR   0x00000038U
 
#define SPI_CR1_BR_0   0x00000008U
 
#define SPI_CR1_BR_1   0x00000010U
 
#define SPI_CR1_BR_2   0x00000020U
 
#define SPI_CR1_SPE   0x00000040U
 
#define SPI_CR1_LSBFIRST   0x00000080U
 
#define SPI_CR1_SSI   0x00000100U
 
#define SPI_CR1_SSM   0x00000200U
 
#define SPI_CR1_RXONLY   0x00000400U
 
#define SPI_CR1_CRCL   0x00000800U
 
#define SPI_CR1_CRCNEXT   0x00001000U
 
#define SPI_CR1_CRCEN   0x00002000U
 
#define SPI_CR1_BIDIOE   0x00004000U
 
#define SPI_CR1_BIDIMODE   0x00008000U
 
#define SPI_CR2_RXDMAEN   0x00000001U
 
#define SPI_CR2_TXDMAEN   0x00000002U
 
#define SPI_CR2_SSOE   0x00000004U
 
#define SPI_CR2_NSSP   0x00000008U
 
#define SPI_CR2_FRF   0x00000010U
 
#define SPI_CR2_ERRIE   0x00000020U
 
#define SPI_CR2_RXNEIE   0x00000040U
 
#define SPI_CR2_TXEIE   0x00000080U
 
#define SPI_CR2_DS   0x00000F00U
 
#define SPI_CR2_DS_0   0x00000100U
 
#define SPI_CR2_DS_1   0x00000200U
 
#define SPI_CR2_DS_2   0x00000400U
 
#define SPI_CR2_DS_3   0x00000800U
 
#define SPI_CR2_FRXTH   0x00001000U
 
#define SPI_CR2_LDMARX   0x00002000U
 
#define SPI_CR2_LDMATX   0x00004000U
 
#define SPI_SR_RXNE   0x00000001U
 
#define SPI_SR_TXE   0x00000002U
 
#define SPI_SR_CHSIDE   0x00000004U
 
#define SPI_SR_UDR   0x00000008U
 
#define SPI_SR_CRCERR   0x00000010U
 
#define SPI_SR_MODF   0x00000020U
 
#define SPI_SR_OVR   0x00000040U
 
#define SPI_SR_BSY   0x00000080U
 
#define SPI_SR_FRE   0x00000100U
 
#define SPI_SR_FRLVL   0x00000600U
 
#define SPI_SR_FRLVL_0   0x00000200U
 
#define SPI_SR_FRLVL_1   0x00000400U
 
#define SPI_SR_FTLVL   0x00001800U
 
#define SPI_SR_FTLVL_0   0x00000800U
 
#define SPI_SR_FTLVL_1   0x00001000U
 
#define SPI_DR_DR   0xFFFFU
 
#define SPI_CRCPR_CRCPOLY   0xFFFFU
 
#define SPI_RXCRCR_RXCRC   0xFFFFU
 
#define SPI_TXCRCR_TXCRC   0xFFFFU
 
#define SPI_I2SCFGR_CHLEN   0x00000001U
 
#define SPI_I2SCFGR_DATLEN   0x00000006U
 
#define SPI_I2SCFGR_DATLEN_0   0x00000002U
 
#define SPI_I2SCFGR_DATLEN_1   0x00000004U
 
#define SPI_I2SCFGR_CKPOL   0x00000008U
 
#define SPI_I2SCFGR_I2SSTD   0x00000030U
 
#define SPI_I2SCFGR_I2SSTD_0   0x00000010U
 
#define SPI_I2SCFGR_I2SSTD_1   0x00000020U
 
#define SPI_I2SCFGR_PCMSYNC   0x00000080U
 
#define SPI_I2SCFGR_I2SCFG   0x00000300U
 
#define SPI_I2SCFGR_I2SCFG_0   0x00000100U
 
#define SPI_I2SCFGR_I2SCFG_1   0x00000200U
 
#define SPI_I2SCFGR_I2SE   0x00000400U
 
#define SPI_I2SCFGR_I2SMOD   0x00000800U
 
#define SPI_I2SCFGR_ASTRTEN   0x00001000U
 
#define SPI_I2SPR_I2SDIV   0x00FFU
 
#define SPI_I2SPR_ODD   0x0100U
 
#define SPI_I2SPR_MCKOE   0x0200U
 
#define SYSCFG_MEMRMP_MEM_BOOT   0x00000001U
 
#define SYSCFG_MEMRMP_SWP_FMC   0x00000C00U
 
#define SYSCFG_MEMRMP_SWP_FMC_0   0x00000400U
 
#define SYSCFG_MEMRMP_SWP_FMC_1   0x00000800U
 
#define SYSCFG_PMC_ADCxDC2   0x00070000U
 
#define SYSCFG_PMC_ADC1DC2   0x00010000U
 
#define SYSCFG_PMC_ADC2DC2   0x00020000U
 
#define SYSCFG_PMC_ADC3DC2   0x00040000U
 
#define SYSCFG_PMC_MII_RMII_SEL   0x00800000U
 
#define SYSCFG_EXTICR1_EXTI0   0x000FU
 
#define SYSCFG_EXTICR1_EXTI1   0x00F0U
 
#define SYSCFG_EXTICR1_EXTI2   0x0F00U
 
#define SYSCFG_EXTICR1_EXTI3   0xF000U
 
#define SYSCFG_EXTICR1_EXTI0_PA   0x0000U
 EXTI0 configuration. More...
 
#define SYSCFG_EXTICR1_EXTI0_PB   0x0001U
 
#define SYSCFG_EXTICR1_EXTI0_PC   0x0002U
 
#define SYSCFG_EXTICR1_EXTI0_PD   0x0003U
 
#define SYSCFG_EXTICR1_EXTI0_PE   0x0004U
 
#define SYSCFG_EXTICR1_EXTI0_PF   0x0005U
 
#define SYSCFG_EXTICR1_EXTI0_PG   0x0006U
 
#define SYSCFG_EXTICR1_EXTI0_PH   0x0007U
 
#define SYSCFG_EXTICR1_EXTI0_PI   0x0008U
 
#define SYSCFG_EXTICR1_EXTI0_PJ   0x0009U
 
#define SYSCFG_EXTICR1_EXTI0_PK   0x000AU
 
#define SYSCFG_EXTICR1_EXTI1_PA   0x0000U
 EXTI1 configuration. More...
 
#define SYSCFG_EXTICR1_EXTI1_PB   0x0010U
 
#define SYSCFG_EXTICR1_EXTI1_PC   0x0020U
 
#define SYSCFG_EXTICR1_EXTI1_PD   0x0030U
 
#define SYSCFG_EXTICR1_EXTI1_PE   0x0040U
 
#define SYSCFG_EXTICR1_EXTI1_PF   0x0050U
 
#define SYSCFG_EXTICR1_EXTI1_PG   0x0060U
 
#define SYSCFG_EXTICR1_EXTI1_PH   0x0070U
 
#define SYSCFG_EXTICR1_EXTI1_PI   0x0080U
 
#define SYSCFG_EXTICR1_EXTI1_PJ   0x0090U
 
#define SYSCFG_EXTICR1_EXTI1_PK   0x00A0U
 
#define SYSCFG_EXTICR1_EXTI2_PA   0x0000U
 EXTI2 configuration. More...
 
#define SYSCFG_EXTICR1_EXTI2_PB   0x0100U
 
#define SYSCFG_EXTICR1_EXTI2_PC   0x0200U
 
#define SYSCFG_EXTICR1_EXTI2_PD   0x0300U
 
#define SYSCFG_EXTICR1_EXTI2_PE   0x0400U
 
#define SYSCFG_EXTICR1_EXTI2_PF   0x0500U
 
#define SYSCFG_EXTICR1_EXTI2_PG   0x0600U
 
#define SYSCFG_EXTICR1_EXTI2_PH   0x0700U
 
#define SYSCFG_EXTICR1_EXTI2_PI   0x0800U
 
#define SYSCFG_EXTICR1_EXTI2_PJ   0x0900U
 
#define SYSCFG_EXTICR1_EXTI2_PK   0x0A00U
 
#define SYSCFG_EXTICR1_EXTI3_PA   0x0000U
 EXTI3 configuration. More...
 
#define SYSCFG_EXTICR1_EXTI3_PB   0x1000U
 
#define SYSCFG_EXTICR1_EXTI3_PC   0x2000U
 
#define SYSCFG_EXTICR1_EXTI3_PD   0x3000U
 
#define SYSCFG_EXTICR1_EXTI3_PE   0x4000U
 
#define SYSCFG_EXTICR1_EXTI3_PF   0x5000U
 
#define SYSCFG_EXTICR1_EXTI3_PG   0x6000U
 
#define SYSCFG_EXTICR1_EXTI3_PH   0x7000U
 
#define SYSCFG_EXTICR1_EXTI3_PI   0x8000U
 
#define SYSCFG_EXTICR1_EXTI3_PJ   0x9000U
 
#define SYSCFG_EXTICR1_EXTI3_PK   0xA000U
 
#define SYSCFG_EXTICR2_EXTI4   0x000FU
 
#define SYSCFG_EXTICR2_EXTI5   0x00F0U
 
#define SYSCFG_EXTICR2_EXTI6   0x0F00U
 
#define SYSCFG_EXTICR2_EXTI7   0xF000U
 
#define SYSCFG_EXTICR2_EXTI4_PA   0x0000U
 EXTI4 configuration. More...
 
#define SYSCFG_EXTICR2_EXTI4_PB   0x0001U
 
#define SYSCFG_EXTICR2_EXTI4_PC   0x0002U
 
#define SYSCFG_EXTICR2_EXTI4_PD   0x0003U
 
#define SYSCFG_EXTICR2_EXTI4_PE   0x0004U
 
#define SYSCFG_EXTICR2_EXTI4_PF   0x0005U
 
#define SYSCFG_EXTICR2_EXTI4_PG   0x0006U
 
#define SYSCFG_EXTICR2_EXTI4_PH   0x0007U
 
#define SYSCFG_EXTICR2_EXTI4_PI   0x0008U
 
#define SYSCFG_EXTICR2_EXTI4_PJ   0x0009U
 
#define SYSCFG_EXTICR2_EXTI4_PK   0x000AU
 
#define SYSCFG_EXTICR2_EXTI5_PA   0x0000U
 EXTI5 configuration. More...
 
#define SYSCFG_EXTICR2_EXTI5_PB   0x0010U
 
#define SYSCFG_EXTICR2_EXTI5_PC   0x0020U
 
#define SYSCFG_EXTICR2_EXTI5_PD   0x0030U
 
#define SYSCFG_EXTICR2_EXTI5_PE   0x0040U
 
#define SYSCFG_EXTICR2_EXTI5_PF   0x0050U
 
#define SYSCFG_EXTICR2_EXTI5_PG   0x0060U
 
#define SYSCFG_EXTICR2_EXTI5_PH   0x0070U
 
#define SYSCFG_EXTICR2_EXTI5_PI   0x0080U
 
#define SYSCFG_EXTICR2_EXTI5_PJ   0x0090U
 
#define SYSCFG_EXTICR2_EXTI5_PK   0x00A0U
 
#define SYSCFG_EXTICR2_EXTI6_PA   0x0000U
 EXTI6 configuration. More...
 
#define SYSCFG_EXTICR2_EXTI6_PB   0x0100U
 
#define SYSCFG_EXTICR2_EXTI6_PC   0x0200U
 
#define SYSCFG_EXTICR2_EXTI6_PD   0x0300U
 
#define SYSCFG_EXTICR2_EXTI6_PE   0x0400U
 
#define SYSCFG_EXTICR2_EXTI6_PF   0x0500U
 
#define SYSCFG_EXTICR2_EXTI6_PG   0x0600U
 
#define SYSCFG_EXTICR2_EXTI6_PH   0x0700U
 
#define SYSCFG_EXTICR2_EXTI6_PI   0x0800U
 
#define SYSCFG_EXTICR2_EXTI6_PJ   0x0900U
 
#define SYSCFG_EXTICR2_EXTI6_PK   0x0A00U
 
#define SYSCFG_EXTICR2_EXTI7_PA   0x0000U
 EXTI7 configuration. More...
 
#define SYSCFG_EXTICR2_EXTI7_PB   0x1000U
 
#define SYSCFG_EXTICR2_EXTI7_PC   0x2000U
 
#define SYSCFG_EXTICR2_EXTI7_PD   0x3000U
 
#define SYSCFG_EXTICR2_EXTI7_PE   0x4000U
 
#define SYSCFG_EXTICR2_EXTI7_PF   0x5000U
 
#define SYSCFG_EXTICR2_EXTI7_PG   0x6000U
 
#define SYSCFG_EXTICR2_EXTI7_PH   0x7000U
 
#define SYSCFG_EXTICR2_EXTI7_PI   0x8000U
 
#define SYSCFG_EXTICR2_EXTI7_PJ   0x9000U
 
#define SYSCFG_EXTICR2_EXTI7_PK   0xA000U
 
#define SYSCFG_EXTICR3_EXTI8   0x000FU
 
#define SYSCFG_EXTICR3_EXTI9   0x00F0U
 
#define SYSCFG_EXTICR3_EXTI10   0x0F00U
 
#define SYSCFG_EXTICR3_EXTI11   0xF000U
 
#define SYSCFG_EXTICR3_EXTI8_PA   0x0000U
 EXTI8 configuration. More...
 
#define SYSCFG_EXTICR3_EXTI8_PB   0x0001U
 
#define SYSCFG_EXTICR3_EXTI8_PC   0x0002U
 
#define SYSCFG_EXTICR3_EXTI8_PD   0x0003U
 
#define SYSCFG_EXTICR3_EXTI8_PE   0x0004U
 
#define SYSCFG_EXTICR3_EXTI8_PF   0x0005U
 
#define SYSCFG_EXTICR3_EXTI8_PG   0x0006U
 
#define SYSCFG_EXTICR3_EXTI8_PH   0x0007U
 
#define SYSCFG_EXTICR3_EXTI8_PI   0x0008U
 
#define SYSCFG_EXTICR3_EXTI8_PJ   0x0009U
 
#define SYSCFG_EXTICR3_EXTI9_PA   0x0000U
 EXTI9 configuration. More...
 
#define SYSCFG_EXTICR3_EXTI9_PB   0x0010U
 
#define SYSCFG_EXTICR3_EXTI9_PC   0x0020U
 
#define SYSCFG_EXTICR3_EXTI9_PD   0x0030U
 
#define SYSCFG_EXTICR3_EXTI9_PE   0x0040U
 
#define SYSCFG_EXTICR3_EXTI9_PF   0x0050U
 
#define SYSCFG_EXTICR3_EXTI9_PG   0x0060U
 
#define SYSCFG_EXTICR3_EXTI9_PH   0x0070U
 
#define SYSCFG_EXTICR3_EXTI9_PI   0x0080U
 
#define SYSCFG_EXTICR3_EXTI9_PJ   0x0090U
 
#define SYSCFG_EXTICR3_EXTI10_PA   0x0000U
 EXTI10 configuration. More...
 
#define SYSCFG_EXTICR3_EXTI10_PB   0x0100U
 
#define SYSCFG_EXTICR3_EXTI10_PC   0x0200U
 
#define SYSCFG_EXTICR3_EXTI10_PD   0x0300U
 
#define SYSCFG_EXTICR3_EXTI10_PE   0x0400U
 
#define SYSCFG_EXTICR3_EXTI10_PF   0x0500U
 
#define SYSCFG_EXTICR3_EXTI10_PG   0x0600U
 
#define SYSCFG_EXTICR3_EXTI10_PH   0x0700U
 
#define SYSCFG_EXTICR3_EXTI10_PI   0x0800U
 
#define SYSCFG_EXTICR3_EXTI10_PJ   0x0900U
 
#define SYSCFG_EXTICR3_EXTI11_PA   0x0000U
 EXTI11 configuration. More...
 
#define SYSCFG_EXTICR3_EXTI11_PB   0x1000U
 
#define SYSCFG_EXTICR3_EXTI11_PC   0x2000U
 
#define SYSCFG_EXTICR3_EXTI11_PD   0x3000U
 
#define SYSCFG_EXTICR3_EXTI11_PE   0x4000U
 
#define SYSCFG_EXTICR3_EXTI11_PF   0x5000U
 
#define SYSCFG_EXTICR3_EXTI11_PG   0x6000U
 
#define SYSCFG_EXTICR3_EXTI11_PH   0x7000U
 
#define SYSCFG_EXTICR3_EXTI11_PI   0x8000U
 
#define SYSCFG_EXTICR3_EXTI11_PJ   0x9000U
 
#define SYSCFG_EXTICR4_EXTI12   0x000FU
 
#define SYSCFG_EXTICR4_EXTI13   0x00F0U
 
#define SYSCFG_EXTICR4_EXTI14   0x0F00U
 
#define SYSCFG_EXTICR4_EXTI15   0xF000U
 
#define SYSCFG_EXTICR4_EXTI12_PA   0x0000U
 EXTI12 configuration. More...
 
#define SYSCFG_EXTICR4_EXTI12_PB   0x0001U
 
#define SYSCFG_EXTICR4_EXTI12_PC   0x0002U
 
#define SYSCFG_EXTICR4_EXTI12_PD   0x0003U
 
#define SYSCFG_EXTICR4_EXTI12_PE   0x0004U
 
#define SYSCFG_EXTICR4_EXTI12_PF   0x0005U
 
#define SYSCFG_EXTICR4_EXTI12_PG   0x0006U
 
#define SYSCFG_EXTICR4_EXTI12_PH   0x0007U
 
#define SYSCFG_EXTICR4_EXTI12_PI   0x0008U
 
#define SYSCFG_EXTICR4_EXTI12_PJ   0x0009U
 
#define SYSCFG_EXTICR4_EXTI13_PA   0x0000U
 EXTI13 configuration. More...
 
#define SYSCFG_EXTICR4_EXTI13_PB   0x0010U
 
#define SYSCFG_EXTICR4_EXTI13_PC   0x0020U
 
#define SYSCFG_EXTICR4_EXTI13_PD   0x0030U
 
#define SYSCFG_EXTICR4_EXTI13_PE   0x0040U
 
#define SYSCFG_EXTICR4_EXTI13_PF   0x0050U
 
#define SYSCFG_EXTICR4_EXTI13_PG   0x0060U
 
#define SYSCFG_EXTICR4_EXTI13_PH   0x0070U
 
#define SYSCFG_EXTICR4_EXTI13_PI   0x0080U
 
#define SYSCFG_EXTICR4_EXTI13_PJ   0x0090U
 
#define SYSCFG_EXTICR4_EXTI14_PA   0x0000U
 EXTI14 configuration. More...
 
#define SYSCFG_EXTICR4_EXTI14_PB   0x0100U
 
#define SYSCFG_EXTICR4_EXTI14_PC   0x0200U
 
#define SYSCFG_EXTICR4_EXTI14_PD   0x0300U
 
#define SYSCFG_EXTICR4_EXTI14_PE   0x0400U
 
#define SYSCFG_EXTICR4_EXTI14_PF   0x0500U
 
#define SYSCFG_EXTICR4_EXTI14_PG   0x0600U
 
#define SYSCFG_EXTICR4_EXTI14_PH   0x0700U
 
#define SYSCFG_EXTICR4_EXTI14_PI   0x0800U
 
#define SYSCFG_EXTICR4_EXTI14_PJ   0x0900U
 
#define SYSCFG_EXTICR4_EXTI15_PA   0x0000U
 EXTI15 configuration. More...
 
#define SYSCFG_EXTICR4_EXTI15_PB   0x1000U
 
#define SYSCFG_EXTICR4_EXTI15_PC   0x2000U
 
#define SYSCFG_EXTICR4_EXTI15_PD   0x3000U
 
#define SYSCFG_EXTICR4_EXTI15_PE   0x4000U
 
#define SYSCFG_EXTICR4_EXTI15_PF   0x5000U
 
#define SYSCFG_EXTICR4_EXTI15_PG   0x6000U
 
#define SYSCFG_EXTICR4_EXTI15_PH   0x7000U
 
#define SYSCFG_EXTICR4_EXTI15_PI   0x8000U
 
#define SYSCFG_EXTICR4_EXTI15_PJ   0x9000U
 
#define SYSCFG_CMPCR_CMP_PD   0x00000001U
 
#define SYSCFG_CMPCR_READY   0x00000100U
 
#define TIM_CR1_CEN   0x0001U
 
#define TIM_CR1_UDIS   0x0002U
 
#define TIM_CR1_URS   0x0004U
 
#define TIM_CR1_OPM   0x0008U
 
#define TIM_CR1_DIR   0x0010U
 
#define TIM_CR1_CMS   0x0060U
 
#define TIM_CR1_CMS_0   0x0020U
 
#define TIM_CR1_CMS_1   0x0040U
 
#define TIM_CR1_ARPE   0x0080U
 
#define TIM_CR1_CKD   0x0300U
 
#define TIM_CR1_CKD_0   0x0100U
 
#define TIM_CR1_CKD_1   0x0200U
 
#define TIM_CR1_UIFREMAP   0x0800U
 
#define TIM_CR2_CCPC   0x00000001U
 
#define TIM_CR2_CCUS   0x00000004U
 
#define TIM_CR2_CCDS   0x00000008U
 
#define TIM_CR2_OIS5   0x00010000U
 
#define TIM_CR2_OIS6   0x00040000U
 
#define TIM_CR2_MMS   0x0070U
 
#define TIM_CR2_MMS_0   0x0010U
 
#define TIM_CR2_MMS_1   0x0020U
 
#define TIM_CR2_MMS_2   0x0040U
 
#define TIM_CR2_MMS2   0x00F00000U
 
#define TIM_CR2_MMS2_0   0x00100000U
 
#define TIM_CR2_MMS2_1   0x00200000U
 
#define TIM_CR2_MMS2_2   0x00400000U
 
#define TIM_CR2_MMS2_3   0x00800000U
 
#define TIM_CR2_TI1S   0x0080U
 
#define TIM_CR2_OIS1   0x0100U
 
#define TIM_CR2_OIS1N   0x0200U
 
#define TIM_CR2_OIS2   0x0400U
 
#define TIM_CR2_OIS2N   0x0800U
 
#define TIM_CR2_OIS3   0x1000U
 
#define TIM_CR2_OIS3N   0x2000U
 
#define TIM_CR2_OIS4   0x4000U
 
#define TIM_SMCR_SMS   0x00010007U
 
#define TIM_SMCR_SMS_0   0x00000001U
 
#define TIM_SMCR_SMS_1   0x00000002U
 
#define TIM_SMCR_SMS_2   0x00000004U
 
#define TIM_SMCR_SMS_3   0x00010000U
 
#define TIM_SMCR_OCCS   0x00000008U
 
#define TIM_SMCR_TS   0x0070U
 
#define TIM_SMCR_TS_0   0x0010U
 
#define TIM_SMCR_TS_1   0x0020U
 
#define TIM_SMCR_TS_2   0x0040U
 
#define TIM_SMCR_MSM   0x0080U
 
#define TIM_SMCR_ETF   0x0F00U
 
#define TIM_SMCR_ETF_0   0x0100U
 
#define TIM_SMCR_ETF_1   0x0200U
 
#define TIM_SMCR_ETF_2   0x0400U
 
#define TIM_SMCR_ETF_3   0x0800U
 
#define TIM_SMCR_ETPS   0x3000U
 
#define TIM_SMCR_ETPS_0   0x1000U
 
#define TIM_SMCR_ETPS_1   0x2000U
 
#define TIM_SMCR_ECE   0x4000U
 
#define TIM_SMCR_ETP   0x8000U
 
#define TIM_DIER_UIE   0x0001U
 
#define TIM_DIER_CC1IE   0x0002U
 
#define TIM_DIER_CC2IE   0x0004U
 
#define TIM_DIER_CC3IE   0x0008U
 
#define TIM_DIER_CC4IE   0x0010U
 
#define TIM_DIER_COMIE   0x0020U
 
#define TIM_DIER_TIE   0x0040U
 
#define TIM_DIER_BIE   0x0080U
 
#define TIM_DIER_UDE   0x0100U
 
#define TIM_DIER_CC1DE   0x0200U
 
#define TIM_DIER_CC2DE   0x0400U
 
#define TIM_DIER_CC3DE   0x0800U
 
#define TIM_DIER_CC4DE   0x1000U
 
#define TIM_DIER_COMDE   0x2000U
 
#define TIM_DIER_TDE   0x4000U
 
#define TIM_SR_UIF   0x0001U
 
#define TIM_SR_CC1IF   0x0002U
 
#define TIM_SR_CC2IF   0x0004U
 
#define TIM_SR_CC3IF   0x0008U
 
#define TIM_SR_CC4IF   0x0010U
 
#define TIM_SR_COMIF   0x0020U
 
#define TIM_SR_TIF   0x0040U
 
#define TIM_SR_BIF   0x0080U
 
#define TIM_SR_B2IF   0x0100U
 
#define TIM_SR_CC1OF   0x0200U
 
#define TIM_SR_CC2OF   0x0400U
 
#define TIM_SR_CC3OF   0x0800U
 
#define TIM_SR_CC4OF   0x1000U
 
#define TIM_EGR_UG   0x00000001U
 
#define TIM_EGR_CC1G   0x00000002U
 
#define TIM_EGR_CC2G   0x00000004U
 
#define TIM_EGR_CC3G   0x00000008U
 
#define TIM_EGR_CC4G   0x00000010U
 
#define TIM_EGR_COMG   0x00000020U
 
#define TIM_EGR_TG   0x00000040U
 
#define TIM_EGR_BG   0x00000080U
 
#define TIM_EGR_B2G   0x00000100U
 
#define TIM_CCMR1_CC1S   0x00000003U
 
#define TIM_CCMR1_CC1S_0   0x00000001U
 
#define TIM_CCMR1_CC1S_1   0x00000002U
 
#define TIM_CCMR1_OC1FE   0x00000004U
 
#define TIM_CCMR1_OC1PE   0x00000008U
 
#define TIM_CCMR1_OC1M   0x00010070U
 
#define TIM_CCMR1_OC1M_0   0x00000010U
 
#define TIM_CCMR1_OC1M_1   0x00000020U
 
#define TIM_CCMR1_OC1M_2   0x00000040U
 
#define TIM_CCMR1_OC1M_3   0x00010000U
 
#define TIM_CCMR1_OC1CE   0x00000080U
 
#define TIM_CCMR1_CC2S   0x00000300U
 
#define TIM_CCMR1_CC2S_0   0x00000100U
 
#define TIM_CCMR1_CC2S_1   0x00000200U
 
#define TIM_CCMR1_OC2FE   0x00000400U
 
#define TIM_CCMR1_OC2PE   0x00000800U
 
#define TIM_CCMR1_OC2M   0x01007000U
 
#define TIM_CCMR1_OC2M_0   0x00001000U
 
#define TIM_CCMR1_OC2M_1   0x00002000U
 
#define TIM_CCMR1_OC2M_2   0x00004000U
 
#define TIM_CCMR1_OC2M_3   0x01000000U
 
#define TIM_CCMR1_OC2CE   0x00008000U
 
#define TIM_CCMR1_IC1PSC   0x000CU
 
#define TIM_CCMR1_IC1PSC_0   0x0004U
 
#define TIM_CCMR1_IC1PSC_1   0x0008U
 
#define TIM_CCMR1_IC1F   0x00F0U
 
#define TIM_CCMR1_IC1F_0   0x0010U
 
#define TIM_CCMR1_IC1F_1   0x0020U
 
#define TIM_CCMR1_IC1F_2   0x0040U
 
#define TIM_CCMR1_IC1F_3   0x0080U
 
#define TIM_CCMR1_IC2PSC   0x0C00U
 
#define TIM_CCMR1_IC2PSC_0   0x0400U
 
#define TIM_CCMR1_IC2PSC_1   0x0800U
 
#define TIM_CCMR1_IC2F   0xF000U
 
#define TIM_CCMR1_IC2F_0   0x1000U
 
#define TIM_CCMR1_IC2F_1   0x2000U
 
#define TIM_CCMR1_IC2F_2   0x4000U
 
#define TIM_CCMR1_IC2F_3   0x8000U
 
#define TIM_CCMR2_CC3S   0x00000003U
 
#define TIM_CCMR2_CC3S_0   0x00000001U
 
#define TIM_CCMR2_CC3S_1   0x00000002U
 
#define TIM_CCMR2_OC3FE   0x00000004U
 
#define TIM_CCMR2_OC3PE   0x00000008U
 
#define TIM_CCMR2_OC3M   0x00010070U
 
#define TIM_CCMR2_OC3M_0   0x00000010U
 
#define TIM_CCMR2_OC3M_1   0x00000020U
 
#define TIM_CCMR2_OC3M_2   0x00000040U
 
#define TIM_CCMR2_OC3M_3   0x00010000U
 
#define TIM_CCMR2_OC3CE   0x00000080U
 
#define TIM_CCMR2_CC4S   0x00000300U
 
#define TIM_CCMR2_CC4S_0   0x00000100U
 
#define TIM_CCMR2_CC4S_1   0x00000200U
 
#define TIM_CCMR2_OC4FE   0x00000400U
 
#define TIM_CCMR2_OC4PE   0x00000800U
 
#define TIM_CCMR2_OC4M   0x01007000U
 
#define TIM_CCMR2_OC4M_0   0x00001000U
 
#define TIM_CCMR2_OC4M_1   0x00002000U
 
#define TIM_CCMR2_OC4M_2   0x00004000U
 
#define TIM_CCMR2_OC4M_3   0x01000000U
 
#define TIM_CCMR2_OC4CE   0x8000U
 
#define TIM_CCMR2_IC3PSC   0x000CU
 
#define TIM_CCMR2_IC3PSC_0   0x0004U
 
#define TIM_CCMR2_IC3PSC_1   0x0008U
 
#define TIM_CCMR2_IC3F   0x00F0U
 
#define TIM_CCMR2_IC3F_0   0x0010U
 
#define TIM_CCMR2_IC3F_1   0x0020U
 
#define TIM_CCMR2_IC3F_2   0x0040U
 
#define TIM_CCMR2_IC3F_3   0x0080U
 
#define TIM_CCMR2_IC4PSC   0x0C00U
 
#define TIM_CCMR2_IC4PSC_0   0x0400U
 
#define TIM_CCMR2_IC4PSC_1   0x0800U
 
#define TIM_CCMR2_IC4F   0xF000U
 
#define TIM_CCMR2_IC4F_0   0x1000U
 
#define TIM_CCMR2_IC4F_1   0x2000U
 
#define TIM_CCMR2_IC4F_2   0x4000U
 
#define TIM_CCMR2_IC4F_3   0x8000U
 
#define TIM_CCER_CC1E   0x00000001U
 
#define TIM_CCER_CC1P   0x00000002U
 
#define TIM_CCER_CC1NE   0x00000004U
 
#define TIM_CCER_CC1NP   0x00000008U
 
#define TIM_CCER_CC2E   0x00000010U
 
#define TIM_CCER_CC2P   0x00000020U
 
#define TIM_CCER_CC2NE   0x00000040U
 
#define TIM_CCER_CC2NP   0x00000080U
 
#define TIM_CCER_CC3E   0x00000100U
 
#define TIM_CCER_CC3P   0x00000200U
 
#define TIM_CCER_CC3NE   0x00000400U
 
#define TIM_CCER_CC3NP   0x00000800U
 
#define TIM_CCER_CC4E   0x00001000U
 
#define TIM_CCER_CC4P   0x00002000U
 
#define TIM_CCER_CC4NP   0x00008000U
 
#define TIM_CCER_CC5E   0x00010000U
 
#define TIM_CCER_CC5P   0x00020000U
 
#define TIM_CCER_CC6E   0x00100000U
 
#define TIM_CCER_CC6P   0x00200000U
 
#define TIM_CNT_CNT   0xFFFFU
 
#define TIM_PSC_PSC   0xFFFFU
 
#define TIM_ARR_ARR   0xFFFFU
 
#define TIM_RCR_REP   ((uint8_t)0xFFU)
 
#define TIM_CCR1_CCR1   0xFFFFU
 
#define TIM_CCR2_CCR2   0xFFFFU
 
#define TIM_CCR3_CCR3   0xFFFFU
 
#define TIM_CCR4_CCR4   0xFFFFU
 
#define TIM_BDTR_DTG   0x000000FFU
 
#define TIM_BDTR_DTG_0   0x00000001U
 
#define TIM_BDTR_DTG_1   0x00000002U
 
#define TIM_BDTR_DTG_2   0x00000004U
 
#define TIM_BDTR_DTG_3   0x00000008U
 
#define TIM_BDTR_DTG_4   0x00000010U
 
#define TIM_BDTR_DTG_5   0x00000020U
 
#define TIM_BDTR_DTG_6   0x00000040U
 
#define TIM_BDTR_DTG_7   0x00000080U
 
#define TIM_BDTR_LOCK   0x00000300U
 
#define TIM_BDTR_LOCK_0   0x00000100U
 
#define TIM_BDTR_LOCK_1   0x00000200U
 
#define TIM_BDTR_OSSI   0x00000400U
 
#define TIM_BDTR_OSSR   0x00000800U
 
#define TIM_BDTR_BKE   0x00001000U
 
#define TIM_BDTR_BKP   0x00002000U
 
#define TIM_BDTR_AOE   0x00004000U
 
#define TIM_BDTR_MOE   0x00008000U
 
#define TIM_BDTR_BKF   0x000F0000U
 
#define TIM_BDTR_BK2F   0x00F00000U
 
#define TIM_BDTR_BK2E   0x01000000U
 
#define TIM_BDTR_BK2P   0x02000000U
 
#define TIM_DCR_DBA   0x001FU
 
#define TIM_DCR_DBA_0   0x0001U
 
#define TIM_DCR_DBA_1   0x0002U
 
#define TIM_DCR_DBA_2   0x0004U
 
#define TIM_DCR_DBA_3   0x0008U
 
#define TIM_DCR_DBA_4   0x0010U
 
#define TIM_DCR_DBL   0x1F00U
 
#define TIM_DCR_DBL_0   0x0100U
 
#define TIM_DCR_DBL_1   0x0200U
 
#define TIM_DCR_DBL_2   0x0400U
 
#define TIM_DCR_DBL_3   0x0800U
 
#define TIM_DCR_DBL_4   0x1000U
 
#define TIM_DMAR_DMAB   0xFFFFU
 
#define TIM_OR_TI4_RMP   0x00C0U
 
#define TIM_OR_TI4_RMP_0   0x0040U
 
#define TIM_OR_TI4_RMP_1   0x0080U
 
#define TIM_OR_ITR1_RMP   0x0C00U
 
#define TIM_OR_ITR1_RMP_0   0x0400U
 
#define TIM_OR_ITR1_RMP_1   0x0800U
 
#define TIM_CCMR3_OC5FE   0x00000004U
 
#define TIM_CCMR3_OC5PE   0x00000008U
 
#define TIM_CCMR3_OC5M   0x00010070U
 
#define TIM_CCMR3_OC5M_0   0x00000010U
 
#define TIM_CCMR3_OC5M_1   0x00000020U
 
#define TIM_CCMR3_OC5M_2   0x00000040U
 
#define TIM_CCMR3_OC5M_3   0x00010000U
 
#define TIM_CCMR3_OC5CE   0x00000080U
 
#define TIM_CCMR3_OC6FE   0x00000400U
 
#define TIM_CCMR3_OC6PE   0x00000800U
 
#define TIM_CCMR3_OC6M   0x01007000U
 
#define TIM_CCMR3_OC6M_0   0x00001000U
 
#define TIM_CCMR3_OC6M_1   0x00002000U
 
#define TIM_CCMR3_OC6M_2   0x00004000U
 
#define TIM_CCMR3_OC6M_3   0x01000000U
 
#define TIM_CCMR3_OC6CE   0x00008000U
 
#define TIM_CCR5_CCR5   0xFFFFFFFFU
 
#define TIM_CCR5_GC5C1   0x20000000U
 
#define TIM_CCR5_GC5C2   0x40000000U
 
#define TIM_CCR5_GC5C3   0x80000000U
 
#define TIM_CCR6_CCR6   ((uint16_t)0xFFFFU)
 
#define LPTIM_ISR_CMPM   0x00000001U
 
#define LPTIM_ISR_ARRM   0x00000002U
 
#define LPTIM_ISR_EXTTRIG   0x00000004U
 
#define LPTIM_ISR_CMPOK   0x00000008U
 
#define LPTIM_ISR_ARROK   0x00000010U
 
#define LPTIM_ISR_UP   0x00000020U
 
#define LPTIM_ISR_DOWN   0x00000040U
 
#define LPTIM_ICR_CMPMCF   0x00000001U
 
#define LPTIM_ICR_ARRMCF   0x00000002U
 
#define LPTIM_ICR_EXTTRIGCF   0x00000004U
 
#define LPTIM_ICR_CMPOKCF   0x00000008U
 
#define LPTIM_ICR_ARROKCF   0x00000010U
 
#define LPTIM_ICR_UPCF   0x00000020U
 
#define LPTIM_ICR_DOWNCF   0x00000040U
 
#define LPTIM_IER_CMPMIE   0x00000001U
 
#define LPTIM_IER_ARRMIE   0x00000002U
 
#define LPTIM_IER_EXTTRIGIE   0x00000004U
 
#define LPTIM_IER_CMPOKIE   0x00000008U
 
#define LPTIM_IER_ARROKIE   0x00000010U
 
#define LPTIM_IER_UPIE   0x00000020U
 
#define LPTIM_IER_DOWNIE   0x00000040U
 
#define LPTIM_CFGR_CKSEL   0x00000001U
 
#define LPTIM_CFGR_CKPOL   0x00000006U
 
#define LPTIM_CFGR_CKPOL_0   0x00000002U
 
#define LPTIM_CFGR_CKPOL_1   0x00000004U
 
#define LPTIM_CFGR_CKFLT   0x00000018U
 
#define LPTIM_CFGR_CKFLT_0   0x00000008U
 
#define LPTIM_CFGR_CKFLT_1   0x00000010U
 
#define LPTIM_CFGR_TRGFLT   0x000000C0U
 
#define LPTIM_CFGR_TRGFLT_0   0x00000040U
 
#define LPTIM_CFGR_TRGFLT_1   0x00000080U
 
#define LPTIM_CFGR_PRESC   0x00000E00U
 
#define LPTIM_CFGR_PRESC_0   0x00000200U
 
#define LPTIM_CFGR_PRESC_1   0x00000400U
 
#define LPTIM_CFGR_PRESC_2   0x00000800U
 
#define LPTIM_CFGR_TRIGSEL   0x0000E000U
 
#define LPTIM_CFGR_TRIGSEL_0   0x00002000U
 
#define LPTIM_CFGR_TRIGSEL_1   0x00004000U
 
#define LPTIM_CFGR_TRIGSEL_2   0x00008000U
 
#define LPTIM_CFGR_TRIGEN   0x00060000U
 
#define LPTIM_CFGR_TRIGEN_0   0x00020000U
 
#define LPTIM_CFGR_TRIGEN_1   0x00040000U
 
#define LPTIM_CFGR_TIMOUT   0x00080000U
 
#define LPTIM_CFGR_WAVE   0x00100000U
 
#define LPTIM_CFGR_WAVPOL   0x00200000U
 
#define LPTIM_CFGR_PRELOAD   0x00400000U
 
#define LPTIM_CFGR_COUNTMODE   0x00800000U
 
#define LPTIM_CFGR_ENC   0x01000000U
 
#define LPTIM_CR_ENABLE   0x00000001U
 
#define LPTIM_CR_SNGSTRT   0x00000002U
 
#define LPTIM_CR_CNTSTRT   0x00000004U
 
#define LPTIM_CMP_CMP   0x0000FFFFU
 
#define LPTIM_ARR_ARR   0x0000FFFFU
 
#define LPTIM_CNT_CNT   0x0000FFFFU
 
#define USART_CR1_UE   0x00000001U
 
#define USART_CR1_RE   0x00000004U
 
#define USART_CR1_TE   0x00000008U
 
#define USART_CR1_IDLEIE   0x00000010U
 
#define USART_CR1_RXNEIE   0x00000020U
 
#define USART_CR1_TCIE   0x00000040U
 
#define USART_CR1_TXEIE   0x00000080U
 
#define USART_CR1_PEIE   0x00000100U
 
#define USART_CR1_PS   0x00000200U
 
#define USART_CR1_PCE   0x00000400U
 
#define USART_CR1_WAKE   0x00000800U
 
#define USART_CR1_M   0x10001000U
 
#define USART_CR1_M_0   0x00001000U
 
#define USART_CR1_MME   0x00002000U
 
#define USART_CR1_CMIE   0x00004000U
 
#define USART_CR1_OVER8   0x00008000U
 
#define USART_CR1_DEDT   0x001F0000U
 
#define USART_CR1_DEDT_0   0x00010000U
 
#define USART_CR1_DEDT_1   0x00020000U
 
#define USART_CR1_DEDT_2   0x00040000U
 
#define USART_CR1_DEDT_3   0x00080000U
 
#define USART_CR1_DEDT_4   0x00100000U
 
#define USART_CR1_DEAT   0x03E00000U
 
#define USART_CR1_DEAT_0   0x00200000U
 
#define USART_CR1_DEAT_1   0x00400000U
 
#define USART_CR1_DEAT_2   0x00800000U
 
#define USART_CR1_DEAT_3   0x01000000U
 
#define USART_CR1_DEAT_4   0x02000000U
 
#define USART_CR1_RTOIE   0x04000000U
 
#define USART_CR1_EOBIE   0x08000000U
 
#define USART_CR1_M_1   0x10000000U
 
#define USART_CR2_ADDM7   0x00000010U
 
#define USART_CR2_LBDL   0x00000020U
 
#define USART_CR2_LBDIE   0x00000040U
 
#define USART_CR2_LBCL   0x00000100U
 
#define USART_CR2_CPHA   0x00000200U
 
#define USART_CR2_CPOL   0x00000400U
 
#define USART_CR2_CLKEN   0x00000800U
 
#define USART_CR2_STOP   0x00003000U
 
#define USART_CR2_STOP_0   0x00001000U
 
#define USART_CR2_STOP_1   0x00002000U
 
#define USART_CR2_LINEN   0x00004000U
 
#define USART_CR2_SWAP   0x00008000U
 
#define USART_CR2_RXINV   0x00010000U
 
#define USART_CR2_TXINV   0x00020000U
 
#define USART_CR2_DATAINV   0x00040000U
 
#define USART_CR2_MSBFIRST   0x00080000U
 
#define USART_CR2_ABREN   0x00100000U
 
#define USART_CR2_ABRMODE   0x00600000U
 
#define USART_CR2_ABRMODE_0   0x00200000U
 
#define USART_CR2_ABRMODE_1   0x00400000U
 
#define USART_CR2_RTOEN   0x00800000U
 
#define USART_CR2_ADD   0xFF000000U
 
#define USART_CR3_EIE   0x00000001U
 
#define USART_CR3_IREN   0x00000002U
 
#define USART_CR3_IRLP   0x00000004U
 
#define USART_CR3_HDSEL   0x00000008U
 
#define USART_CR3_NACK   0x00000010U
 
#define USART_CR3_SCEN   0x00000020U
 
#define USART_CR3_DMAR   0x00000040U
 
#define USART_CR3_DMAT   0x00000080U
 
#define USART_CR3_RTSE   0x00000100U
 
#define USART_CR3_CTSE   0x00000200U
 
#define USART_CR3_CTSIE   0x00000400U
 
#define USART_CR3_ONEBIT   0x00000800U
 
#define USART_CR3_OVRDIS   0x00001000U
 
#define USART_CR3_DDRE   0x00002000U
 
#define USART_CR3_DEM   0x00004000U
 
#define USART_CR3_DEP   0x00008000U
 
#define USART_CR3_SCARCNT   0x000E0000U
 
#define USART_CR3_SCARCNT_0   0x00020000U
 
#define USART_CR3_SCARCNT_1   0x00040000U
 
#define USART_CR3_SCARCNT_2   0x00080000U
 
#define USART_BRR_DIV_FRACTION   0x000FU
 
#define USART_BRR_DIV_MANTISSA   0xFFF0U
 
#define USART_GTPR_PSC   0x00FFU
 
#define USART_GTPR_GT   0xFF00U
 
#define USART_RTOR_RTO   0x00FFFFFFU
 
#define USART_RTOR_BLEN   0xFF000000U
 
#define USART_RQR_ABRRQ   0x0001U
 
#define USART_RQR_SBKRQ   0x0002U
 
#define USART_RQR_MMRQ   0x0004U
 
#define USART_RQR_RXFRQ   0x0008U
 
#define USART_RQR_TXFRQ   0x0010U
 
#define USART_ISR_PE   0x00000001U
 
#define USART_ISR_FE   0x00000002U
 
#define USART_ISR_NE   0x00000004U
 
#define USART_ISR_ORE   0x00000008U
 
#define USART_ISR_IDLE   0x00000010U
 
#define USART_ISR_RXNE   0x00000020U
 
#define USART_ISR_TC   0x00000040U
 
#define USART_ISR_TXE   0x00000080U
 
#define USART_ISR_LBDF   0x00000100U
 
#define USART_ISR_CTSIF   0x00000200U
 
#define USART_ISR_CTS   0x00000400U
 
#define USART_ISR_RTOF   0x00000800U
 
#define USART_ISR_EOBF   0x00001000U
 
#define USART_ISR_ABRE   0x00004000U
 
#define USART_ISR_ABRF   0x00008000U
 
#define USART_ISR_BUSY   0x00010000U
 
#define USART_ISR_CMF   0x00020000U
 
#define USART_ISR_SBKF   0x00040000U
 
#define USART_ISR_RWU   0x00080000U
 
#define USART_ISR_WUF   0x00100000U
 
#define USART_ISR_TEACK   0x00200000U
 
#define USART_ISR_REACK   0x00400000U
 
#define USART_ISR_LBD   USART_ISR_LBDF
 
#define USART_ICR_PECF   0x00000001U
 
#define USART_ICR_FECF   0x00000002U
 
#define USART_ICR_NCF   0x00000004U
 
#define USART_ICR_ORECF   0x00000008U
 
#define USART_ICR_IDLECF   0x00000010U
 
#define USART_ICR_TCCF   0x00000040U
 
#define USART_ICR_LBDCF   0x00000100U
 
#define USART_ICR_CTSCF   0x00000200U
 
#define USART_ICR_RTOCF   0x00000800U
 
#define USART_ICR_EOBCF   0x00001000U
 
#define USART_ICR_CMCF   0x00020000U
 
#define USART_ICR_WUCF   0x00100000U
 
#define USART_RDR_RDR   0x01FFU
 
#define USART_TDR_TDR   0x01FFU
 
#define WWDG_CR_T   0x7FU
 
#define WWDG_CR_T_0   0x01U
 
#define WWDG_CR_T_1   0x02U
 
#define WWDG_CR_T_2   0x04U
 
#define WWDG_CR_T_3   0x08U
 
#define WWDG_CR_T_4   0x10U
 
#define WWDG_CR_T_5   0x20U
 
#define WWDG_CR_T_6   0x40U
 
#define WWDG_CR_T0   WWDG_CR_T_0
 
#define WWDG_CR_T1   WWDG_CR_T_1
 
#define WWDG_CR_T2   WWDG_CR_T_2
 
#define WWDG_CR_T3   WWDG_CR_T_3
 
#define WWDG_CR_T4   WWDG_CR_T_4
 
#define WWDG_CR_T5   WWDG_CR_T_5
 
#define WWDG_CR_T6   WWDG_CR_T_6
 
#define WWDG_CR_WDGA   0x80U
 
#define WWDG_CFR_W   0x007FU
 
#define WWDG_CFR_W_0   0x0001U
 
#define WWDG_CFR_W_1   0x0002U
 
#define WWDG_CFR_W_2   0x0004U
 
#define WWDG_CFR_W_3   0x0008U
 
#define WWDG_CFR_W_4   0x0010U
 
#define WWDG_CFR_W_5   0x0020U
 
#define WWDG_CFR_W_6   0x0040U
 
#define WWDG_CFR_W0   WWDG_CFR_W_0
 
#define WWDG_CFR_W1   WWDG_CFR_W_1
 
#define WWDG_CFR_W2   WWDG_CFR_W_2
 
#define WWDG_CFR_W3   WWDG_CFR_W_3
 
#define WWDG_CFR_W4   WWDG_CFR_W_4
 
#define WWDG_CFR_W5   WWDG_CFR_W_5
 
#define WWDG_CFR_W6   WWDG_CFR_W_6
 
#define WWDG_CFR_WDGTB   0x0180U
 
#define WWDG_CFR_WDGTB_0   0x0080U
 
#define WWDG_CFR_WDGTB_1   0x0100U
 
#define WWDG_CFR_WDGTB0   WWDG_CFR_WDGTB_0
 
#define WWDG_CFR_WDGTB1   WWDG_CFR_WDGTB_1
 
#define WWDG_CFR_EWI   0x0200U
 
#define WWDG_SR_EWIF   0x01U
 
#define DBGMCU_IDCODE_DEV_ID   0x00000FFFU
 
#define DBGMCU_IDCODE_REV_ID   0xFFFF0000U
 
#define DBGMCU_CR_DBG_SLEEP   0x00000001U
 
#define DBGMCU_CR_DBG_STOP   0x00000002U
 
#define DBGMCU_CR_DBG_STANDBY   0x00000004U
 
#define DBGMCU_CR_TRACE_IOEN   0x00000020U
 
#define DBGMCU_CR_TRACE_MODE   0x000000C0U
 
#define DBGMCU_CR_TRACE_MODE_0   0x00000040U
 
#define DBGMCU_CR_TRACE_MODE_1   0x00000080U
 
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP   0x00000001U
 
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP   0x00000002U
 
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP   0x00000004U
 
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP   0x00000008U
 
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP   0x00000010U
 
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP   0x00000020U
 
#define DBGMCU_APB1_FZ_DBG_TIM12_STOP   0x00000040U
 
#define DBGMCU_APB1_FZ_DBG_TIM13_STOP   0x00000080U
 
#define DBGMCU_APB1_FZ_DBG_TIM14_STOP   0x00000100U
 
#define DBGMCU_APB1_FZ_DBG_RTC_STOP   0x00000400U
 
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP   0x00000800U
 
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP   0x00001000U
 
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
 
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
 
#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
 
#define DBGMCU_APB1_FZ_DBG_CAN1_STOP   0x02000000U
 
#define DBGMCU_APB1_FZ_DBG_CAN2_STOP   0x04000000U
 
#define DBGMCU_APB2_FZ_DBG_TIM1_STOP   0x00000001U
 
#define DBGMCU_APB2_FZ_DBG_TIM8_STOP   0x00000002U
 
#define DBGMCU_APB2_FZ_DBG_TIM9_STOP   0x00010000U
 
#define DBGMCU_APB2_FZ_DBG_TIM10_STOP   0x00020000U
 
#define DBGMCU_APB2_FZ_DBG_TIM11_STOP   0x00040000U
 
#define ETH_MACCR_WD   0x00800000U /* Watchdog disable */
 
#define ETH_MACCR_JD   0x00400000U /* Jabber disable */
 
#define ETH_MACCR_IFG   0x000E0000U /* Inter-frame gap */
 
#define ETH_MACCR_IFG_96Bit   0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
 
#define ETH_MACCR_IFG_88Bit   0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
 
#define ETH_MACCR_IFG_80Bit   0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
 
#define ETH_MACCR_IFG_72Bit   0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
 
#define ETH_MACCR_IFG_64Bit   0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
 
#define ETH_MACCR_IFG_56Bit   0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
 
#define ETH_MACCR_IFG_48Bit   0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
 
#define ETH_MACCR_IFG_40Bit   0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
 
#define ETH_MACCR_CSD   0x00010000U /* Carrier sense disable (during transmission) */
 
#define ETH_MACCR_FES   0x00004000U /* Fast ethernet speed */
 
#define ETH_MACCR_ROD   0x00002000U /* Receive own disable */
 
#define ETH_MACCR_LM   0x00001000U /* loopback mode */
 
#define ETH_MACCR_DM   0x00000800U /* Duplex mode */
 
#define ETH_MACCR_IPCO   0x00000400U /* IP Checksum offload */
 
#define ETH_MACCR_RD   0x00000200U /* Retry disable */
 
#define ETH_MACCR_APCS   0x00000080U /* Automatic Pad/CRC stripping */
 
#define ETH_MACCR_BL
 
#define ETH_MACCR_BL_10   0x00000000U /* k = min (n, 10) */
 
#define ETH_MACCR_BL_8   0x00000020U /* k = min (n, 8) */
 
#define ETH_MACCR_BL_4   0x00000040U /* k = min (n, 4) */
 
#define ETH_MACCR_BL_1   0x00000060U /* k = min (n, 1) */
 
#define ETH_MACCR_DC   0x00000010U /* Defferal check */
 
#define ETH_MACCR_TE   0x00000008U /* Transmitter enable */
 
#define ETH_MACCR_RE   0x00000004U /* Receiver enable */
 
#define ETH_MACFFR_RA   0x80000000U /* Receive all */
 
#define ETH_MACFFR_HPF   0x00000400U /* Hash or perfect filter */
 
#define ETH_MACFFR_SAF   0x00000200U /* Source address filter enable */
 
#define ETH_MACFFR_SAIF   0x00000100U /* SA inverse filtering */
 
#define ETH_MACFFR_PCF   0x000000C0U /* Pass control frames: 3 cases */
 
#define ETH_MACFFR_PCF_BlockAll   0x00000040U /* MAC filters all control frames from reaching the application */
 
#define ETH_MACFFR_PCF_ForwardAll   0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
 
#define ETH_MACFFR_PCF_ForwardPassedAddrFilter   0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
 
#define ETH_MACFFR_BFD   0x00000020U /* Broadcast frame disable */
 
#define ETH_MACFFR_PAM   0x00000010U /* Pass all mutlicast */
 
#define ETH_MACFFR_DAIF   0x00000008U /* DA Inverse filtering */
 
#define ETH_MACFFR_HM   0x00000004U /* Hash multicast */
 
#define ETH_MACFFR_HU   0x00000002U /* Hash unicast */
 
#define ETH_MACFFR_PM   0x00000001U /* Promiscuous mode */
 
#define ETH_MACHTHR_HTH   0xFFFFFFFFU /* Hash table high */
 
#define ETH_MACHTLR_HTL   0xFFFFFFFFU /* Hash table low */
 
#define ETH_MACMIIAR_PA   0x0000F800U /* Physical layer address */
 
#define ETH_MACMIIAR_MR   0x000007C0U /* MII register in the selected PHY */
 
#define ETH_MACMIIAR_CR   0x0000001CU /* CR clock range: 6 cases */
 
#define ETH_MACMIIAR_CR_Div42   0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
 
#define ETH_MACMIIAR_CR_Div62   0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
 
#define ETH_MACMIIAR_CR_Div16   0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
 
#define ETH_MACMIIAR_CR_Div26   0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
 
#define ETH_MACMIIAR_CR_Div102   0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
 
#define ETH_MACMIIAR_MW   0x00000002U /* MII write */
 
#define ETH_MACMIIAR_MB   0x00000001U /* MII busy */
 
#define ETH_MACMIIDR_MD   0x0000FFFFU /* MII data: read/write data from/to PHY */
 
#define ETH_MACFCR_PT   0xFFFF0000U /* Pause time */
 
#define ETH_MACFCR_ZQPD   0x00000080U /* Zero-quanta pause disable */
 
#define ETH_MACFCR_PLT   0x00000030U /* Pause low threshold: 4 cases */
 
#define ETH_MACFCR_PLT_Minus4   0x00000000U /* Pause time minus 4 slot times */
 
#define ETH_MACFCR_PLT_Minus28   0x00000010U /* Pause time minus 28 slot times */
 
#define ETH_MACFCR_PLT_Minus144   0x00000020U /* Pause time minus 144 slot times */
 
#define ETH_MACFCR_PLT_Minus256   0x00000030U /* Pause time minus 256 slot times */
 
#define ETH_MACFCR_UPFD   0x00000008U /* Unicast pause frame detect */
 
#define ETH_MACFCR_RFCE   0x00000004U /* Receive flow control enable */
 
#define ETH_MACFCR_TFCE   0x00000002U /* Transmit flow control enable */
 
#define ETH_MACFCR_FCBBPA   0x00000001U /* Flow control busy/backpressure activate */
 
#define ETH_MACVLANTR_VLANTC   0x00010000U /* 12-bit VLAN tag comparison */
 
#define ETH_MACVLANTR_VLANTI   0x0000FFFFU /* VLAN tag identifier (for receive frames) */
 
#define ETH_MACRWUFFR_D   0xFFFFFFFFU /* Wake-up frame filter register data */
 
#define ETH_MACPMTCSR_WFFRPR   0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
 
#define ETH_MACPMTCSR_GU   0x00000200U /* Global Unicast */
 
#define ETH_MACPMTCSR_WFR   0x00000040U /* Wake-Up Frame Received */
 
#define ETH_MACPMTCSR_MPR   0x00000020U /* Magic Packet Received */
 
#define ETH_MACPMTCSR_WFE   0x00000004U /* Wake-Up Frame Enable */
 
#define ETH_MACPMTCSR_MPE   0x00000002U /* Magic Packet Enable */
 
#define ETH_MACPMTCSR_PD   0x00000001U /* Power Down */
 
#define ETH_MACSR_TSTS   0x00000200U /* Time stamp trigger status */
 
#define ETH_MACSR_MMCTS   0x00000040U /* MMC transmit status */
 
#define ETH_MACSR_MMMCRS   0x00000020U /* MMC receive status */
 
#define ETH_MACSR_MMCS   0x00000010U /* MMC status */
 
#define ETH_MACSR_PMTS   0x00000008U /* PMT status */
 
#define ETH_MACIMR_TSTIM   0x00000200U /* Time stamp trigger interrupt mask */
 
#define ETH_MACIMR_PMTIM   0x00000008U /* PMT interrupt mask */
 
#define ETH_MACA0HR_MACA0H   0x0000FFFFU /* MAC address0 high */
 
#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU /* MAC address0 low */
 
#define ETH_MACA1HR_AE   0x80000000U /* Address enable */
 
#define ETH_MACA1HR_SA   0x40000000U /* Source address */
 
#define ETH_MACA1HR_MBC   0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
 
#define ETH_MACA1HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
 
#define ETH_MACA1HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
 
#define ETH_MACA1HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
 
#define ETH_MACA1HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
 
#define ETH_MACA1HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
 
#define ETH_MACA1HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [7:0] */
 
#define ETH_MACA1HR_MACA1H   0x0000FFFFU /* MAC address1 high */
 
#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU /* MAC address1 low */
 
#define ETH_MACA2HR_AE   0x80000000U /* Address enable */
 
#define ETH_MACA2HR_SA   0x40000000U /* Source address */
 
#define ETH_MACA2HR_MBC   0x3F000000U /* Mask byte control */
 
#define ETH_MACA2HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
 
#define ETH_MACA2HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
 
#define ETH_MACA2HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
 
#define ETH_MACA2HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
 
#define ETH_MACA2HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
 
#define ETH_MACA2HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [70] */
 
#define ETH_MACA2HR_MACA2H   0x0000FFFFU /* MAC address1 high */
 
#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU /* MAC address2 low */
 
#define ETH_MACA3HR_AE   0x80000000U /* Address enable */
 
#define ETH_MACA3HR_SA   0x40000000U /* Source address */
 
#define ETH_MACA3HR_MBC   0x3F000000U /* Mask byte control */
 
#define ETH_MACA3HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
 
#define ETH_MACA3HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
 
#define ETH_MACA3HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
 
#define ETH_MACA3HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
 
#define ETH_MACA3HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
 
#define ETH_MACA3HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [70] */
 
#define ETH_MACA3HR_MACA3H   0x0000FFFFU /* MAC address3 high */
 
#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU /* MAC address3 low */
 
#define ETH_MMCCR_MCFHP   0x00000020U /* MMC counter Full-Half preset */
 
#define ETH_MMCCR_MCP   0x00000010U /* MMC counter preset */
 
#define ETH_MMCCR_MCF   0x00000008U /* MMC Counter Freeze */
 
#define ETH_MMCCR_ROR   0x00000004U /* Reset on Read */
 
#define ETH_MMCCR_CSR   0x00000002U /* Counter Stop Rollover */
 
#define ETH_MMCCR_CR   0x00000001U /* Counters Reset */
 
#define ETH_MMCRIR_RGUFS   0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
 
#define ETH_MMCRIR_RFAES   0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
 
#define ETH_MMCRIR_RFCES   0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
 
#define ETH_MMCTIR_TGFS   0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
 
#define ETH_MMCTIR_TGFMSCS   0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
 
#define ETH_MMCTIR_TGFSCS   0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
 
#define ETH_MMCRIMR_RGUFM   0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
 
#define ETH_MMCRIMR_RFAEM   0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
 
#define ETH_MMCRIMR_RFCEM   0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
 
#define ETH_MMCTIMR_TGFM   0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
 
#define ETH_MMCTIMR_TGFMSCM   0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
 
#define ETH_MMCTIMR_TGFSCM   0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
 
#define ETH_MMCTGFSCCR_TGFSCC   0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
 
#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
 
#define ETH_MMCTGFCR_TGFC   0xFFFFFFFFU /* Number of good frames transmitted. */
 
#define ETH_MMCRFCECR_RFCEC   0xFFFFFFFFU /* Number of frames received with CRC error. */
 
#define ETH_MMCRFAECR_RFAEC   0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
 
#define ETH_MMCRGUFCR_RGUFC   0xFFFFFFFFU /* Number of good unicast frames received. */
 
#define ETH_PTPTSCR_TSCNT   0x00030000U /* Time stamp clock node type */
 
#define ETH_PTPTSSR_TSSMRME   0x00008000U /* Time stamp snapshot for message relevant to master enable */
 
#define ETH_PTPTSSR_TSSEME   0x00004000U /* Time stamp snapshot for event message enable */
 
#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U /* Time stamp snapshot for IPv4 frames enable */
 
#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U /* Time stamp snapshot for IPv6 frames enable */
 
#define ETH_PTPTSSR_TSSPTPOEFE   0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
 
#define ETH_PTPTSSR_TSPTPPSV2E   0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
 
#define ETH_PTPTSSR_TSSSR   0x00000200U /* Time stamp Sub-seconds rollover */
 
#define ETH_PTPTSSR_TSSARFE   0x00000100U /* Time stamp snapshot for all received frames enable */
 
#define ETH_PTPTSCR_TSARU   0x00000020U /* Addend register update */
 
#define ETH_PTPTSCR_TSITE   0x00000010U /* Time stamp interrupt trigger enable */
 
#define ETH_PTPTSCR_TSSTU   0x00000008U /* Time stamp update */
 
#define ETH_PTPTSCR_TSSTI   0x00000004U /* Time stamp initialize */
 
#define ETH_PTPTSCR_TSFCU   0x00000002U /* Time stamp fine or coarse update */
 
#define ETH_PTPTSCR_TSE   0x00000001U /* Time stamp enable */
 
#define ETH_PTPSSIR_STSSI   0x000000FFU /* System time Sub-second increment value */
 
#define ETH_PTPTSHR_STS   0xFFFFFFFFU /* System Time second */
 
#define ETH_PTPTSLR_STPNS   0x80000000U /* System Time Positive or negative time */
 
#define ETH_PTPTSLR_STSS   0x7FFFFFFFU /* System Time sub-seconds */
 
#define ETH_PTPTSHUR_TSUS   0xFFFFFFFFU /* Time stamp update seconds */
 
#define ETH_PTPTSLUR_TSUPNS   0x80000000U /* Time stamp update Positive or negative time */
 
#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU /* Time stamp update sub-seconds */
 
#define ETH_PTPTSAR_TSA   0xFFFFFFFFU /* Time stamp addend */
 
#define ETH_PTPTTHR_TTSH   0xFFFFFFFFU /* Target time stamp high */
 
#define ETH_PTPTTLR_TTSL   0xFFFFFFFFU /* Target time stamp low */
 
#define ETH_PTPTSSR_TSTTR   0x00000020U /* Time stamp target time reached */
 
#define ETH_PTPTSSR_TSSO   0x00000010U /* Time stamp seconds overflow */
 
#define ETH_DMABMR_AAB   0x02000000U /* Address-Aligned beats */
 
#define ETH_DMABMR_FPM   0x01000000U /* 4xPBL mode */
 
#define ETH_DMABMR_USP   0x00800000U /* Use separate PBL */
 
#define ETH_DMABMR_RDP   0x007E0000U /* RxDMA PBL */
 
#define ETH_DMABMR_RDP_1Beat   0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
 
#define ETH_DMABMR_RDP_2Beat   0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
 
#define ETH_DMABMR_RDP_4Beat   0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
 
#define ETH_DMABMR_RDP_8Beat   0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
 
#define ETH_DMABMR_RDP_16Beat   0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
 
#define ETH_DMABMR_RDP_32Beat   0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
 
#define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
 
#define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
 
#define ETH_DMABMR_RDP_4xPBL_16Beat   0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
 
#define ETH_DMABMR_RDP_4xPBL_32Beat   0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
 
#define ETH_DMABMR_RDP_4xPBL_64Beat   0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
 
#define ETH_DMABMR_RDP_4xPBL_128Beat   0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
 
#define ETH_DMABMR_FB   0x00010000U /* Fixed Burst */
 
#define ETH_DMABMR_RTPR   0x0000C000U /* Rx Tx priority ratio */
 
#define ETH_DMABMR_RTPR_1_1   0x00000000U /* Rx Tx priority ratio */
 
#define ETH_DMABMR_RTPR_2_1   0x00004000U /* Rx Tx priority ratio */
 
#define ETH_DMABMR_RTPR_3_1   0x00008000U /* Rx Tx priority ratio */
 
#define ETH_DMABMR_RTPR_4_1   0x0000C000U /* Rx Tx priority ratio */
 
#define ETH_DMABMR_PBL   0x00003F00U /* Programmable burst length */
 
#define ETH_DMABMR_PBL_1Beat   0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
 
#define ETH_DMABMR_PBL_2Beat   0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
 
#define ETH_DMABMR_PBL_4Beat   0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
 
#define ETH_DMABMR_PBL_8Beat   0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
 
#define ETH_DMABMR_PBL_16Beat   0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
 
#define ETH_DMABMR_PBL_32Beat   0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
 
#define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
 
#define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
 
#define ETH_DMABMR_PBL_4xPBL_16Beat   0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
 
#define ETH_DMABMR_PBL_4xPBL_32Beat   0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
 
#define ETH_DMABMR_PBL_4xPBL_64Beat   0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
 
#define ETH_DMABMR_PBL_4xPBL_128Beat   0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
 
#define ETH_DMABMR_EDE   0x00000080U /* Enhanced Descriptor Enable */
 
#define ETH_DMABMR_DSL   0x0000007CU /* Descriptor Skip Length */
 
#define ETH_DMABMR_DA   0x00000002U /* DMA arbitration scheme */
 
#define ETH_DMABMR_SR   0x00000001U /* Software reset */
 
#define ETH_DMATPDR_TPD   0xFFFFFFFFU /* Transmit poll demand */
 
#define ETH_DMARPDR_RPD   0xFFFFFFFFU /* Receive poll demand */
 
#define ETH_DMARDLAR_SRL   0xFFFFFFFFU /* Start of receive list */
 
#define ETH_DMATDLAR_STL   0xFFFFFFFFU /* Start of transmit list */
 
#define ETH_DMASR_TSTS   0x20000000U /* Time-stamp trigger status */
 
#define ETH_DMASR_PMTS   0x10000000U /* PMT status */
 
#define ETH_DMASR_MMCS   0x08000000U /* MMC status */
 
#define ETH_DMASR_EBS   0x03800000U /* Error bits status */
 
#define ETH_DMASR_EBS_DescAccess   0x02000000U /* Error bits 0-data buffer, 1-desc. access */
 
#define ETH_DMASR_EBS_ReadTransf   0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
 
#define ETH_DMASR_EBS_DataTransfTx   0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
 
#define ETH_DMASR_TPS   0x00700000U /* Transmit process state */
 
#define ETH_DMASR_TPS_Stopped   0x00000000U /* Stopped - Reset or Stop Tx Command issued */
 
#define ETH_DMASR_TPS_Fetching   0x00100000U /* Running - fetching the Tx descriptor */
 
#define ETH_DMASR_TPS_Waiting   0x00200000U /* Running - waiting for status */
 
#define ETH_DMASR_TPS_Reading   0x00300000U /* Running - reading the data from host memory */
 
#define ETH_DMASR_TPS_Suspended   0x00600000U /* Suspended - Tx Descriptor unavailabe */
 
#define ETH_DMASR_TPS_Closing   0x00700000U /* Running - closing Rx descriptor */
 
#define ETH_DMASR_RPS   0x000E0000U /* Receive process state */
 
#define ETH_DMASR_RPS_Stopped   0x00000000U /* Stopped - Reset or Stop Rx Command issued */
 
#define ETH_DMASR_RPS_Fetching   0x00020000U /* Running - fetching the Rx descriptor */
 
#define ETH_DMASR_RPS_Waiting   0x00060000U /* Running - waiting for packet */
 
#define ETH_DMASR_RPS_Suspended   0x00080000U /* Suspended - Rx Descriptor unavailable */
 
#define ETH_DMASR_RPS_Closing   0x000A0000U /* Running - closing descriptor */
 
#define ETH_DMASR_RPS_Queuing   0x000E0000U /* Running - queuing the recieve frame into host memory */
 
#define ETH_DMASR_NIS   0x00010000U /* Normal interrupt summary */
 
#define ETH_DMASR_AIS   0x00008000U /* Abnormal interrupt summary */
 
#define ETH_DMASR_ERS   0x00004000U /* Early receive status */
 
#define ETH_DMASR_FBES   0x00002000U /* Fatal bus error status */
 
#define ETH_DMASR_ETS   0x00000400U /* Early transmit status */
 
#define ETH_DMASR_RWTS   0x00000200U /* Receive watchdog timeout status */
 
#define ETH_DMASR_RPSS   0x00000100U /* Receive process stopped status */
 
#define ETH_DMASR_RBUS   0x00000080U /* Receive buffer unavailable status */
 
#define ETH_DMASR_RS   0x00000040U /* Receive status */
 
#define ETH_DMASR_TUS   0x00000020U /* Transmit underflow status */
 
#define ETH_DMASR_ROS   0x00000010U /* Receive overflow status */
 
#define ETH_DMASR_TJTS   0x00000008U /* Transmit jabber timeout status */
 
#define ETH_DMASR_TBUS   0x00000004U /* Transmit buffer unavailable status */
 
#define ETH_DMASR_TPSS   0x00000002U /* Transmit process stopped status */
 
#define ETH_DMASR_TS   0x00000001U /* Transmit status */
 
#define ETH_DMAOMR_DTCEFD   0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
 
#define ETH_DMAOMR_RSF   0x02000000U /* Receive store and forward */
 
#define ETH_DMAOMR_DFRF   0x01000000U /* Disable flushing of received frames */
 
#define ETH_DMAOMR_TSF   0x00200000U /* Transmit store and forward */
 
#define ETH_DMAOMR_FTF   0x00100000U /* Flush transmit FIFO */
 
#define ETH_DMAOMR_TTC   0x0001C000U /* Transmit threshold control */
 
#define ETH_DMAOMR_TTC_64Bytes   0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
 
#define ETH_DMAOMR_TTC_128Bytes   0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
 
#define ETH_DMAOMR_TTC_192Bytes   0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
 
#define ETH_DMAOMR_TTC_256Bytes   0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
 
#define ETH_DMAOMR_TTC_40Bytes   0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
 
#define ETH_DMAOMR_TTC_32Bytes   0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
 
#define ETH_DMAOMR_TTC_24Bytes   0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
 
#define ETH_DMAOMR_TTC_16Bytes   0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
 
#define ETH_DMAOMR_ST   0x00002000U /* Start/stop transmission command */
 
#define ETH_DMAOMR_FEF   0x00000080U /* Forward error frames */
 
#define ETH_DMAOMR_FUGF   0x00000040U /* Forward undersized good frames */
 
#define ETH_DMAOMR_RTC   0x00000018U /* receive threshold control */
 
#define ETH_DMAOMR_RTC_64Bytes   0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
 
#define ETH_DMAOMR_RTC_32Bytes   0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
 
#define ETH_DMAOMR_RTC_96Bytes   0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
 
#define ETH_DMAOMR_RTC_128Bytes   0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
 
#define ETH_DMAOMR_OSF   0x00000004U /* operate on second frame */
 
#define ETH_DMAOMR_SR   0x00000002U /* Start/stop receive */
 
#define ETH_DMAIER_NISE   0x00010000U /* Normal interrupt summary enable */
 
#define ETH_DMAIER_AISE   0x00008000U /* Abnormal interrupt summary enable */
 
#define ETH_DMAIER_ERIE   0x00004000U /* Early receive interrupt enable */
 
#define ETH_DMAIER_FBEIE   0x00002000U /* Fatal bus error interrupt enable */
 
#define ETH_DMAIER_ETIE   0x00000400U /* Early transmit interrupt enable */
 
#define ETH_DMAIER_RWTIE   0x00000200U /* Receive watchdog timeout interrupt enable */
 
#define ETH_DMAIER_RPSIE   0x00000100U /* Receive process stopped interrupt enable */
 
#define ETH_DMAIER_RBUIE   0x00000080U /* Receive buffer unavailable interrupt enable */
 
#define ETH_DMAIER_RIE   0x00000040U /* Receive interrupt enable */
 
#define ETH_DMAIER_TUIE   0x00000020U /* Transmit Underflow interrupt enable */
 
#define ETH_DMAIER_ROIE   0x00000010U /* Receive Overflow interrupt enable */
 
#define ETH_DMAIER_TJTIE   0x00000008U /* Transmit jabber timeout interrupt enable */
 
#define ETH_DMAIER_TBUIE   0x00000004U /* Transmit buffer unavailable interrupt enable */
 
#define ETH_DMAIER_TPSIE   0x00000002U /* Transmit process stopped interrupt enable */
 
#define ETH_DMAIER_TIE   0x00000001U /* Transmit interrupt enable */
 
#define ETH_DMAMFBOCR_OFOC   0x10000000U /* Overflow bit for FIFO overflow counter */
 
#define ETH_DMAMFBOCR_MFA   0x0FFE0000U /* Number of frames missed by the application */
 
#define ETH_DMAMFBOCR_OMFC   0x00010000U /* Overflow bit for missed frame counter */
 
#define ETH_DMAMFBOCR_MFC   0x0000FFFFU /* Number of frames missed by the controller */
 
#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU /* Host transmit descriptor address pointer */
 
#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU /* Host receive descriptor address pointer */
 
#define ETH_DMACHTBAR_HTBAP   0xFFFFFFFFU /* Host transmit buffer address pointer */
 
#define ETH_DMACHRBAR_HRBAP   0xFFFFFFFFU /* Host receive buffer address pointer */
 
#define USB_OTG_GOTGCTL_SRQSCS   0x00000001U
 
#define USB_OTG_GOTGCTL_SRQ   0x00000002U
 
#define USB_OTG_GOTGCTL_VBVALOEN   0x00000004U
 
#define USB_OTG_GOTGCTL_VBVALOVAL   0x00000008U
 
#define USB_OTG_GOTGCTL_AVALOEN   0x00000010U
 
#define USB_OTG_GOTGCTL_AVALOVAL   0x00000020U
 
#define USB_OTG_GOTGCTL_BVALOEN   0x00000040U
 
#define USB_OTG_GOTGCTL_BVALOVAL   0x00000080U
 
#define USB_OTG_GOTGCTL_HNGSCS   0x00000100U
 
#define USB_OTG_GOTGCTL_HNPRQ   0x00000200U
 
#define USB_OTG_GOTGCTL_HSHNPEN   0x00000400U
 
#define USB_OTG_GOTGCTL_DHNPEN   0x00000800U
 
#define USB_OTG_GOTGCTL_EHEN   0x00001000U
 
#define USB_OTG_GOTGCTL_CIDSTS   0x00010000U
 
#define USB_OTG_GOTGCTL_DBCT   0x00020000U
 
#define USB_OTG_GOTGCTL_ASVLD   0x00040000U
 
#define USB_OTG_GOTGCTL_BSESVLD   0x00080000U
 
#define USB_OTG_GOTGCTL_OTGVER   0x00100000U
 
#define USB_OTG_HCFG_FSLSPCS   0x00000003U
 
#define USB_OTG_HCFG_FSLSPCS_0   0x00000001U
 
#define USB_OTG_HCFG_FSLSPCS_1   0x00000002U
 
#define USB_OTG_HCFG_FSLSS   0x00000004U
 
#define USB_OTG_DCFG_DSPD   0x00000003U
 
#define USB_OTG_DCFG_DSPD_0   0x00000001U
 
#define USB_OTG_DCFG_DSPD_1   0x00000002U
 
#define USB_OTG_DCFG_NZLSOHSK   0x00000004U
 
#define USB_OTG_DCFG_DAD   0x000007F0U
 
#define USB_OTG_DCFG_DAD_0   0x00000010U
 
#define USB_OTG_DCFG_DAD_1   0x00000020U
 
#define USB_OTG_DCFG_DAD_2   0x00000040U
 
#define USB_OTG_DCFG_DAD_3   0x00000080U
 
#define USB_OTG_DCFG_DAD_4   0x00000100U
 
#define USB_OTG_DCFG_DAD_5   0x00000200U
 
#define USB_OTG_DCFG_DAD_6   0x00000400U
 
#define USB_OTG_DCFG_PFIVL   0x00001800U
 
#define USB_OTG_DCFG_PFIVL_0   0x00000800U
 
#define USB_OTG_DCFG_PFIVL_1   0x00001000U
 
#define USB_OTG_DCFG_PERSCHIVL   0x03000000U
 
#define USB_OTG_DCFG_PERSCHIVL_0   0x01000000U
 
#define USB_OTG_DCFG_PERSCHIVL_1   0x02000000U
 
#define USB_OTG_PCGCR_STPPCLK   0x00000001U
 
#define USB_OTG_PCGCR_GATEHCLK   0x00000002U
 
#define USB_OTG_PCGCR_PHYSUSP   0x00000010U
 
#define USB_OTG_GOTGINT_SEDET   0x00000004U
 
#define USB_OTG_GOTGINT_SRSSCHG   0x00000100U
 
#define USB_OTG_GOTGINT_HNSSCHG   0x00000200U
 
#define USB_OTG_GOTGINT_HNGDET   0x00020000U
 
#define USB_OTG_GOTGINT_ADTOCHG   0x00040000U
 
#define USB_OTG_GOTGINT_DBCDNE   0x00080000U
 
#define USB_OTG_GOTGINT_IDCHNG   0x00100000U
 
#define USB_OTG_DCTL_RWUSIG   0x00000001U
 
#define USB_OTG_DCTL_SDIS   0x00000002U
 
#define USB_OTG_DCTL_GINSTS   0x00000004U
 
#define USB_OTG_DCTL_GONSTS   0x00000008U
 
#define USB_OTG_DCTL_TCTL   0x00000070U
 
#define USB_OTG_DCTL_TCTL_0   0x00000010U
 
#define USB_OTG_DCTL_TCTL_1   0x00000020U
 
#define USB_OTG_DCTL_TCTL_2   0x00000040U
 
#define USB_OTG_DCTL_SGINAK   0x00000080U
 
#define USB_OTG_DCTL_CGINAK   0x00000100U
 
#define USB_OTG_DCTL_SGONAK   0x00000200U
 
#define USB_OTG_DCTL_CGONAK   0x00000400U
 
#define USB_OTG_DCTL_POPRGDNE   0x00000800U
 
#define USB_OTG_HFIR_FRIVL   0x0000FFFFU
 
#define USB_OTG_HFNUM_FRNUM   0x0000FFFFU
 
#define USB_OTG_HFNUM_FTREM   0xFFFF0000U
 
#define USB_OTG_DSTS_SUSPSTS   0x00000001U
 
#define USB_OTG_DSTS_ENUMSPD   0x00000006U
 
#define USB_OTG_DSTS_ENUMSPD_0   0x00000002U
 
#define USB_OTG_DSTS_ENUMSPD_1   0x00000004U
 
#define USB_OTG_DSTS_EERR   0x00000008U
 
#define USB_OTG_DSTS_FNSOF   0x003FFF00U
 
#define USB_OTG_GAHBCFG_GINT   0x00000001U
 
#define USB_OTG_GAHBCFG_HBSTLEN   0x0000001EU
 
#define USB_OTG_GAHBCFG_HBSTLEN_0   0x00000002U
 
#define USB_OTG_GAHBCFG_HBSTLEN_1   0x00000004U
 
#define USB_OTG_GAHBCFG_HBSTLEN_2   0x00000008U
 
#define USB_OTG_GAHBCFG_HBSTLEN_3   0x00000010U
 
#define USB_OTG_GAHBCFG_DMAEN   0x00000020U
 
#define USB_OTG_GAHBCFG_TXFELVL   0x00000080U
 
#define USB_OTG_GAHBCFG_PTXFELVL   0x00000100U
 
#define USB_OTG_GUSBCFG_TOCAL   0x00000007U
 
#define USB_OTG_GUSBCFG_TOCAL_0   0x00000001U
 
#define USB_OTG_GUSBCFG_TOCAL_1   0x00000002U
 
#define USB_OTG_GUSBCFG_TOCAL_2   0x00000004U
 
#define USB_OTG_GUSBCFG_PHYSEL   0x00000040U
 
#define USB_OTG_GUSBCFG_SRPCAP   0x00000100U
 
#define USB_OTG_GUSBCFG_HNPCAP   0x00000200U
 
#define USB_OTG_GUSBCFG_TRDT   0x00003C00U
 
#define USB_OTG_GUSBCFG_TRDT_0   0x00000400U
 
#define USB_OTG_GUSBCFG_TRDT_1   0x00000800U
 
#define USB_OTG_GUSBCFG_TRDT_2   0x00001000U
 
#define USB_OTG_GUSBCFG_TRDT_3   0x00002000U
 
#define USB_OTG_GUSBCFG_PHYLPCS   0x00008000U
 
#define USB_OTG_GUSBCFG_ULPIFSLS   0x00020000U
 
#define USB_OTG_GUSBCFG_ULPIAR   0x00040000U
 
#define USB_OTG_GUSBCFG_ULPICSM   0x00080000U
 
#define USB_OTG_GUSBCFG_ULPIEVBUSD   0x00100000U
 
#define USB_OTG_GUSBCFG_ULPIEVBUSI   0x00200000U
 
#define USB_OTG_GUSBCFG_TSDPS   0x00400000U
 
#define USB_OTG_GUSBCFG_PCCI   0x00800000U
 
#define USB_OTG_GUSBCFG_PTCI   0x01000000U
 
#define USB_OTG_GUSBCFG_ULPIIPD   0x02000000U
 
#define USB_OTG_GUSBCFG_FHMOD   0x20000000U
 
#define USB_OTG_GUSBCFG_FDMOD   0x40000000U
 
#define USB_OTG_GUSBCFG_CTXPKT   0x80000000U
 
#define USB_OTG_GRSTCTL_CSRST   0x00000001U
 
#define USB_OTG_GRSTCTL_HSRST   0x00000002U
 
#define USB_OTG_GRSTCTL_FCRST   0x00000004U
 
#define USB_OTG_GRSTCTL_RXFFLSH   0x00000010U
 
#define USB_OTG_GRSTCTL_TXFFLSH   0x00000020U
 
#define USB_OTG_GRSTCTL_TXFNUM   0x000007C0U
 
#define USB_OTG_GRSTCTL_TXFNUM_0   0x00000040U
 
#define USB_OTG_GRSTCTL_TXFNUM_1   0x00000080U
 
#define USB_OTG_GRSTCTL_TXFNUM_2   0x00000100U
 
#define USB_OTG_GRSTCTL_TXFNUM_3   0x00000200U
 
#define USB_OTG_GRSTCTL_TXFNUM_4   0x00000400U
 
#define USB_OTG_GRSTCTL_DMAREQ   0x40000000U
 
#define USB_OTG_GRSTCTL_AHBIDL   0x80000000U
 
#define USB_OTG_DIEPMSK_XFRCM   0x00000001U
 
#define USB_OTG_DIEPMSK_EPDM   0x00000002U
 
#define USB_OTG_DIEPMSK_TOM   0x00000008U
 
#define USB_OTG_DIEPMSK_ITTXFEMSK   0x00000010U
 
#define USB_OTG_DIEPMSK_INEPNMM   0x00000020U
 
#define USB_OTG_DIEPMSK_INEPNEM   0x00000040U
 
#define USB_OTG_DIEPMSK_TXFURM   0x00000100U
 
#define USB_OTG_DIEPMSK_BIM   0x00000200U
 
#define USB_OTG_HPTXSTS_PTXFSAVL   0x0000FFFFU
 
#define USB_OTG_HPTXSTS_PTXQSAV   0x00FF0000U
 
#define USB_OTG_HPTXSTS_PTXQSAV_0   0x00010000U
 
#define USB_OTG_HPTXSTS_PTXQSAV_1   0x00020000U
 
#define USB_OTG_HPTXSTS_PTXQSAV_2   0x00040000U
 
#define USB_OTG_HPTXSTS_PTXQSAV_3   0x00080000U
 
#define USB_OTG_HPTXSTS_PTXQSAV_4   0x00100000U
 
#define USB_OTG_HPTXSTS_PTXQSAV_5   0x00200000U
 
#define USB_OTG_HPTXSTS_PTXQSAV_6   0x00400000U
 
#define USB_OTG_HPTXSTS_PTXQSAV_7   0x00800000U
 
#define USB_OTG_HPTXSTS_PTXQTOP   0xFF000000U
 
#define USB_OTG_HPTXSTS_PTXQTOP_0   0x01000000U
 
#define USB_OTG_HPTXSTS_PTXQTOP_1   0x02000000U
 
#define USB_OTG_HPTXSTS_PTXQTOP_2   0x04000000U
 
#define USB_OTG_HPTXSTS_PTXQTOP_3   0x08000000U
 
#define USB_OTG_HPTXSTS_PTXQTOP_4   0x10000000U
 
#define USB_OTG_HPTXSTS_PTXQTOP_5   0x20000000U
 
#define USB_OTG_HPTXSTS_PTXQTOP_6   0x40000000U
 
#define USB_OTG_HPTXSTS_PTXQTOP_7   0x80000000U
 
#define USB_OTG_HAINT_HAINT   0x0000FFFFU
 
#define USB_OTG_DOEPMSK_XFRCM   0x00000001U
 
#define USB_OTG_DOEPMSK_EPDM   0x00000002U
 
#define USB_OTG_DOEPMSK_STUPM   0x00000008U
 
#define USB_OTG_DOEPMSK_OTEPDM   0x00000010U
 
#define USB_OTG_DOEPMSK_OTEPSPRM   0x00000020U
 
#define USB_OTG_DOEPMSK_B2BSTUP   0x00000040U
 
#define USB_OTG_DOEPMSK_OPEM   0x00000100U
 
#define USB_OTG_DOEPMSK_BOIM   0x00000200U
 
#define USB_OTG_GINTSTS_CMOD   0x00000001U
 
#define USB_OTG_GINTSTS_MMIS   0x00000002U
 
#define USB_OTG_GINTSTS_OTGINT   0x00000004U
 
#define USB_OTG_GINTSTS_SOF   0x00000008U
 
#define USB_OTG_GINTSTS_RXFLVL   0x00000010U
 
#define USB_OTG_GINTSTS_NPTXFE   0x00000020U
 
#define USB_OTG_GINTSTS_GINAKEFF   0x00000040U
 
#define USB_OTG_GINTSTS_BOUTNAKEFF   0x00000080U
 
#define USB_OTG_GINTSTS_ESUSP   0x00000400U
 
#define USB_OTG_GINTSTS_USBSUSP   0x00000800U
 
#define USB_OTG_GINTSTS_USBRST   0x00001000U
 
#define USB_OTG_GINTSTS_ENUMDNE   0x00002000U
 
#define USB_OTG_GINTSTS_ISOODRP   0x00004000U
 
#define USB_OTG_GINTSTS_EOPF   0x00008000U
 
#define USB_OTG_GINTSTS_IEPINT   0x00040000U
 
#define USB_OTG_GINTSTS_OEPINT   0x00080000U
 
#define USB_OTG_GINTSTS_IISOIXFR   0x00100000U
 
#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT   0x00200000U
 
#define USB_OTG_GINTSTS_DATAFSUSP   0x00400000U
 
#define USB_OTG_GINTSTS_RSTDET   0x00800000U
 
#define USB_OTG_GINTSTS_HPRTINT   0x01000000U
 
#define USB_OTG_GINTSTS_HCINT   0x02000000U
 
#define USB_OTG_GINTSTS_PTXFE   0x04000000U
 
#define USB_OTG_GINTSTS_LPMINT   0x08000000U
 
#define USB_OTG_GINTSTS_CIDSCHG   0x10000000U
 
#define USB_OTG_GINTSTS_DISCINT   0x20000000U
 
#define USB_OTG_GINTSTS_SRQINT   0x40000000U
 
#define USB_OTG_GINTSTS_WKUINT   0x80000000U
 
#define USB_OTG_GINTMSK_MMISM   0x00000002U
 
#define USB_OTG_GINTMSK_OTGINT   0x00000004U
 
#define USB_OTG_GINTMSK_SOFM   0x00000008U
 
#define USB_OTG_GINTMSK_RXFLVLM   0x00000010U
 
#define USB_OTG_GINTMSK_NPTXFEM   0x00000020U
 
#define USB_OTG_GINTMSK_GINAKEFFM   0x00000040U
 
#define USB_OTG_GINTMSK_GONAKEFFM   0x00000080U
 
#define USB_OTG_GINTMSK_ESUSPM   0x00000400U
 
#define USB_OTG_GINTMSK_USBSUSPM   0x00000800U
 
#define USB_OTG_GINTMSK_USBRST   0x00001000U
 
#define USB_OTG_GINTMSK_ENUMDNEM   0x00002000U
 
#define USB_OTG_GINTMSK_ISOODRPM   0x00004000U
 
#define USB_OTG_GINTMSK_EOPFM   0x00008000U
 
#define USB_OTG_GINTMSK_EPMISM   0x00020000U
 
#define USB_OTG_GINTMSK_IEPINT   0x00040000U
 
#define USB_OTG_GINTMSK_OEPINT   0x00080000U
 
#define USB_OTG_GINTMSK_IISOIXFRM   0x00100000U
 
#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM   0x00200000U
 
#define USB_OTG_GINTMSK_FSUSPM   0x00400000U
 
#define USB_OTG_GINTMSK_RSTDEM   0x00800000U
 
#define USB_OTG_GINTMSK_PRTIM   0x01000000U
 
#define USB_OTG_GINTMSK_HCIM   0x02000000U
 
#define USB_OTG_GINTMSK_PTXFEM   0x04000000U
 
#define USB_OTG_GINTMSK_LPMINTM   0x08000000U
 
#define USB_OTG_GINTMSK_CIDSCHGM   0x10000000U
 
#define USB_OTG_GINTMSK_DISCINT   0x20000000U
 
#define USB_OTG_GINTMSK_SRQIM   0x40000000U
 
#define USB_OTG_GINTMSK_WUIM   0x80000000U
 
#define USB_OTG_DAINT_IEPINT   0x0000FFFFU
 
#define USB_OTG_DAINT_OEPINT   0xFFFF0000U
 
#define USB_OTG_HAINTMSK_HAINTM   0x0000FFFFU
 
#define USB_OTG_GRXSTSP_EPNUM   0x0000000FU
 
#define USB_OTG_GRXSTSP_BCNT   0x00007FF0U
 
#define USB_OTG_GRXSTSP_DPID   0x00018000U
 
#define USB_OTG_GRXSTSP_PKTSTS   0x001E0000U
 
#define USB_OTG_DAINTMSK_IEPM   0x0000FFFFU
 
#define USB_OTG_DAINTMSK_OEPM   0xFFFF0000U
 
#define USB_OTG_CHNUM   0x0000000FU
 
#define USB_OTG_CHNUM   0x0000000FU
 
#define USB_OTG_CHNUM_0   0x00000001U
 
#define USB_OTG_CHNUM_0   0x00000001U
 
#define USB_OTG_CHNUM_1   0x00000002U
 
#define USB_OTG_CHNUM_1   0x00000002U
 
#define USB_OTG_CHNUM_2   0x00000004U
 
#define USB_OTG_CHNUM_2   0x00000004U
 
#define USB_OTG_CHNUM_3   0x00000008U
 
#define USB_OTG_CHNUM_3   0x00000008U
 
#define USB_OTG_BCNT   0x00007FF0U
 
#define USB_OTG_BCNT   0x00007FF0U
 
#define USB_OTG_DPID   0x00018000U
 
#define USB_OTG_DPID   0x00018000U
 
#define USB_OTG_DPID_0   0x00008000U
 
#define USB_OTG_DPID_0   0x00008000U
 
#define USB_OTG_DPID_1   0x00010000U
 
#define USB_OTG_DPID_1   0x00010000U
 
#define USB_OTG_PKTSTS   0x001E0000U
 
#define USB_OTG_PKTSTS   0x001E0000U
 
#define USB_OTG_PKTSTS_0   0x00020000U
 
#define USB_OTG_PKTSTS_0   0x00020000U
 
#define USB_OTG_PKTSTS_1   0x00040000U
 
#define USB_OTG_PKTSTS_1   0x00040000U
 
#define USB_OTG_PKTSTS_2   0x00080000U
 
#define USB_OTG_PKTSTS_2   0x00080000U
 
#define USB_OTG_PKTSTS_3   0x00100000U
 
#define USB_OTG_PKTSTS_3   0x00100000U
 
#define USB_OTG_EPNUM   0x0000000FU
 
#define USB_OTG_EPNUM   0x0000000FU
 
#define USB_OTG_EPNUM_0   0x00000001U
 
#define USB_OTG_EPNUM_0   0x00000001U
 
#define USB_OTG_EPNUM_1   0x00000002U
 
#define USB_OTG_EPNUM_1   0x00000002U
 
#define USB_OTG_EPNUM_2   0x00000004U
 
#define USB_OTG_EPNUM_2   0x00000004U
 
#define USB_OTG_EPNUM_3   0x00000008U
 
#define USB_OTG_EPNUM_3   0x00000008U
 
#define USB_OTG_FRMNUM   0x01E00000U
 
#define USB_OTG_FRMNUM   0x01E00000U
 
#define USB_OTG_FRMNUM_0   0x00200000U
 
#define USB_OTG_FRMNUM_0   0x00200000U
 
#define USB_OTG_FRMNUM_1   0x00400000U
 
#define USB_OTG_FRMNUM_1   0x00400000U
 
#define USB_OTG_FRMNUM_2   0x00800000U
 
#define USB_OTG_FRMNUM_2   0x00800000U
 
#define USB_OTG_FRMNUM_3   0x01000000U
 
#define USB_OTG_FRMNUM_3   0x01000000U
 
#define USB_OTG_GRXFSIZ_RXFD   0x0000FFFFU
 
#define USB_OTG_DVBUSDIS_VBUSDT   0x0000FFFFU
 
#define USB_OTG_NPTXFSA   0x0000FFFFU
 
#define USB_OTG_NPTXFD   0xFFFF0000U
 
#define USB_OTG_TX0FSA   0x0000FFFFU
 
#define USB_OTG_TX0FD   0xFFFF0000U
 
#define USB_OTG_DVBUSPULSE_DVBUSP   0x00000FFFU
 
#define USB_OTG_GNPTXSTS_NPTXFSAV   0x0000FFFFU
 
#define USB_OTG_GNPTXSTS_NPTQXSAV   0x00FF0000U
 
#define USB_OTG_GNPTXSTS_NPTQXSAV_0   0x00010000U
 
#define USB_OTG_GNPTXSTS_NPTQXSAV_1   0x00020000U
 
#define USB_OTG_GNPTXSTS_NPTQXSAV_2   0x00040000U
 
#define USB_OTG_GNPTXSTS_NPTQXSAV_3   0x00080000U
 
#define USB_OTG_GNPTXSTS_NPTQXSAV_4   0x00100000U
 
#define USB_OTG_GNPTXSTS_NPTQXSAV_5   0x00200000U
 
#define USB_OTG_GNPTXSTS_NPTQXSAV_6   0x00400000U
 
#define USB_OTG_GNPTXSTS_NPTQXSAV_7   0x00800000U
 
#define USB_OTG_GNPTXSTS_NPTXQTOP   0x7F000000U
 
#define USB_OTG_GNPTXSTS_NPTXQTOP_0   0x01000000U
 
#define USB_OTG_GNPTXSTS_NPTXQTOP_1   0x02000000U
 
#define USB_OTG_GNPTXSTS_NPTXQTOP_2   0x04000000U
 
#define USB_OTG_GNPTXSTS_NPTXQTOP_3   0x08000000U
 
#define USB_OTG_GNPTXSTS_NPTXQTOP_4   0x10000000U
 
#define USB_OTG_GNPTXSTS_NPTXQTOP_5   0x20000000U
 
#define USB_OTG_GNPTXSTS_NPTXQTOP_6   0x40000000U
 
#define USB_OTG_DTHRCTL_NONISOTHREN   0x00000001U
 
#define USB_OTG_DTHRCTL_ISOTHREN   0x00000002U
 
#define USB_OTG_DTHRCTL_TXTHRLEN   0x000007FCU
 
#define USB_OTG_DTHRCTL_TXTHRLEN_0   0x00000004U
 
#define USB_OTG_DTHRCTL_TXTHRLEN_1   0x00000008U
 
#define USB_OTG_DTHRCTL_TXTHRLEN_2   0x00000010U
 
#define USB_OTG_DTHRCTL_TXTHRLEN_3   0x00000020U
 
#define USB_OTG_DTHRCTL_TXTHRLEN_4   0x00000040U
 
#define USB_OTG_DTHRCTL_TXTHRLEN_5   0x00000080U
 
#define USB_OTG_DTHRCTL_TXTHRLEN_6   0x00000100U
 
#define USB_OTG_DTHRCTL_TXTHRLEN_7   0x00000200U
 
#define USB_OTG_DTHRCTL_TXTHRLEN_8   0x00000400U
 
#define USB_OTG_DTHRCTL_RXTHREN   0x00010000U
 
#define USB_OTG_DTHRCTL_RXTHRLEN   0x03FE0000U
 
#define USB_OTG_DTHRCTL_RXTHRLEN_0   0x00020000U
 
#define USB_OTG_DTHRCTL_RXTHRLEN_1   0x00040000U
 
#define USB_OTG_DTHRCTL_RXTHRLEN_2   0x00080000U
 
#define USB_OTG_DTHRCTL_RXTHRLEN_3   0x00100000U
 
#define USB_OTG_DTHRCTL_RXTHRLEN_4   0x00200000U
 
#define USB_OTG_DTHRCTL_RXTHRLEN_5   0x00400000U
 
#define USB_OTG_DTHRCTL_RXTHRLEN_6   0x00800000U
 
#define USB_OTG_DTHRCTL_RXTHRLEN_7   0x01000000U
 
#define USB_OTG_DTHRCTL_RXTHRLEN_8   0x02000000U
 
#define USB_OTG_DTHRCTL_ARPEN   0x08000000U
 
#define USB_OTG_DIEPEMPMSK_INEPTXFEM   0x0000FFFFU
 
#define USB_OTG_DEACHINT_IEP1INT   0x00000002U
 
#define USB_OTG_DEACHINT_OEP1INT   0x00020000U
 
#define USB_OTG_GCCFG_PWRDWN   0x00010000U
 
#define USB_OTG_GCCFG_VBDEN   0x00200000U
 
#define USB_OTG_GPWRDN_ADPMEN   0x00000001U
 
#define USB_OTG_GPWRDN_ADPIF   0x00800000U
 
#define USB_OTG_DEACHINTMSK_IEP1INTM   0x00000002U
 
#define USB_OTG_DEACHINTMSK_OEP1INTM   0x00020000U
 
#define USB_OTG_CID_PRODUCT_ID   0xFFFFFFFFU
 
#define USB_OTG_GLPMCFG_LPMEN   0x00000001U
 
#define USB_OTG_GLPMCFG_LPMACK   0x00000002U
 
#define USB_OTG_GLPMCFG_BESL   0x0000003CU
 
#define USB_OTG_GLPMCFG_REMWAKE   0x00000040U
 
#define USB_OTG_GLPMCFG_L1SSEN   0x00000080U
 
#define USB_OTG_GLPMCFG_BESLTHRS   0x00000F00U
 
#define USB_OTG_GLPMCFG_L1DSEN   0x00001000U
 
#define USB_OTG_GLPMCFG_LPMRSP   0x00006000U
 
#define USB_OTG_GLPMCFG_SLPSTS   0x00008000U
 
#define USB_OTG_GLPMCFG_L1RSMOK   0x00010000U
 
#define USB_OTG_GLPMCFG_LPMCHIDX   0x001E0000U
 
#define USB_OTG_GLPMCFG_LPMRCNT   0x00E00000U
 
#define USB_OTG_GLPMCFG_SNDLPM   0x01000000U
 
#define USB_OTG_GLPMCFG_LPMRCNTSTS   0x0E000000U
 
#define USB_OTG_GLPMCFG_ENBESL   0x10000000U
 
#define USB_OTG_DIEPEACHMSK1_XFRCM   0x00000001U
 
#define USB_OTG_DIEPEACHMSK1_EPDM   0x00000002U
 
#define USB_OTG_DIEPEACHMSK1_TOM   0x00000008U
 
#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK   0x00000010U
 
#define USB_OTG_DIEPEACHMSK1_INEPNMM   0x00000020U
 
#define USB_OTG_DIEPEACHMSK1_INEPNEM   0x00000040U
 
#define USB_OTG_DIEPEACHMSK1_TXFURM   0x00000100U
 
#define USB_OTG_DIEPEACHMSK1_BIM   0x00000200U
 
#define USB_OTG_DIEPEACHMSK1_NAKM   0x00002000U
 
#define USB_OTG_HPRT_PCSTS   0x00000001U
 
#define USB_OTG_HPRT_PCDET   0x00000002U
 
#define USB_OTG_HPRT_PENA   0x00000004U
 
#define USB_OTG_HPRT_PENCHNG   0x00000008U
 
#define USB_OTG_HPRT_POCA   0x00000010U
 
#define USB_OTG_HPRT_POCCHNG   0x00000020U
 
#define USB_OTG_HPRT_PRES   0x00000040U
 
#define USB_OTG_HPRT_PSUSP   0x00000080U
 
#define USB_OTG_HPRT_PRST   0x00000100U
 
#define USB_OTG_HPRT_PLSTS   0x00000C00U
 
#define USB_OTG_HPRT_PLSTS_0   0x00000400U
 
#define USB_OTG_HPRT_PLSTS_1   0x00000800U
 
#define USB_OTG_HPRT_PPWR   0x00001000U
 
#define USB_OTG_HPRT_PTCTL   0x0001E000U
 
#define USB_OTG_HPRT_PTCTL_0   0x00002000U
 
#define USB_OTG_HPRT_PTCTL_1   0x00004000U
 
#define USB_OTG_HPRT_PTCTL_2   0x00008000U
 
#define USB_OTG_HPRT_PTCTL_3   0x00010000U
 
#define USB_OTG_HPRT_PSPD   0x00060000U
 
#define USB_OTG_HPRT_PSPD_0   0x00020000U
 
#define USB_OTG_HPRT_PSPD_1   0x00040000U
 
#define USB_OTG_DOEPEACHMSK1_XFRCM   0x00000001U
 
#define USB_OTG_DOEPEACHMSK1_EPDM   0x00000002U
 
#define USB_OTG_DOEPEACHMSK1_TOM   0x00000008U
 
#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK   0x00000010U
 
#define USB_OTG_DOEPEACHMSK1_INEPNMM   0x00000020U
 
#define USB_OTG_DOEPEACHMSK1_INEPNEM   0x00000040U
 
#define USB_OTG_DOEPEACHMSK1_TXFURM   0x00000100U
 
#define USB_OTG_DOEPEACHMSK1_BIM   0x00000200U
 
#define USB_OTG_DOEPEACHMSK1_BERRM   0x00001000U
 
#define USB_OTG_DOEPEACHMSK1_NAKM   0x00002000U
 
#define USB_OTG_DOEPEACHMSK1_NYETM   0x00004000U
 
#define USB_OTG_HPTXFSIZ_PTXSA   0x0000FFFFU
 
#define USB_OTG_HPTXFSIZ_PTXFD   0xFFFF0000U
 
#define USB_OTG_DIEPCTL_MPSIZ   0x000007FFU
 
#define USB_OTG_DIEPCTL_USBAEP   0x00008000U
 
#define USB_OTG_DIEPCTL_EONUM_DPID   0x00010000U
 
#define USB_OTG_DIEPCTL_NAKSTS   0x00020000U
 
#define USB_OTG_DIEPCTL_EPTYP   0x000C0000U
 
#define USB_OTG_DIEPCTL_EPTYP_0   0x00040000U
 
#define USB_OTG_DIEPCTL_EPTYP_1   0x00080000U
 
#define USB_OTG_DIEPCTL_STALL   0x00200000U
 
#define USB_OTG_DIEPCTL_TXFNUM   0x03C00000U
 
#define USB_OTG_DIEPCTL_TXFNUM_0   0x00400000U
 
#define USB_OTG_DIEPCTL_TXFNUM_1   0x00800000U
 
#define USB_OTG_DIEPCTL_TXFNUM_2   0x01000000U
 
#define USB_OTG_DIEPCTL_TXFNUM_3   0x02000000U
 
#define USB_OTG_DIEPCTL_CNAK   0x04000000U
 
#define USB_OTG_DIEPCTL_SNAK   0x08000000U
 
#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM   0x10000000U
 
#define USB_OTG_DIEPCTL_SODDFRM   0x20000000U
 
#define USB_OTG_DIEPCTL_EPDIS   0x40000000U
 
#define USB_OTG_DIEPCTL_EPENA   0x80000000U
 
#define USB_OTG_HCCHAR_MPSIZ   0x000007FFU
 
#define USB_OTG_HCCHAR_EPNUM   0x00007800U
 
#define USB_OTG_HCCHAR_EPNUM_0   0x00000800U
 
#define USB_OTG_HCCHAR_EPNUM_1   0x00001000U
 
#define USB_OTG_HCCHAR_EPNUM_2   0x00002000U
 
#define USB_OTG_HCCHAR_EPNUM_3   0x00004000U
 
#define USB_OTG_HCCHAR_EPDIR   0x00008000U
 
#define USB_OTG_HCCHAR_LSDEV   0x00020000U
 
#define USB_OTG_HCCHAR_EPTYP   0x000C0000U
 
#define USB_OTG_HCCHAR_EPTYP_0   0x00040000U
 
#define USB_OTG_HCCHAR_EPTYP_1   0x00080000U
 
#define USB_OTG_HCCHAR_MC   0x00300000U
 
#define USB_OTG_HCCHAR_MC_0   0x00100000U
 
#define USB_OTG_HCCHAR_MC_1   0x00200000U
 
#define USB_OTG_HCCHAR_DAD   0x1FC00000U
 
#define USB_OTG_HCCHAR_DAD_0   0x00400000U
 
#define USB_OTG_HCCHAR_DAD_1   0x00800000U
 
#define USB_OTG_HCCHAR_DAD_2   0x01000000U
 
#define USB_OTG_HCCHAR_DAD_3   0x02000000U
 
#define USB_OTG_HCCHAR_DAD_4   0x04000000U
 
#define USB_OTG_HCCHAR_DAD_5   0x08000000U
 
#define USB_OTG_HCCHAR_DAD_6   0x10000000U
 
#define USB_OTG_HCCHAR_ODDFRM   0x20000000U
 
#define USB_OTG_HCCHAR_CHDIS   0x40000000U
 
#define USB_OTG_HCCHAR_CHENA   0x80000000U
 
#define USB_OTG_HCSPLT_PRTADDR   0x0000007FU
 
#define USB_OTG_HCSPLT_PRTADDR_0   0x00000001U
 
#define USB_OTG_HCSPLT_PRTADDR_1   0x00000002U
 
#define USB_OTG_HCSPLT_PRTADDR_2   0x00000004U
 
#define USB_OTG_HCSPLT_PRTADDR_3   0x00000008U
 
#define USB_OTG_HCSPLT_PRTADDR_4   0x00000010U
 
#define USB_OTG_HCSPLT_PRTADDR_5   0x00000020U
 
#define USB_OTG_HCSPLT_PRTADDR_6   0x00000040U
 
#define USB_OTG_HCSPLT_HUBADDR   0x00003F80U
 
#define USB_OTG_HCSPLT_HUBADDR_0   0x00000080U
 
#define USB_OTG_HCSPLT_HUBADDR_1   0x00000100U
 
#define USB_OTG_HCSPLT_HUBADDR_2   0x00000200U
 
#define USB_OTG_HCSPLT_HUBADDR_3   0x00000400U
 
#define USB_OTG_HCSPLT_HUBADDR_4   0x00000800U
 
#define USB_OTG_HCSPLT_HUBADDR_5   0x00001000U
 
#define USB_OTG_HCSPLT_HUBADDR_6   0x00002000U
 
#define USB_OTG_HCSPLT_XACTPOS   0x0000C000U
 
#define USB_OTG_HCSPLT_XACTPOS_0   0x00004000U
 
#define USB_OTG_HCSPLT_XACTPOS_1   0x00008000U
 
#define USB_OTG_HCSPLT_COMPLSPLT   0x00010000U
 
#define USB_OTG_HCSPLT_SPLITEN   0x80000000U
 
#define USB_OTG_HCINT_XFRC   0x00000001U
 
#define USB_OTG_HCINT_CHH   0x00000002U
 
#define USB_OTG_HCINT_AHBERR   0x00000004U
 
#define USB_OTG_HCINT_STALL   0x00000008U
 
#define USB_OTG_HCINT_NAK   0x00000010U
 
#define USB_OTG_HCINT_ACK   0x00000020U
 
#define USB_OTG_HCINT_NYET   0x00000040U
 
#define USB_OTG_HCINT_TXERR   0x00000080U
 
#define USB_OTG_HCINT_BBERR   0x00000100U
 
#define USB_OTG_HCINT_FRMOR   0x00000200U
 
#define USB_OTG_HCINT_DTERR   0x00000400U
 
#define USB_OTG_DIEPINT_XFRC   0x00000001U
 
#define USB_OTG_DIEPINT_EPDISD   0x00000002U
 
#define USB_OTG_DIEPINT_TOC   0x00000008U
 
#define USB_OTG_DIEPINT_ITTXFE   0x00000010U
 
#define USB_OTG_DIEPINT_INEPNE   0x00000040U
 
#define USB_OTG_DIEPINT_TXFE   0x00000080U
 
#define USB_OTG_DIEPINT_TXFIFOUDRN   0x00000100U
 
#define USB_OTG_DIEPINT_BNA   0x00000200U
 
#define USB_OTG_DIEPINT_PKTDRPSTS   0x00000800U
 
#define USB_OTG_DIEPINT_BERR   0x00001000U
 
#define USB_OTG_DIEPINT_NAK   0x00002000U
 
#define USB_OTG_HCINTMSK_XFRCM   0x00000001U
 
#define USB_OTG_HCINTMSK_CHHM   0x00000002U
 
#define USB_OTG_HCINTMSK_AHBERR   0x00000004U
 
#define USB_OTG_HCINTMSK_STALLM   0x00000008U
 
#define USB_OTG_HCINTMSK_NAKM   0x00000010U
 
#define USB_OTG_HCINTMSK_ACKM   0x00000020U
 
#define USB_OTG_HCINTMSK_NYET   0x00000040U
 
#define USB_OTG_HCINTMSK_TXERRM   0x00000080U
 
#define USB_OTG_HCINTMSK_BBERRM   0x00000100U
 
#define USB_OTG_HCINTMSK_FRMORM   0x00000200U
 
#define USB_OTG_HCINTMSK_DTERRM   0x00000400U
 
#define USB_OTG_DIEPTSIZ_XFRSIZ   0x0007FFFFU
 
#define USB_OTG_DIEPTSIZ_PKTCNT   0x1FF80000U
 
#define USB_OTG_DIEPTSIZ_MULCNT   0x60000000U
 
#define USB_OTG_HCTSIZ_XFRSIZ   0x0007FFFFU
 
#define USB_OTG_HCTSIZ_PKTCNT   0x1FF80000U
 
#define USB_OTG_HCTSIZ_DOPING   0x80000000U
 
#define USB_OTG_HCTSIZ_DPID   0x60000000U
 
#define USB_OTG_HCTSIZ_DPID_0   0x20000000U
 
#define USB_OTG_HCTSIZ_DPID_1   0x40000000U
 
#define USB_OTG_DIEPDMA_DMAADDR   0xFFFFFFFFU
 
#define USB_OTG_HCDMA_DMAADDR   0xFFFFFFFFU
 
#define USB_OTG_DTXFSTS_INEPTFSAV   0x0000FFFFU
 
#define USB_OTG_DIEPTXF_INEPTXSA   0x0000FFFFU
 
#define USB_OTG_DIEPTXF_INEPTXFD   0xFFFF0000U
 
#define USB_OTG_DOEPCTL_MPSIZ   0x000007FFU /*!< Maximum packet size */
 
#define USB_OTG_DOEPCTL_USBAEP   0x00008000U
 
#define USB_OTG_DOEPCTL_NAKSTS   0x00020000U
 
#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM   0x10000000U
 
#define USB_OTG_DOEPCTL_SODDFRM   0x20000000U
 
#define USB_OTG_DOEPCTL_EPTYP   0x000C0000U
 
#define USB_OTG_DOEPCTL_EPTYP_0   0x00040000U
 
#define USB_OTG_DOEPCTL_EPTYP_1   0x00080000U
 
#define USB_OTG_DOEPCTL_SNPM   0x00100000U
 
#define USB_OTG_DOEPCTL_STALL   0x00200000U
 
#define USB_OTG_DOEPCTL_CNAK   0x04000000U
 
#define USB_OTG_DOEPCTL_SNAK   0x08000000U
 
#define USB_OTG_DOEPCTL_EPDIS   0x40000000U
 
#define USB_OTG_DOEPCTL_EPENA   0x80000000U
 
#define USB_OTG_DOEPINT_XFRC   0x00000001U
 
#define USB_OTG_DOEPINT_EPDISD   0x00000002U
 
#define USB_OTG_DOEPINT_STUP   0x00000008U
 
#define USB_OTG_DOEPINT_OTEPDIS   0x00000010U
 
#define USB_OTG_DOEPINT_OTEPSPR   0x00000020U
 
#define USB_OTG_DOEPINT_B2BSTUP   0x00000040U
 
#define USB_OTG_DOEPINT_NYET   0x00004000U
 
#define USB_OTG_DOEPTSIZ_XFRSIZ   0x0007FFFFU
 
#define USB_OTG_DOEPTSIZ_PKTCNT   0x1FF80000U
 
#define USB_OTG_DOEPTSIZ_STUPCNT   0x60000000U
 
#define USB_OTG_DOEPTSIZ_STUPCNT_0   0x20000000U
 
#define USB_OTG_DOEPTSIZ_STUPCNT_1   0x40000000U
 
#define USB_OTG_PCGCCTL_STOPCLK   0x00000001U
 
#define USB_OTG_PCGCCTL_GATECLK   0x00000002U
 
#define USB_OTG_PCGCCTL_PHYSUSP   0x00000010U
 

Detailed Description

Macro Definition Documentation

#define ADC_CCR_ADCPRE   0x00030000U

ADCPRE[1:0] bits (ADC prescaler)

#define ADC_CCR_ADCPRE_0   0x00010000U

Bit 0

#define ADC_CCR_ADCPRE_1   0x00020000U

Bit 1

#define ADC_CCR_DDS   0x00002000U

DMA disable selection (Multi-ADC mode)

#define ADC_CCR_DELAY   0x00000F00U

DELAY[3:0] bits (Delay between 2 sampling phases)

#define ADC_CCR_DELAY_0   0x00000100U

Bit 0

#define ADC_CCR_DELAY_1   0x00000200U

Bit 1

#define ADC_CCR_DELAY_2   0x00000400U

Bit 2

#define ADC_CCR_DELAY_3   0x00000800U

Bit 3

#define ADC_CCR_DMA   0x0000C000U

DMA[1:0] bits (Direct Memory Access mode for multimode)

#define ADC_CCR_DMA_0   0x00004000U

Bit 0

#define ADC_CCR_DMA_1   0x00008000U

Bit 1

#define ADC_CCR_MULTI   0x0000001FU

MULTI[4:0] bits (Multi-ADC mode selection)

#define ADC_CCR_MULTI_0   0x00000001U

Bit 0

#define ADC_CCR_MULTI_1   0x00000002U

Bit 1

#define ADC_CCR_MULTI_2   0x00000004U

Bit 2

#define ADC_CCR_MULTI_3   0x00000008U

Bit 3

#define ADC_CCR_MULTI_4   0x00000010U

Bit 4

#define ADC_CCR_TSVREFE   0x00800000U

Temperature Sensor and VREFINT Enable

#define ADC_CCR_VBATE   0x00400000U

VBAT Enable

#define ADC_CDR_DATA1   0x0000FFFFU

1st data of a pair of regular conversions

#define ADC_CDR_DATA2   0xFFFF0000U

2nd data of a pair of regular conversions

#define ADC_CR1_AWDCH   0x0000001FU

AWDCH[4:0] bits (Analog watchdog channel select bits)

#define ADC_CR1_AWDCH_0   0x00000001U

Bit 0

#define ADC_CR1_AWDCH_1   0x00000002U

Bit 1

#define ADC_CR1_AWDCH_2   0x00000004U

Bit 2

#define ADC_CR1_AWDCH_3   0x00000008U

Bit 3

#define ADC_CR1_AWDCH_4   0x00000010U

Bit 4

#define ADC_CR1_AWDEN   0x00800000U

Analog watchdog enable on regular channels

#define ADC_CR1_AWDIE   0x00000040U

AAnalog Watchdog interrupt enable

#define ADC_CR1_AWDSGL   0x00000200U

Enable the watchdog on a single channel in scan mode

#define ADC_CR1_DISCEN   0x00000800U

Discontinuous mode on regular channels

#define ADC_CR1_DISCNUM   0x0000E000U

DISCNUM[2:0] bits (Discontinuous mode channel count)

#define ADC_CR1_DISCNUM_0   0x00002000U

Bit 0

#define ADC_CR1_DISCNUM_1   0x00004000U

Bit 1

#define ADC_CR1_DISCNUM_2   0x00008000U

Bit 2

#define ADC_CR1_EOCIE   0x00000020U

Interrupt enable for EOC

#define ADC_CR1_JAUTO   0x00000400U

Automatic injected group conversion

#define ADC_CR1_JAWDEN   0x00400000U

Analog watchdog enable on injected channels

#define ADC_CR1_JDISCEN   0x00001000U

Discontinuous mode on injected channels

#define ADC_CR1_JEOCIE   0x00000080U

Interrupt enable for injected channels

#define ADC_CR1_OVRIE   0x04000000U

overrun interrupt enable

#define ADC_CR1_RES   0x03000000U

RES[2:0] bits (Resolution)

#define ADC_CR1_RES_0   0x01000000U

Bit 0

#define ADC_CR1_RES_1   0x02000000U

Bit 1

#define ADC_CR1_SCAN   0x00000100U

Scan mode

#define ADC_CR2_ADON   0x00000001U

A/D Converter ON / OFF

#define ADC_CR2_ALIGN   0x00000800U

Data Alignment

#define ADC_CR2_CONT   0x00000002U

Continuous Conversion

#define ADC_CR2_DDS   0x00000200U

DMA disable selection (Single ADC)

#define ADC_CR2_DMA   0x00000100U

Direct Memory access mode

#define ADC_CR2_EOCS   0x00000400U

End of conversion selection

#define ADC_CR2_EXTEN   0x30000000U

EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp)

#define ADC_CR2_EXTEN_0   0x10000000U

Bit 0

#define ADC_CR2_EXTEN_1   0x20000000U

Bit 1

#define ADC_CR2_EXTSEL   0x0F000000U

EXTSEL[3:0] bits (External Event Select for regular group)

#define ADC_CR2_EXTSEL_0   0x01000000U

Bit 0

#define ADC_CR2_EXTSEL_1   0x02000000U

Bit 1

#define ADC_CR2_EXTSEL_2   0x04000000U

Bit 2

#define ADC_CR2_EXTSEL_3   0x08000000U

Bit 3

#define ADC_CR2_JEXTEN   0x00300000U

JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp)

#define ADC_CR2_JEXTEN_0   0x00100000U

Bit 0

#define ADC_CR2_JEXTEN_1   0x00200000U

Bit 1

#define ADC_CR2_JEXTSEL   0x000F0000U

JEXTSEL[3:0] bits (External event select for injected group)

#define ADC_CR2_JEXTSEL_0   0x00010000U

Bit 0

#define ADC_CR2_JEXTSEL_1   0x00020000U

Bit 1

#define ADC_CR2_JEXTSEL_2   0x00040000U

Bit 2

#define ADC_CR2_JEXTSEL_3   0x00080000U

Bit 3

#define ADC_CR2_JSWSTART   0x00400000U

Start Conversion of injected channels

#define ADC_CR2_SWSTART   0x40000000U

Start Conversion of regular channels

#define ADC_CSR_AWD1   0x00000001U

ADC1 Analog watchdog flag

#define ADC_CSR_AWD2   0x00000100U

ADC2 Analog watchdog flag

#define ADC_CSR_AWD3   0x00010000U

ADC3 Analog watchdog flag

#define ADC_CSR_DOVR1   ADC_CSR_OVR1
#define ADC_CSR_DOVR2   ADC_CSR_OVR2
#define ADC_CSR_DOVR3   ADC_CSR_OVR3
#define ADC_CSR_EOC1   0x00000002U

ADC1 End of conversion

#define ADC_CSR_EOC2   0x00000200U

ADC2 End of conversion

#define ADC_CSR_EOC3   0x00020000U

ADC3 End of conversion

#define ADC_CSR_JEOC1   0x00000004U

ADC1 Injected channel end of conversion

#define ADC_CSR_JEOC2   0x00000400U

ADC2 Injected channel end of conversion

#define ADC_CSR_JEOC3   0x00040000U

ADC3 Injected channel end of conversion

#define ADC_CSR_JSTRT1   0x00000008U

ADC1 Injected channel Start flag

#define ADC_CSR_JSTRT2   0x00000800U

ADC2 Injected channel Start flag

#define ADC_CSR_JSTRT3   0x00080000U

ADC3 Injected channel Start flag

#define ADC_CSR_OVR1   0x00000020U

ADC1 Overrun flag

#define ADC_CSR_OVR2   0x00002000U

ADC2 Overrun flag

#define ADC_CSR_OVR3   0x00200000U

ADC3 Overrun flag

#define ADC_CSR_STRT1   0x00000010U

ADC1 Regular channel Start flag

#define ADC_CSR_STRT2   0x00001000U

ADC2 Regular channel Start flag

#define ADC_CSR_STRT3   0x00100000U

ADC3 Regular channel Start flag

#define ADC_DR_ADC2DATA   0xFFFF0000U

ADC2 data

#define ADC_DR_DATA   0x0000FFFFU

Regular data

#define ADC_HTR_HT   0x0FFFU

Analog watchdog high threshold

#define ADC_JDR1_JDATA   ((uint16_t)0xFFFFU)

Injected data

#define ADC_JDR2_JDATA   ((uint16_t)0xFFFFU)

Injected data

#define ADC_JDR3_JDATA   ((uint16_t)0xFFFFU)

Injected data

#define ADC_JDR4_JDATA   ((uint16_t)0xFFFFU)

Injected data

#define ADC_JOFR1_JOFFSET1   0x0FFFU

Data offset for injected channel 1

#define ADC_JOFR2_JOFFSET2   0x0FFFU

Data offset for injected channel 2

#define ADC_JOFR3_JOFFSET3   0x0FFFU

Data offset for injected channel 3

#define ADC_JOFR4_JOFFSET4   0x0FFFU

Data offset for injected channel 4

#define ADC_JSQR_JL   0x00300000U

JL[1:0] bits (Injected Sequence length)

#define ADC_JSQR_JL_0   0x00100000U

Bit 0

#define ADC_JSQR_JL_1   0x00200000U

Bit 1

#define ADC_JSQR_JSQ1   0x0000001FU

JSQ1[4:0] bits (1st conversion in injected sequence)

#define ADC_JSQR_JSQ1_0   0x00000001U

Bit 0

#define ADC_JSQR_JSQ1_1   0x00000002U

Bit 1

#define ADC_JSQR_JSQ1_2   0x00000004U

Bit 2

#define ADC_JSQR_JSQ1_3   0x00000008U

Bit 3

#define ADC_JSQR_JSQ1_4   0x00000010U

Bit 4

#define ADC_JSQR_JSQ2   0x000003E0U

JSQ2[4:0] bits (2nd conversion in injected sequence)

#define ADC_JSQR_JSQ2_0   0x00000020U

Bit 0

#define ADC_JSQR_JSQ2_1   0x00000040U

Bit 1

#define ADC_JSQR_JSQ2_2   0x00000080U

Bit 2

#define ADC_JSQR_JSQ2_3   0x00000100U

Bit 3

#define ADC_JSQR_JSQ2_4   0x00000200U

Bit 4

#define ADC_JSQR_JSQ3   0x00007C00U

JSQ3[4:0] bits (3rd conversion in injected sequence)

#define ADC_JSQR_JSQ3_0   0x00000400U

Bit 0

#define ADC_JSQR_JSQ3_1   0x00000800U

Bit 1

#define ADC_JSQR_JSQ3_2   0x00001000U

Bit 2

#define ADC_JSQR_JSQ3_3   0x00002000U

Bit 3

#define ADC_JSQR_JSQ3_4   0x00004000U

Bit 4

#define ADC_JSQR_JSQ4   0x000F8000U

JSQ4[4:0] bits (4th conversion in injected sequence)

#define ADC_JSQR_JSQ4_0   0x00008000U

Bit 0

#define ADC_JSQR_JSQ4_1   0x00010000U

Bit 1

#define ADC_JSQR_JSQ4_2   0x00020000U

Bit 2

#define ADC_JSQR_JSQ4_3   0x00040000U

Bit 3

#define ADC_JSQR_JSQ4_4   0x00080000U

Bit 4

#define ADC_LTR_LT   0x0FFFU

Analog watchdog low threshold

#define ADC_SMPR1_SMP10   0x00000007U

SMP10[2:0] bits (Channel 10 Sample time selection)

#define ADC_SMPR1_SMP10_0   0x00000001U

Bit 0

#define ADC_SMPR1_SMP10_1   0x00000002U

Bit 1

#define ADC_SMPR1_SMP10_2   0x00000004U

Bit 2

#define ADC_SMPR1_SMP11   0x00000038U

SMP11[2:0] bits (Channel 11 Sample time selection)

#define ADC_SMPR1_SMP11_0   0x00000008U

Bit 0

#define ADC_SMPR1_SMP11_1   0x00000010U

Bit 1

#define ADC_SMPR1_SMP11_2   0x00000020U

Bit 2

#define ADC_SMPR1_SMP12   0x000001C0U

SMP12[2:0] bits (Channel 12 Sample time selection)

#define ADC_SMPR1_SMP12_0   0x00000040U

Bit 0

#define ADC_SMPR1_SMP12_1   0x00000080U

Bit 1

#define ADC_SMPR1_SMP12_2   0x00000100U

Bit 2

#define ADC_SMPR1_SMP13   0x00000E00U

SMP13[2:0] bits (Channel 13 Sample time selection)

#define ADC_SMPR1_SMP13_0   0x00000200U

Bit 0

#define ADC_SMPR1_SMP13_1   0x00000400U

Bit 1

#define ADC_SMPR1_SMP13_2   0x00000800U

Bit 2

#define ADC_SMPR1_SMP14   0x00007000U

SMP14[2:0] bits (Channel 14 Sample time selection)

#define ADC_SMPR1_SMP14_0   0x00001000U

Bit 0

#define ADC_SMPR1_SMP14_1   0x00002000U

Bit 1

#define ADC_SMPR1_SMP14_2   0x00004000U

Bit 2

#define ADC_SMPR1_SMP15   0x00038000U

SMP15[2:0] bits (Channel 15 Sample time selection)

#define ADC_SMPR1_SMP15_0   0x00008000U

Bit 0

#define ADC_SMPR1_SMP15_1   0x00010000U

Bit 1

#define ADC_SMPR1_SMP15_2   0x00020000U

Bit 2

#define ADC_SMPR1_SMP16   0x001C0000U

SMP16[2:0] bits (Channel 16 Sample time selection)

#define ADC_SMPR1_SMP16_0   0x00040000U

Bit 0

#define ADC_SMPR1_SMP16_1   0x00080000U

Bit 1

#define ADC_SMPR1_SMP16_2   0x00100000U

Bit 2

#define ADC_SMPR1_SMP17   0x00E00000U

SMP17[2:0] bits (Channel 17 Sample time selection)

#define ADC_SMPR1_SMP17_0   0x00200000U

Bit 0

#define ADC_SMPR1_SMP17_1   0x00400000U

Bit 1

#define ADC_SMPR1_SMP17_2   0x00800000U

Bit 2

#define ADC_SMPR1_SMP18   0x07000000U

SMP18[2:0] bits (Channel 18 Sample time selection)

#define ADC_SMPR1_SMP18_0   0x01000000U

Bit 0

#define ADC_SMPR1_SMP18_1   0x02000000U

Bit 1

#define ADC_SMPR1_SMP18_2   0x04000000U

Bit 2

#define ADC_SMPR2_SMP0   0x00000007U

SMP0[2:0] bits (Channel 0 Sample time selection)

#define ADC_SMPR2_SMP0_0   0x00000001U

Bit 0

#define ADC_SMPR2_SMP0_1   0x00000002U

Bit 1

#define ADC_SMPR2_SMP0_2   0x00000004U

Bit 2

#define ADC_SMPR2_SMP1   0x00000038U

SMP1[2:0] bits (Channel 1 Sample time selection)

#define ADC_SMPR2_SMP1_0   0x00000008U

Bit 0

#define ADC_SMPR2_SMP1_1   0x00000010U

Bit 1

#define ADC_SMPR2_SMP1_2   0x00000020U

Bit 2

#define ADC_SMPR2_SMP2   0x000001C0U

SMP2[2:0] bits (Channel 2 Sample time selection)

#define ADC_SMPR2_SMP2_0   0x00000040U

Bit 0

#define ADC_SMPR2_SMP2_1   0x00000080U

Bit 1

#define ADC_SMPR2_SMP2_2   0x00000100U

Bit 2

#define ADC_SMPR2_SMP3   0x00000E00U

SMP3[2:0] bits (Channel 3 Sample time selection)

#define ADC_SMPR2_SMP3_0   0x00000200U

Bit 0

#define ADC_SMPR2_SMP3_1   0x00000400U

Bit 1

#define ADC_SMPR2_SMP3_2   0x00000800U

Bit 2

#define ADC_SMPR2_SMP4   0x00007000U

SMP4[2:0] bits (Channel 4 Sample time selection)

#define ADC_SMPR2_SMP4_0   0x00001000U

Bit 0

#define ADC_SMPR2_SMP4_1   0x00002000U

Bit 1

#define ADC_SMPR2_SMP4_2   0x00004000U

Bit 2

#define ADC_SMPR2_SMP5   0x00038000U

SMP5[2:0] bits (Channel 5 Sample time selection)

#define ADC_SMPR2_SMP5_0   0x00008000U

Bit 0

#define ADC_SMPR2_SMP5_1   0x00010000U

Bit 1

#define ADC_SMPR2_SMP5_2   0x00020000U

Bit 2

#define ADC_SMPR2_SMP6   0x001C0000U

SMP6[2:0] bits (Channel 6 Sample time selection)

#define ADC_SMPR2_SMP6_0   0x00040000U

Bit 0

#define ADC_SMPR2_SMP6_1   0x00080000U

Bit 1

#define ADC_SMPR2_SMP6_2   0x00100000U

Bit 2

#define ADC_SMPR2_SMP7   0x00E00000U

SMP7[2:0] bits (Channel 7 Sample time selection)

#define ADC_SMPR2_SMP7_0   0x00200000U

Bit 0

#define ADC_SMPR2_SMP7_1   0x00400000U

Bit 1

#define ADC_SMPR2_SMP7_2   0x00800000U

Bit 2

#define ADC_SMPR2_SMP8   0x07000000U

SMP8[2:0] bits (Channel 8 Sample time selection)

#define ADC_SMPR2_SMP8_0   0x01000000U

Bit 0

#define ADC_SMPR2_SMP8_1   0x02000000U

Bit 1

#define ADC_SMPR2_SMP8_2   0x04000000U

Bit 2

#define ADC_SMPR2_SMP9   0x38000000U

SMP9[2:0] bits (Channel 9 Sample time selection)

#define ADC_SMPR2_SMP9_0   0x08000000U

Bit 0

#define ADC_SMPR2_SMP9_1   0x10000000U

Bit 1

#define ADC_SMPR2_SMP9_2   0x20000000U

Bit 2

#define ADC_SQR1_L   0x00F00000U

L[3:0] bits (Regular channel sequence length)

#define ADC_SQR1_L_0   0x00100000U

Bit 0

#define ADC_SQR1_L_1   0x00200000U

Bit 1

#define ADC_SQR1_L_2   0x00400000U

Bit 2

#define ADC_SQR1_L_3   0x00800000U

Bit 3

#define ADC_SQR1_SQ13   0x0000001FU

SQ13[4:0] bits (13th conversion in regular sequence)

#define ADC_SQR1_SQ13_0   0x00000001U

Bit 0

#define ADC_SQR1_SQ13_1   0x00000002U

Bit 1

#define ADC_SQR1_SQ13_2   0x00000004U

Bit 2

#define ADC_SQR1_SQ13_3   0x00000008U

Bit 3

#define ADC_SQR1_SQ13_4   0x00000010U

Bit 4

#define ADC_SQR1_SQ14   0x000003E0U

SQ14[4:0] bits (14th conversion in regular sequence)

#define ADC_SQR1_SQ14_0   0x00000020U

Bit 0

#define ADC_SQR1_SQ14_1   0x00000040U

Bit 1

#define ADC_SQR1_SQ14_2   0x00000080U

Bit 2

#define ADC_SQR1_SQ14_3   0x00000100U

Bit 3

#define ADC_SQR1_SQ14_4   0x00000200U

Bit 4

#define ADC_SQR1_SQ15   0x00007C00U

SQ15[4:0] bits (15th conversion in regular sequence)

#define ADC_SQR1_SQ15_0   0x00000400U

Bit 0

#define ADC_SQR1_SQ15_1   0x00000800U

Bit 1

#define ADC_SQR1_SQ15_2   0x00001000U

Bit 2

#define ADC_SQR1_SQ15_3   0x00002000U

Bit 3

#define ADC_SQR1_SQ15_4   0x00004000U

Bit 4

#define ADC_SQR1_SQ16   0x000F8000U

SQ16[4:0] bits (16th conversion in regular sequence)

#define ADC_SQR1_SQ16_0   0x00008000U

Bit 0

#define ADC_SQR1_SQ16_1   0x00010000U

Bit 1

#define ADC_SQR1_SQ16_2   0x00020000U

Bit 2

#define ADC_SQR1_SQ16_3   0x00040000U

Bit 3

#define ADC_SQR1_SQ16_4   0x00080000U

Bit 4

#define ADC_SQR2_SQ10   0x000F8000U

SQ10[4:0] bits (10th conversion in regular sequence)

#define ADC_SQR2_SQ10_0   0x00008000U

Bit 0

#define ADC_SQR2_SQ10_1   0x00010000U

Bit 1

#define ADC_SQR2_SQ10_2   0x00020000U

Bit 2

#define ADC_SQR2_SQ10_3   0x00040000U

Bit 3

#define ADC_SQR2_SQ10_4   0x00080000U

Bit 4

#define ADC_SQR2_SQ11   0x01F00000U

SQ11[4:0] bits (11th conversion in regular sequence)

#define ADC_SQR2_SQ11_0   0x00100000U

Bit 0

#define ADC_SQR2_SQ11_1   0x00200000U

Bit 1

#define ADC_SQR2_SQ11_2   0x00400000U

Bit 2

#define ADC_SQR2_SQ11_3   0x00800000U

Bit 3

#define ADC_SQR2_SQ11_4   0x01000000U

Bit 4

#define ADC_SQR2_SQ12   0x3E000000U

SQ12[4:0] bits (12th conversion in regular sequence)

#define ADC_SQR2_SQ12_0   0x02000000U

Bit 0

#define ADC_SQR2_SQ12_1   0x04000000U

Bit 1

#define ADC_SQR2_SQ12_2   0x08000000U

Bit 2

#define ADC_SQR2_SQ12_3   0x10000000U

Bit 3

#define ADC_SQR2_SQ12_4   0x20000000U

Bit 4

#define ADC_SQR2_SQ7   0x0000001FU

SQ7[4:0] bits (7th conversion in regular sequence)

#define ADC_SQR2_SQ7_0   0x00000001U

Bit 0

#define ADC_SQR2_SQ7_1   0x00000002U

Bit 1

#define ADC_SQR2_SQ7_2   0x00000004U

Bit 2

#define ADC_SQR2_SQ7_3   0x00000008U

Bit 3

#define ADC_SQR2_SQ7_4   0x00000010U

Bit 4

#define ADC_SQR2_SQ8   0x000003E0U

SQ8[4:0] bits (8th conversion in regular sequence)

#define ADC_SQR2_SQ8_0   0x00000020U

Bit 0

#define ADC_SQR2_SQ8_1   0x00000040U

Bit 1

#define ADC_SQR2_SQ8_2   0x00000080U

Bit 2

#define ADC_SQR2_SQ8_3   0x00000100U

Bit 3

#define ADC_SQR2_SQ8_4   0x00000200U

Bit 4

#define ADC_SQR2_SQ9   0x00007C00U

SQ9[4:0] bits (9th conversion in regular sequence)

#define ADC_SQR2_SQ9_0   0x00000400U

Bit 0

#define ADC_SQR2_SQ9_1   0x00000800U

Bit 1

#define ADC_SQR2_SQ9_2   0x00001000U

Bit 2

#define ADC_SQR2_SQ9_3   0x00002000U

Bit 3

#define ADC_SQR2_SQ9_4   0x00004000U

Bit 4

#define ADC_SQR3_SQ1   0x0000001FU

SQ1[4:0] bits (1st conversion in regular sequence)

#define ADC_SQR3_SQ1_0   0x00000001U

Bit 0

#define ADC_SQR3_SQ1_1   0x00000002U

Bit 1

#define ADC_SQR3_SQ1_2   0x00000004U

Bit 2

#define ADC_SQR3_SQ1_3   0x00000008U

Bit 3

#define ADC_SQR3_SQ1_4   0x00000010U

Bit 4

#define ADC_SQR3_SQ2   0x000003E0U

SQ2[4:0] bits (2nd conversion in regular sequence)

#define ADC_SQR3_SQ2_0   0x00000020U

Bit 0

#define ADC_SQR3_SQ2_1   0x00000040U

Bit 1

#define ADC_SQR3_SQ2_2   0x00000080U

Bit 2

#define ADC_SQR3_SQ2_3   0x00000100U

Bit 3

#define ADC_SQR3_SQ2_4   0x00000200U

Bit 4

#define ADC_SQR3_SQ3   0x00007C00U

SQ3[4:0] bits (3rd conversion in regular sequence)

#define ADC_SQR3_SQ3_0   0x00000400U

Bit 0

#define ADC_SQR3_SQ3_1   0x00000800U

Bit 1

#define ADC_SQR3_SQ3_2   0x00001000U

Bit 2

#define ADC_SQR3_SQ3_3   0x00002000U

Bit 3

#define ADC_SQR3_SQ3_4   0x00004000U

Bit 4

#define ADC_SQR3_SQ4   0x000F8000U

SQ4[4:0] bits (4th conversion in regular sequence)

#define ADC_SQR3_SQ4_0   0x00008000U

Bit 0

#define ADC_SQR3_SQ4_1   0x00010000U

Bit 1

#define ADC_SQR3_SQ4_2   0x00020000U

Bit 2

#define ADC_SQR3_SQ4_3   0x00040000U

Bit 3

#define ADC_SQR3_SQ4_4   0x00080000U

Bit 4

#define ADC_SQR3_SQ5   0x01F00000U

SQ5[4:0] bits (5th conversion in regular sequence)

#define ADC_SQR3_SQ5_0   0x00100000U

Bit 0

#define ADC_SQR3_SQ5_1   0x00200000U

Bit 1

#define ADC_SQR3_SQ5_2   0x00400000U

Bit 2

#define ADC_SQR3_SQ5_3   0x00800000U

Bit 3

#define ADC_SQR3_SQ5_4   0x01000000U

Bit 4

#define ADC_SQR3_SQ6   0x3E000000U

SQ6[4:0] bits (6th conversion in regular sequence)

#define ADC_SQR3_SQ6_0   0x02000000U

Bit 0

#define ADC_SQR3_SQ6_1   0x04000000U

Bit 1

#define ADC_SQR3_SQ6_2   0x08000000U

Bit 2

#define ADC_SQR3_SQ6_3   0x10000000U

Bit 3

#define ADC_SQR3_SQ6_4   0x20000000U

Bit 4

#define ADC_SR_AWD   0x00000001U

Analog watchdog flag

#define ADC_SR_EOC   0x00000002U

End of conversion

#define ADC_SR_JEOC   0x00000004U

Injected channel end of conversion

#define ADC_SR_JSTRT   0x00000008U

Injected channel Start flag

#define ADC_SR_OVR   0x00000020U

Overrun flag

#define ADC_SR_STRT   0x00000010U

Regular channel Start flag

#define CAN_BTR_BRP   0x000003FFU

Baud Rate Prescaler

#define CAN_BTR_LBKM   0x40000000U

Loop Back Mode (Debug)

#define CAN_BTR_SILM   0x80000000U

Silent Mode Mailbox registers

#define CAN_BTR_SJW   0x03000000U

Resynchronization Jump Width

#define CAN_BTR_SJW_0   0x01000000U

Bit 0

#define CAN_BTR_SJW_1   0x02000000U

Bit 1

#define CAN_BTR_TS1   0x000F0000U

Time Segment 1

#define CAN_BTR_TS1_0   0x00010000U

Bit 0

#define CAN_BTR_TS1_1   0x00020000U

Bit 1

#define CAN_BTR_TS1_2   0x00040000U

Bit 2

#define CAN_BTR_TS1_3   0x00080000U

Bit 3

#define CAN_BTR_TS2   0x00700000U

Time Segment 2

#define CAN_BTR_TS2_0   0x00100000U

Bit 0

#define CAN_BTR_TS2_1   0x00200000U

Bit 1

#define CAN_BTR_TS2_2   0x00400000U

Bit 2

#define CAN_ESR_BOFF   0x00000004U

Bus-Off Flag

#define CAN_ESR_EPVF   0x00000002U

Error Passive Flag

#define CAN_ESR_EWGF   0x00000001U

Error Warning Flag

#define CAN_ESR_LEC   0x00000070U

LEC[2:0] bits (Last Error Code)

#define CAN_ESR_LEC_0   0x00000010U

Bit 0

#define CAN_ESR_LEC_1   0x00000020U

Bit 1

#define CAN_ESR_LEC_2   0x00000040U

Bit 2

#define CAN_ESR_REC   0xFF000000U

Receive Error Counter

#define CAN_ESR_TEC   0x00FF0000U

Least significant byte of the 9-bit Transmit Error Counter

#define CAN_F0R1_FB0   0x00000001U

Filter bit 0

#define CAN_F0R1_FB1   0x00000002U

Filter bit 1

#define CAN_F0R1_FB10   0x00000400U

Filter bit 10

#define CAN_F0R1_FB11   0x00000800U

Filter bit 11

#define CAN_F0R1_FB12   0x00001000U

Filter bit 12

#define CAN_F0R1_FB13   0x00002000U

Filter bit 13

#define CAN_F0R1_FB14   0x00004000U

Filter bit 14

#define CAN_F0R1_FB15   0x00008000U

Filter bit 15

#define CAN_F0R1_FB16   0x00010000U

Filter bit 16

#define CAN_F0R1_FB17   0x00020000U

Filter bit 17

#define CAN_F0R1_FB18   0x00040000U

Filter bit 18

#define CAN_F0R1_FB19   0x00080000U

Filter bit 19

#define CAN_F0R1_FB2   0x00000004U

Filter bit 2

#define CAN_F0R1_FB20   0x00100000U

Filter bit 20

#define CAN_F0R1_FB21   0x00200000U

Filter bit 21

#define CAN_F0R1_FB22   0x00400000U

Filter bit 22

#define CAN_F0R1_FB23   0x00800000U

Filter bit 23

#define CAN_F0R1_FB24   0x01000000U

Filter bit 24

#define CAN_F0R1_FB25   0x02000000U

Filter bit 25

#define CAN_F0R1_FB26   0x04000000U

Filter bit 26

#define CAN_F0R1_FB27   0x08000000U

Filter bit 27

#define CAN_F0R1_FB28   0x10000000U

Filter bit 28

#define CAN_F0R1_FB29   0x20000000U

Filter bit 29

#define CAN_F0R1_FB3   0x00000008U

Filter bit 3

#define CAN_F0R1_FB30   0x40000000U

Filter bit 30

#define CAN_F0R1_FB31   0x80000000U

Filter bit 31

#define CAN_F0R1_FB4   0x00000010U

Filter bit 4

#define CAN_F0R1_FB5   0x00000020U

Filter bit 5

#define CAN_F0R1_FB6   0x00000040U

Filter bit 6

#define CAN_F0R1_FB7   0x00000080U

Filter bit 7

#define CAN_F0R1_FB8   0x00000100U

Filter bit 8

#define CAN_F0R1_FB9   0x00000200U

Filter bit 9

#define CAN_F0R2_FB0   0x00000001U

Filter bit 0

#define CAN_F0R2_FB1   0x00000002U

Filter bit 1

#define CAN_F0R2_FB10   0x00000400U

Filter bit 10

#define CAN_F0R2_FB11   0x00000800U

Filter bit 11

#define CAN_F0R2_FB12   0x00001000U

Filter bit 12

#define CAN_F0R2_FB13   0x00002000U

Filter bit 13

#define CAN_F0R2_FB14   0x00004000U

Filter bit 14

#define CAN_F0R2_FB15   0x00008000U

Filter bit 15

#define CAN_F0R2_FB16   0x00010000U

Filter bit 16

#define CAN_F0R2_FB17   0x00020000U

Filter bit 17

#define CAN_F0R2_FB18   0x00040000U

Filter bit 18

#define CAN_F0R2_FB19   0x00080000U

Filter bit 19

#define CAN_F0R2_FB2   0x00000004U

Filter bit 2

#define CAN_F0R2_FB20   0x00100000U

Filter bit 20

#define CAN_F0R2_FB21   0x00200000U

Filter bit 21

#define CAN_F0R2_FB22   0x00400000U

Filter bit 22

#define CAN_F0R2_FB23   0x00800000U

Filter bit 23

#define CAN_F0R2_FB24   0x01000000U

Filter bit 24

#define CAN_F0R2_FB25   0x02000000U

Filter bit 25

#define CAN_F0R2_FB26   0x04000000U

Filter bit 26

#define CAN_F0R2_FB27   0x08000000U

Filter bit 27

#define CAN_F0R2_FB28   0x10000000U

Filter bit 28

#define CAN_F0R2_FB29   0x20000000U

Filter bit 29

#define CAN_F0R2_FB3   0x00000008U

Filter bit 3

#define CAN_F0R2_FB30   0x40000000U

Filter bit 30

#define CAN_F0R2_FB31   0x80000000U

Filter bit 31

#define CAN_F0R2_FB4   0x00000010U

Filter bit 4

#define CAN_F0R2_FB5   0x00000020U

Filter bit 5

#define CAN_F0R2_FB6   0x00000040U

Filter bit 6

#define CAN_F0R2_FB7   0x00000080U

Filter bit 7

#define CAN_F0R2_FB8   0x00000100U

Filter bit 8

#define CAN_F0R2_FB9   0x00000200U

Filter bit 9

#define CAN_F10R1_FB0   0x00000001U

Filter bit 0

#define CAN_F10R1_FB1   0x00000002U

Filter bit 1

#define CAN_F10R1_FB10   0x00000400U

Filter bit 10

#define CAN_F10R1_FB11   0x00000800U

Filter bit 11

#define CAN_F10R1_FB12   0x00001000U

Filter bit 12

#define CAN_F10R1_FB13   0x00002000U

Filter bit 13

#define CAN_F10R1_FB14   0x00004000U

Filter bit 14

#define CAN_F10R1_FB15   0x00008000U

Filter bit 15

#define CAN_F10R1_FB16   0x00010000U

Filter bit 16

#define CAN_F10R1_FB17   0x00020000U

Filter bit 17

#define CAN_F10R1_FB18   0x00040000U

Filter bit 18

#define CAN_F10R1_FB19   0x00080000U

Filter bit 19

#define CAN_F10R1_FB2   0x00000004U

Filter bit 2

#define CAN_F10R1_FB20   0x00100000U

Filter bit 20

#define CAN_F10R1_FB21   0x00200000U

Filter bit 21

#define CAN_F10R1_FB22   0x00400000U

Filter bit 22

#define CAN_F10R1_FB23   0x00800000U

Filter bit 23

#define CAN_F10R1_FB24   0x01000000U

Filter bit 24

#define CAN_F10R1_FB25   0x02000000U

Filter bit 25

#define CAN_F10R1_FB26   0x04000000U

Filter bit 26

#define CAN_F10R1_FB27   0x08000000U

Filter bit 27

#define CAN_F10R1_FB28   0x10000000U

Filter bit 28

#define CAN_F10R1_FB29   0x20000000U

Filter bit 29

#define CAN_F10R1_FB3   0x00000008U

Filter bit 3

#define CAN_F10R1_FB30   0x40000000U

Filter bit 30

#define CAN_F10R1_FB31   0x80000000U

Filter bit 31

#define CAN_F10R1_FB4   0x00000010U

Filter bit 4

#define CAN_F10R1_FB5   0x00000020U

Filter bit 5

#define CAN_F10R1_FB6   0x00000040U

Filter bit 6

#define CAN_F10R1_FB7   0x00000080U

Filter bit 7

#define CAN_F10R1_FB8   0x00000100U

Filter bit 8

#define CAN_F10R1_FB9   0x00000200U

Filter bit 9

#define CAN_F10R2_FB0   0x00000001U

Filter bit 0

#define CAN_F10R2_FB1   0x00000002U

Filter bit 1

#define CAN_F10R2_FB10   0x00000400U

Filter bit 10

#define CAN_F10R2_FB11   0x00000800U

Filter bit 11

#define CAN_F10R2_FB12   0x00001000U

Filter bit 12

#define CAN_F10R2_FB13   0x00002000U

Filter bit 13

#define CAN_F10R2_FB14   0x00004000U

Filter bit 14

#define CAN_F10R2_FB15   0x00008000U

Filter bit 15

#define CAN_F10R2_FB16   0x00010000U

Filter bit 16

#define CAN_F10R2_FB17   0x00020000U

Filter bit 17

#define CAN_F10R2_FB18   0x00040000U

Filter bit 18

#define CAN_F10R2_FB19   0x00080000U

Filter bit 19

#define CAN_F10R2_FB2   0x00000004U

Filter bit 2

#define CAN_F10R2_FB20   0x00100000U

Filter bit 20

#define CAN_F10R2_FB21   0x00200000U

Filter bit 21

#define CAN_F10R2_FB22   0x00400000U

Filter bit 22

#define CAN_F10R2_FB23   0x00800000U

Filter bit 23

#define CAN_F10R2_FB24   0x01000000U

Filter bit 24

#define CAN_F10R2_FB25   0x02000000U

Filter bit 25

#define CAN_F10R2_FB26   0x04000000U

Filter bit 26

#define CAN_F10R2_FB27   0x08000000U

Filter bit 27

#define CAN_F10R2_FB28   0x10000000U

Filter bit 28

#define CAN_F10R2_FB29   0x20000000U

Filter bit 29

#define CAN_F10R2_FB3   0x00000008U

Filter bit 3

#define CAN_F10R2_FB30   0x40000000U

Filter bit 30

#define CAN_F10R2_FB31   0x80000000U

Filter bit 31

#define CAN_F10R2_FB4   0x00000010U

Filter bit 4

#define CAN_F10R2_FB5   0x00000020U

Filter bit 5

#define CAN_F10R2_FB6   0x00000040U

Filter bit 6

#define CAN_F10R2_FB7   0x00000080U

Filter bit 7

#define CAN_F10R2_FB8   0x00000100U

Filter bit 8

#define CAN_F10R2_FB9   0x00000200U

Filter bit 9

#define CAN_F11R1_FB0   0x00000001U

Filter bit 0

#define CAN_F11R1_FB1   0x00000002U

Filter bit 1

#define CAN_F11R1_FB10   0x00000400U

Filter bit 10

#define CAN_F11R1_FB11   0x00000800U

Filter bit 11

#define CAN_F11R1_FB12   0x00001000U

Filter bit 12

#define CAN_F11R1_FB13   0x00002000U

Filter bit 13

#define CAN_F11R1_FB14   0x00004000U

Filter bit 14

#define CAN_F11R1_FB15   0x00008000U

Filter bit 15

#define CAN_F11R1_FB16   0x00010000U

Filter bit 16

#define CAN_F11R1_FB17   0x00020000U

Filter bit 17

#define CAN_F11R1_FB18   0x00040000U

Filter bit 18

#define CAN_F11R1_FB19   0x00080000U

Filter bit 19

#define CAN_F11R1_FB2   0x00000004U

Filter bit 2

#define CAN_F11R1_FB20   0x00100000U

Filter bit 20

#define CAN_F11R1_FB21   0x00200000U

Filter bit 21

#define CAN_F11R1_FB22   0x00400000U

Filter bit 22

#define CAN_F11R1_FB23   0x00800000U

Filter bit 23

#define CAN_F11R1_FB24   0x01000000U

Filter bit 24

#define CAN_F11R1_FB25   0x02000000U

Filter bit 25

#define CAN_F11R1_FB26   0x04000000U

Filter bit 26

#define CAN_F11R1_FB27   0x08000000U

Filter bit 27

#define CAN_F11R1_FB28   0x10000000U

Filter bit 28

#define CAN_F11R1_FB29   0x20000000U

Filter bit 29

#define CAN_F11R1_FB3   0x00000008U

Filter bit 3

#define CAN_F11R1_FB30   0x40000000U

Filter bit 30

#define CAN_F11R1_FB31   0x80000000U

Filter bit 31

#define CAN_F11R1_FB4   0x00000010U

Filter bit 4

#define CAN_F11R1_FB5   0x00000020U

Filter bit 5

#define CAN_F11R1_FB6   0x00000040U

Filter bit 6

#define CAN_F11R1_FB7   0x00000080U

Filter bit 7

#define CAN_F11R1_FB8   0x00000100U

Filter bit 8

#define CAN_F11R1_FB9   0x00000200U

Filter bit 9

#define CAN_F11R2_FB0   0x00000001U

Filter bit 0

#define CAN_F11R2_FB1   0x00000002U

Filter bit 1

#define CAN_F11R2_FB10   0x00000400U

Filter bit 10

#define CAN_F11R2_FB11   0x00000800U

Filter bit 11

#define CAN_F11R2_FB12   0x00001000U

Filter bit 12

#define CAN_F11R2_FB13   0x00002000U

Filter bit 13

#define CAN_F11R2_FB14   0x00004000U

Filter bit 14

#define CAN_F11R2_FB15   0x00008000U

Filter bit 15

#define CAN_F11R2_FB16   0x00010000U

Filter bit 16

#define CAN_F11R2_FB17   0x00020000U

Filter bit 17

#define CAN_F11R2_FB18   0x00040000U

Filter bit 18

#define CAN_F11R2_FB19   0x00080000U

Filter bit 19

#define CAN_F11R2_FB2   0x00000004U

Filter bit 2

#define CAN_F11R2_FB20   0x00100000U

Filter bit 20

#define CAN_F11R2_FB21   0x00200000U

Filter bit 21

#define CAN_F11R2_FB22   0x00400000U

Filter bit 22

#define CAN_F11R2_FB23   0x00800000U

Filter bit 23

#define CAN_F11R2_FB24   0x01000000U

Filter bit 24

#define CAN_F11R2_FB25   0x02000000U

Filter bit 25

#define CAN_F11R2_FB26   0x04000000U

Filter bit 26

#define CAN_F11R2_FB27   0x08000000U

Filter bit 27

#define CAN_F11R2_FB28   0x10000000U

Filter bit 28

#define CAN_F11R2_FB29   0x20000000U

Filter bit 29

#define CAN_F11R2_FB3   0x00000008U

Filter bit 3

#define CAN_F11R2_FB30   0x40000000U

Filter bit 30

#define CAN_F11R2_FB31   0x80000000U

Filter bit 31

#define CAN_F11R2_FB4   0x00000010U

Filter bit 4

#define CAN_F11R2_FB5   0x00000020U

Filter bit 5

#define CAN_F11R2_FB6   0x00000040U

Filter bit 6

#define CAN_F11R2_FB7   0x00000080U

Filter bit 7

#define CAN_F11R2_FB8   0x00000100U

Filter bit 8

#define CAN_F11R2_FB9   0x00000200U

Filter bit 9

#define CAN_F12R1_FB0   0x00000001U

Filter bit 0

#define CAN_F12R1_FB1   0x00000002U

Filter bit 1

#define CAN_F12R1_FB10   0x00000400U

Filter bit 10

#define CAN_F12R1_FB11   0x00000800U

Filter bit 11

#define CAN_F12R1_FB12   0x00001000U

Filter bit 12

#define CAN_F12R1_FB13   0x00002000U

Filter bit 13

#define CAN_F12R1_FB14   0x00004000U

Filter bit 14

#define CAN_F12R1_FB15   0x00008000U

Filter bit 15

#define CAN_F12R1_FB16   0x00010000U

Filter bit 16

#define CAN_F12R1_FB17   0x00020000U

Filter bit 17

#define CAN_F12R1_FB18   0x00040000U

Filter bit 18

#define CAN_F12R1_FB19   0x00080000U

Filter bit 19

#define CAN_F12R1_FB2   0x00000004U

Filter bit 2

#define CAN_F12R1_FB20   0x00100000U

Filter bit 20

#define CAN_F12R1_FB21   0x00200000U

Filter bit 21

#define CAN_F12R1_FB22   0x00400000U

Filter bit 22

#define CAN_F12R1_FB23   0x00800000U

Filter bit 23

#define CAN_F12R1_FB24   0x01000000U

Filter bit 24

#define CAN_F12R1_FB25   0x02000000U

Filter bit 25

#define CAN_F12R1_FB26   0x04000000U

Filter bit 26

#define CAN_F12R1_FB27   0x08000000U

Filter bit 27

#define CAN_F12R1_FB28   0x10000000U

Filter bit 28

#define CAN_F12R1_FB29   0x20000000U

Filter bit 29

#define CAN_F12R1_FB3   0x00000008U

Filter bit 3

#define CAN_F12R1_FB30   0x40000000U

Filter bit 30

#define CAN_F12R1_FB31   0x80000000U

Filter bit 31

#define CAN_F12R1_FB4   0x00000010U

Filter bit 4

#define CAN_F12R1_FB5   0x00000020U

Filter bit 5

#define CAN_F12R1_FB6   0x00000040U

Filter bit 6

#define CAN_F12R1_FB7   0x00000080U

Filter bit 7

#define CAN_F12R1_FB8   0x00000100U

Filter bit 8

#define CAN_F12R1_FB9   0x00000200U

Filter bit 9

#define CAN_F12R2_FB0   0x00000001U

Filter bit 0

#define CAN_F12R2_FB1   0x00000002U

Filter bit 1

#define CAN_F12R2_FB10   0x00000400U

Filter bit 10

#define CAN_F12R2_FB11   0x00000800U

Filter bit 11

#define CAN_F12R2_FB12   0x00001000U

Filter bit 12

#define CAN_F12R2_FB13   0x00002000U

Filter bit 13

#define CAN_F12R2_FB14   0x00004000U

Filter bit 14

#define CAN_F12R2_FB15   0x00008000U

Filter bit 15

#define CAN_F12R2_FB16   0x00010000U

Filter bit 16

#define CAN_F12R2_FB17   0x00020000U

Filter bit 17

#define CAN_F12R2_FB18   0x00040000U

Filter bit 18

#define CAN_F12R2_FB19   0x00080000U

Filter bit 19

#define CAN_F12R2_FB2   0x00000004U

Filter bit 2

#define CAN_F12R2_FB20   0x00100000U

Filter bit 20

#define CAN_F12R2_FB21   0x00200000U

Filter bit 21

#define CAN_F12R2_FB22   0x00400000U

Filter bit 22

#define CAN_F12R2_FB23   0x00800000U

Filter bit 23

#define CAN_F12R2_FB24   0x01000000U

Filter bit 24

#define CAN_F12R2_FB25   0x02000000U

Filter bit 25

#define CAN_F12R2_FB26   0x04000000U

Filter bit 26

#define CAN_F12R2_FB27   0x08000000U

Filter bit 27

#define CAN_F12R2_FB28   0x10000000U

Filter bit 28

#define CAN_F12R2_FB29   0x20000000U

Filter bit 29

#define CAN_F12R2_FB3   0x00000008U

Filter bit 3

#define CAN_F12R2_FB30   0x40000000U

Filter bit 30

#define CAN_F12R2_FB31   0x80000000U

Filter bit 31

#define CAN_F12R2_FB4   0x00000010U

Filter bit 4

#define CAN_F12R2_FB5   0x00000020U

Filter bit 5

#define CAN_F12R2_FB6   0x00000040U

Filter bit 6

#define CAN_F12R2_FB7   0x00000080U

Filter bit 7

#define CAN_F12R2_FB8   0x00000100U

Filter bit 8

#define CAN_F12R2_FB9   0x00000200U

Filter bit 9

#define CAN_F13R1_FB0   0x00000001U

Filter bit 0

#define CAN_F13R1_FB1   0x00000002U

Filter bit 1

#define CAN_F13R1_FB10   0x00000400U

Filter bit 10

#define CAN_F13R1_FB11   0x00000800U

Filter bit 11

#define CAN_F13R1_FB12   0x00001000U

Filter bit 12

#define CAN_F13R1_FB13   0x00002000U

Filter bit 13

#define CAN_F13R1_FB14   0x00004000U

Filter bit 14

#define CAN_F13R1_FB15   0x00008000U

Filter bit 15

#define CAN_F13R1_FB16   0x00010000U

Filter bit 16

#define CAN_F13R1_FB17   0x00020000U

Filter bit 17

#define CAN_F13R1_FB18   0x00040000U

Filter bit 18

#define CAN_F13R1_FB19   0x00080000U

Filter bit 19

#define CAN_F13R1_FB2   0x00000004U

Filter bit 2

#define CAN_F13R1_FB20   0x00100000U

Filter bit 20

#define CAN_F13R1_FB21   0x00200000U

Filter bit 21

#define CAN_F13R1_FB22   0x00400000U

Filter bit 22

#define CAN_F13R1_FB23   0x00800000U

Filter bit 23

#define CAN_F13R1_FB24   0x01000000U

Filter bit 24

#define CAN_F13R1_FB25   0x02000000U

Filter bit 25

#define CAN_F13R1_FB26   0x04000000U

Filter bit 26

#define CAN_F13R1_FB27   0x08000000U

Filter bit 27

#define CAN_F13R1_FB28   0x10000000U

Filter bit 28

#define CAN_F13R1_FB29   0x20000000U

Filter bit 29

#define CAN_F13R1_FB3   0x00000008U

Filter bit 3

#define CAN_F13R1_FB30   0x40000000U

Filter bit 30

#define CAN_F13R1_FB31   0x80000000U

Filter bit 31

#define CAN_F13R1_FB4   0x00000010U

Filter bit 4

#define CAN_F13R1_FB5   0x00000020U

Filter bit 5

#define CAN_F13R1_FB6   0x00000040U

Filter bit 6

#define CAN_F13R1_FB7   0x00000080U

Filter bit 7

#define CAN_F13R1_FB8   0x00000100U

Filter bit 8

#define CAN_F13R1_FB9   0x00000200U

Filter bit 9

#define CAN_F13R2_FB0   0x00000001U

Filter bit 0

#define CAN_F13R2_FB1   0x00000002U

Filter bit 1

#define CAN_F13R2_FB10   0x00000400U

Filter bit 10

#define CAN_F13R2_FB11   0x00000800U

Filter bit 11

#define CAN_F13R2_FB12   0x00001000U

Filter bit 12

#define CAN_F13R2_FB13   0x00002000U

Filter bit 13

#define CAN_F13R2_FB14   0x00004000U

Filter bit 14

#define CAN_F13R2_FB15   0x00008000U

Filter bit 15

#define CAN_F13R2_FB16   0x00010000U

Filter bit 16

#define CAN_F13R2_FB17   0x00020000U

Filter bit 17

#define CAN_F13R2_FB18   0x00040000U

Filter bit 18

#define CAN_F13R2_FB19   0x00080000U

Filter bit 19

#define CAN_F13R2_FB2   0x00000004U

Filter bit 2

#define CAN_F13R2_FB20   0x00100000U

Filter bit 20

#define CAN_F13R2_FB21   0x00200000U

Filter bit 21

#define CAN_F13R2_FB22   0x00400000U

Filter bit 22

#define CAN_F13R2_FB23   0x00800000U

Filter bit 23

#define CAN_F13R2_FB24   0x01000000U

Filter bit 24

#define CAN_F13R2_FB25   0x02000000U

Filter bit 25

#define CAN_F13R2_FB26   0x04000000U

Filter bit 26

#define CAN_F13R2_FB27   0x08000000U

Filter bit 27

#define CAN_F13R2_FB28   0x10000000U

Filter bit 28

#define CAN_F13R2_FB29   0x20000000U

Filter bit 29

#define CAN_F13R2_FB3   0x00000008U

Filter bit 3

#define CAN_F13R2_FB30   0x40000000U

Filter bit 30

#define CAN_F13R2_FB31   0x80000000U

Filter bit 31

#define CAN_F13R2_FB4   0x00000010U

Filter bit 4

#define CAN_F13R2_FB5   0x00000020U

Filter bit 5

#define CAN_F13R2_FB6   0x00000040U

Filter bit 6

#define CAN_F13R2_FB7   0x00000080U

Filter bit 7

#define CAN_F13R2_FB8   0x00000100U

Filter bit 8

#define CAN_F13R2_FB9   0x00000200U

Filter bit 9

#define CAN_F1R1_FB0   0x00000001U

Filter bit 0

#define CAN_F1R1_FB1   0x00000002U

Filter bit 1

#define CAN_F1R1_FB10   0x00000400U

Filter bit 10

#define CAN_F1R1_FB11   0x00000800U

Filter bit 11

#define CAN_F1R1_FB12   0x00001000U

Filter bit 12

#define CAN_F1R1_FB13   0x00002000U

Filter bit 13

#define CAN_F1R1_FB14   0x00004000U

Filter bit 14

#define CAN_F1R1_FB15   0x00008000U

Filter bit 15

#define CAN_F1R1_FB16   0x00010000U

Filter bit 16

#define CAN_F1R1_FB17   0x00020000U

Filter bit 17

#define CAN_F1R1_FB18   0x00040000U

Filter bit 18

#define CAN_F1R1_FB19   0x00080000U

Filter bit 19

#define CAN_F1R1_FB2   0x00000004U

Filter bit 2

#define CAN_F1R1_FB20   0x00100000U

Filter bit 20

#define CAN_F1R1_FB21   0x00200000U

Filter bit 21

#define CAN_F1R1_FB22   0x00400000U

Filter bit 22

#define CAN_F1R1_FB23   0x00800000U

Filter bit 23

#define CAN_F1R1_FB24   0x01000000U

Filter bit 24

#define CAN_F1R1_FB25   0x02000000U

Filter bit 25

#define CAN_F1R1_FB26   0x04000000U

Filter bit 26

#define CAN_F1R1_FB27   0x08000000U

Filter bit 27

#define CAN_F1R1_FB28   0x10000000U

Filter bit 28

#define CAN_F1R1_FB29   0x20000000U

Filter bit 29

#define CAN_F1R1_FB3   0x00000008U

Filter bit 3

#define CAN_F1R1_FB30   0x40000000U

Filter bit 30

#define CAN_F1R1_FB31   0x80000000U

Filter bit 31

#define CAN_F1R1_FB4   0x00000010U

Filter bit 4

#define CAN_F1R1_FB5   0x00000020U

Filter bit 5

#define CAN_F1R1_FB6   0x00000040U

Filter bit 6

#define CAN_F1R1_FB7   0x00000080U

Filter bit 7

#define CAN_F1R1_FB8   0x00000100U

Filter bit 8

#define CAN_F1R1_FB9   0x00000200U

Filter bit 9

#define CAN_F1R2_FB0   0x00000001U

Filter bit 0

#define CAN_F1R2_FB1   0x00000002U

Filter bit 1

#define CAN_F1R2_FB10   0x00000400U

Filter bit 10

#define CAN_F1R2_FB11   0x00000800U

Filter bit 11

#define CAN_F1R2_FB12   0x00001000U

Filter bit 12

#define CAN_F1R2_FB13   0x00002000U

Filter bit 13

#define CAN_F1R2_FB14   0x00004000U

Filter bit 14

#define CAN_F1R2_FB15   0x00008000U

Filter bit 15

#define CAN_F1R2_FB16   0x00010000U

Filter bit 16

#define CAN_F1R2_FB17   0x00020000U

Filter bit 17

#define CAN_F1R2_FB18   0x00040000U

Filter bit 18

#define CAN_F1R2_FB19   0x00080000U

Filter bit 19

#define CAN_F1R2_FB2   0x00000004U

Filter bit 2

#define CAN_F1R2_FB20   0x00100000U

Filter bit 20

#define CAN_F1R2_FB21   0x00200000U

Filter bit 21

#define CAN_F1R2_FB22   0x00400000U

Filter bit 22

#define CAN_F1R2_FB23   0x00800000U

Filter bit 23

#define CAN_F1R2_FB24   0x01000000U

Filter bit 24

#define CAN_F1R2_FB25   0x02000000U

Filter bit 25

#define CAN_F1R2_FB26   0x04000000U

Filter bit 26

#define CAN_F1R2_FB27   0x08000000U

Filter bit 27

#define CAN_F1R2_FB28   0x10000000U

Filter bit 28

#define CAN_F1R2_FB29   0x20000000U

Filter bit 29

#define CAN_F1R2_FB3   0x00000008U

Filter bit 3

#define CAN_F1R2_FB30   0x40000000U

Filter bit 30

#define CAN_F1R2_FB31   0x80000000U

Filter bit 31

#define CAN_F1R2_FB4   0x00000010U

Filter bit 4

#define CAN_F1R2_FB5   0x00000020U

Filter bit 5

#define CAN_F1R2_FB6   0x00000040U

Filter bit 6

#define CAN_F1R2_FB7   0x00000080U

Filter bit 7

#define CAN_F1R2_FB8   0x00000100U

Filter bit 8

#define CAN_F1R2_FB9   0x00000200U

Filter bit 9

#define CAN_F2R1_FB0   0x00000001U

Filter bit 0

#define CAN_F2R1_FB1   0x00000002U

Filter bit 1

#define CAN_F2R1_FB10   0x00000400U

Filter bit 10

#define CAN_F2R1_FB11   0x00000800U

Filter bit 11

#define CAN_F2R1_FB12   0x00001000U

Filter bit 12

#define CAN_F2R1_FB13   0x00002000U

Filter bit 13

#define CAN_F2R1_FB14   0x00004000U

Filter bit 14

#define CAN_F2R1_FB15   0x00008000U

Filter bit 15

#define CAN_F2R1_FB16   0x00010000U

Filter bit 16

#define CAN_F2R1_FB17   0x00020000U

Filter bit 17

#define CAN_F2R1_FB18   0x00040000U

Filter bit 18

#define CAN_F2R1_FB19   0x00080000U

Filter bit 19

#define CAN_F2R1_FB2   0x00000004U

Filter bit 2

#define CAN_F2R1_FB20   0x00100000U

Filter bit 20

#define CAN_F2R1_FB21   0x00200000U

Filter bit 21

#define CAN_F2R1_FB22   0x00400000U

Filter bit 22

#define CAN_F2R1_FB23   0x00800000U

Filter bit 23

#define CAN_F2R1_FB24   0x01000000U

Filter bit 24

#define CAN_F2R1_FB25   0x02000000U

Filter bit 25

#define CAN_F2R1_FB26   0x04000000U

Filter bit 26

#define CAN_F2R1_FB27   0x08000000U

Filter bit 27

#define CAN_F2R1_FB28   0x10000000U

Filter bit 28

#define CAN_F2R1_FB29   0x20000000U

Filter bit 29

#define CAN_F2R1_FB3   0x00000008U

Filter bit 3

#define CAN_F2R1_FB30   0x40000000U

Filter bit 30

#define CAN_F2R1_FB31   0x80000000U

Filter bit 31

#define CAN_F2R1_FB4   0x00000010U

Filter bit 4

#define CAN_F2R1_FB5   0x00000020U

Filter bit 5

#define CAN_F2R1_FB6   0x00000040U

Filter bit 6

#define CAN_F2R1_FB7   0x00000080U

Filter bit 7

#define CAN_F2R1_FB8   0x00000100U

Filter bit 8

#define CAN_F2R1_FB9   0x00000200U

Filter bit 9

#define CAN_F2R2_FB0   0x00000001U

Filter bit 0

#define CAN_F2R2_FB1   0x00000002U

Filter bit 1

#define CAN_F2R2_FB10   0x00000400U

Filter bit 10

#define CAN_F2R2_FB11   0x00000800U

Filter bit 11

#define CAN_F2R2_FB12   0x00001000U

Filter bit 12

#define CAN_F2R2_FB13   0x00002000U

Filter bit 13

#define CAN_F2R2_FB14   0x00004000U

Filter bit 14

#define CAN_F2R2_FB15   0x00008000U

Filter bit 15

#define CAN_F2R2_FB16   0x00010000U

Filter bit 16

#define CAN_F2R2_FB17   0x00020000U

Filter bit 17

#define CAN_F2R2_FB18   0x00040000U

Filter bit 18

#define CAN_F2R2_FB19   0x00080000U

Filter bit 19

#define CAN_F2R2_FB2   0x00000004U

Filter bit 2

#define CAN_F2R2_FB20   0x00100000U

Filter bit 20

#define CAN_F2R2_FB21   0x00200000U

Filter bit 21

#define CAN_F2R2_FB22   0x00400000U

Filter bit 22

#define CAN_F2R2_FB23   0x00800000U

Filter bit 23

#define CAN_F2R2_FB24   0x01000000U

Filter bit 24

#define CAN_F2R2_FB25   0x02000000U

Filter bit 25

#define CAN_F2R2_FB26   0x04000000U

Filter bit 26

#define CAN_F2R2_FB27   0x08000000U

Filter bit 27

#define CAN_F2R2_FB28   0x10000000U

Filter bit 28

#define CAN_F2R2_FB29   0x20000000U

Filter bit 29

#define CAN_F2R2_FB3   0x00000008U

Filter bit 3

#define CAN_F2R2_FB30   0x40000000U

Filter bit 30

#define CAN_F2R2_FB31   0x80000000U

Filter bit 31

#define CAN_F2R2_FB4   0x00000010U

Filter bit 4

#define CAN_F2R2_FB5   0x00000020U

Filter bit 5

#define CAN_F2R2_FB6   0x00000040U

Filter bit 6

#define CAN_F2R2_FB7   0x00000080U

Filter bit 7

#define CAN_F2R2_FB8   0x00000100U

Filter bit 8

#define CAN_F2R2_FB9   0x00000200U

Filter bit 9

#define CAN_F3R1_FB0   0x00000001U

Filter bit 0

#define CAN_F3R1_FB1   0x00000002U

Filter bit 1

#define CAN_F3R1_FB10   0x00000400U

Filter bit 10

#define CAN_F3R1_FB11   0x00000800U

Filter bit 11

#define CAN_F3R1_FB12   0x00001000U

Filter bit 12

#define CAN_F3R1_FB13   0x00002000U

Filter bit 13

#define CAN_F3R1_FB14   0x00004000U

Filter bit 14

#define CAN_F3R1_FB15   0x00008000U

Filter bit 15

#define CAN_F3R1_FB16   0x00010000U

Filter bit 16

#define CAN_F3R1_FB17   0x00020000U

Filter bit 17

#define CAN_F3R1_FB18   0x00040000U

Filter bit 18

#define CAN_F3R1_FB19   0x00080000U

Filter bit 19

#define CAN_F3R1_FB2   0x00000004U

Filter bit 2

#define CAN_F3R1_FB20   0x00100000U

Filter bit 20

#define CAN_F3R1_FB21   0x00200000U

Filter bit 21

#define CAN_F3R1_FB22   0x00400000U

Filter bit 22

#define CAN_F3R1_FB23   0x00800000U

Filter bit 23

#define CAN_F3R1_FB24   0x01000000U

Filter bit 24

#define CAN_F3R1_FB25   0x02000000U

Filter bit 25

#define CAN_F3R1_FB26   0x04000000U

Filter bit 26

#define CAN_F3R1_FB27   0x08000000U

Filter bit 27

#define CAN_F3R1_FB28   0x10000000U

Filter bit 28

#define CAN_F3R1_FB29   0x20000000U

Filter bit 29

#define CAN_F3R1_FB3   0x00000008U

Filter bit 3

#define CAN_F3R1_FB30   0x40000000U

Filter bit 30

#define CAN_F3R1_FB31   0x80000000U

Filter bit 31

#define CAN_F3R1_FB4   0x00000010U

Filter bit 4

#define CAN_F3R1_FB5   0x00000020U

Filter bit 5

#define CAN_F3R1_FB6   0x00000040U

Filter bit 6

#define CAN_F3R1_FB7   0x00000080U

Filter bit 7

#define CAN_F3R1_FB8   0x00000100U

Filter bit 8

#define CAN_F3R1_FB9   0x00000200U

Filter bit 9

#define CAN_F3R2_FB0   0x00000001U

Filter bit 0

#define CAN_F3R2_FB1   0x00000002U

Filter bit 1

#define CAN_F3R2_FB10   0x00000400U

Filter bit 10

#define CAN_F3R2_FB11   0x00000800U

Filter bit 11

#define CAN_F3R2_FB12   0x00001000U

Filter bit 12

#define CAN_F3R2_FB13   0x00002000U

Filter bit 13

#define CAN_F3R2_FB14   0x00004000U

Filter bit 14

#define CAN_F3R2_FB15   0x00008000U

Filter bit 15

#define CAN_F3R2_FB16   0x00010000U

Filter bit 16

#define CAN_F3R2_FB17   0x00020000U

Filter bit 17

#define CAN_F3R2_FB18   0x00040000U

Filter bit 18

#define CAN_F3R2_FB19   0x00080000U

Filter bit 19

#define CAN_F3R2_FB2   0x00000004U

Filter bit 2

#define CAN_F3R2_FB20   0x00100000U

Filter bit 20

#define CAN_F3R2_FB21   0x00200000U

Filter bit 21

#define CAN_F3R2_FB22   0x00400000U

Filter bit 22

#define CAN_F3R2_FB23   0x00800000U

Filter bit 23

#define CAN_F3R2_FB24   0x01000000U

Filter bit 24

#define CAN_F3R2_FB25   0x02000000U

Filter bit 25

#define CAN_F3R2_FB26   0x04000000U

Filter bit 26

#define CAN_F3R2_FB27   0x08000000U

Filter bit 27

#define CAN_F3R2_FB28   0x10000000U

Filter bit 28

#define CAN_F3R2_FB29   0x20000000U

Filter bit 29

#define CAN_F3R2_FB3   0x00000008U

Filter bit 3

#define CAN_F3R2_FB30   0x40000000U

Filter bit 30

#define CAN_F3R2_FB31   0x80000000U

Filter bit 31

#define CAN_F3R2_FB4   0x00000010U

Filter bit 4

#define CAN_F3R2_FB5   0x00000020U

Filter bit 5

#define CAN_F3R2_FB6   0x00000040U

Filter bit 6

#define CAN_F3R2_FB7   0x00000080U

Filter bit 7

#define CAN_F3R2_FB8   0x00000100U

Filter bit 8

#define CAN_F3R2_FB9   0x00000200U

Filter bit 9

#define CAN_F4R1_FB0   0x00000001U

Filter bit 0

#define CAN_F4R1_FB1   0x00000002U

Filter bit 1

#define CAN_F4R1_FB10   0x00000400U

Filter bit 10

#define CAN_F4R1_FB11   0x00000800U

Filter bit 11

#define CAN_F4R1_FB12   0x00001000U

Filter bit 12

#define CAN_F4R1_FB13   0x00002000U

Filter bit 13

#define CAN_F4R1_FB14   0x00004000U

Filter bit 14

#define CAN_F4R1_FB15   0x00008000U

Filter bit 15

#define CAN_F4R1_FB16   0x00010000U

Filter bit 16

#define CAN_F4R1_FB17   0x00020000U

Filter bit 17

#define CAN_F4R1_FB18   0x00040000U

Filter bit 18

#define CAN_F4R1_FB19   0x00080000U

Filter bit 19

#define CAN_F4R1_FB2   0x00000004U

Filter bit 2

#define CAN_F4R1_FB20   0x00100000U

Filter bit 20

#define CAN_F4R1_FB21   0x00200000U

Filter bit 21

#define CAN_F4R1_FB22   0x00400000U

Filter bit 22

#define CAN_F4R1_FB23   0x00800000U

Filter bit 23

#define CAN_F4R1_FB24   0x01000000U

Filter bit 24

#define CAN_F4R1_FB25   0x02000000U

Filter bit 25

#define CAN_F4R1_FB26   0x04000000U

Filter bit 26

#define CAN_F4R1_FB27   0x08000000U

Filter bit 27

#define CAN_F4R1_FB28   0x10000000U

Filter bit 28

#define CAN_F4R1_FB29   0x20000000U

Filter bit 29

#define CAN_F4R1_FB3   0x00000008U

Filter bit 3

#define CAN_F4R1_FB30   0x40000000U

Filter bit 30

#define CAN_F4R1_FB31   0x80000000U

Filter bit 31

#define CAN_F4R1_FB4   0x00000010U

Filter bit 4

#define CAN_F4R1_FB5   0x00000020U

Filter bit 5

#define CAN_F4R1_FB6   0x00000040U

Filter bit 6

#define CAN_F4R1_FB7   0x00000080U

Filter bit 7

#define CAN_F4R1_FB8   0x00000100U

Filter bit 8

#define CAN_F4R1_FB9   0x00000200U

Filter bit 9

#define CAN_F4R2_FB0   0x00000001U

Filter bit 0

#define CAN_F4R2_FB1   0x00000002U

Filter bit 1

#define CAN_F4R2_FB10   0x00000400U

Filter bit 10

#define CAN_F4R2_FB11   0x00000800U

Filter bit 11

#define CAN_F4R2_FB12   0x00001000U

Filter bit 12

#define CAN_F4R2_FB13   0x00002000U

Filter bit 13

#define CAN_F4R2_FB14   0x00004000U

Filter bit 14

#define CAN_F4R2_FB15   0x00008000U

Filter bit 15

#define CAN_F4R2_FB16   0x00010000U

Filter bit 16

#define CAN_F4R2_FB17   0x00020000U

Filter bit 17

#define CAN_F4R2_FB18   0x00040000U

Filter bit 18

#define CAN_F4R2_FB19   0x00080000U

Filter bit 19

#define CAN_F4R2_FB2   0x00000004U

Filter bit 2

#define CAN_F4R2_FB20   0x00100000U

Filter bit 20

#define CAN_F4R2_FB21   0x00200000U

Filter bit 21

#define CAN_F4R2_FB22   0x00400000U

Filter bit 22

#define CAN_F4R2_FB23   0x00800000U

Filter bit 23

#define CAN_F4R2_FB24   0x01000000U

Filter bit 24

#define CAN_F4R2_FB25   0x02000000U

Filter bit 25

#define CAN_F4R2_FB26   0x04000000U

Filter bit 26

#define CAN_F4R2_FB27   0x08000000U

Filter bit 27

#define CAN_F4R2_FB28   0x10000000U

Filter bit 28

#define CAN_F4R2_FB29   0x20000000U

Filter bit 29

#define CAN_F4R2_FB3   0x00000008U

Filter bit 3

#define CAN_F4R2_FB30   0x40000000U

Filter bit 30

#define CAN_F4R2_FB31   0x80000000U

Filter bit 31

#define CAN_F4R2_FB4   0x00000010U

Filter bit 4

#define CAN_F4R2_FB5   0x00000020U

Filter bit 5

#define CAN_F4R2_FB6   0x00000040U

Filter bit 6

#define CAN_F4R2_FB7   0x00000080U

Filter bit 7

#define CAN_F4R2_FB8   0x00000100U

Filter bit 8

#define CAN_F4R2_FB9   0x00000200U

Filter bit 9

#define CAN_F5R1_FB0   0x00000001U

Filter bit 0

#define CAN_F5R1_FB1   0x00000002U

Filter bit 1

#define CAN_F5R1_FB10   0x00000400U

Filter bit 10

#define CAN_F5R1_FB11   0x00000800U

Filter bit 11

#define CAN_F5R1_FB12   0x00001000U

Filter bit 12

#define CAN_F5R1_FB13   0x00002000U

Filter bit 13

#define CAN_F5R1_FB14   0x00004000U

Filter bit 14

#define CAN_F5R1_FB15   0x00008000U

Filter bit 15

#define CAN_F5R1_FB16   0x00010000U

Filter bit 16

#define CAN_F5R1_FB17   0x00020000U

Filter bit 17

#define CAN_F5R1_FB18   0x00040000U

Filter bit 18

#define CAN_F5R1_FB19   0x00080000U

Filter bit 19

#define CAN_F5R1_FB2   0x00000004U

Filter bit 2

#define CAN_F5R1_FB20   0x00100000U

Filter bit 20

#define CAN_F5R1_FB21   0x00200000U

Filter bit 21

#define CAN_F5R1_FB22   0x00400000U

Filter bit 22

#define CAN_F5R1_FB23   0x00800000U

Filter bit 23

#define CAN_F5R1_FB24   0x01000000U

Filter bit 24

#define CAN_F5R1_FB25   0x02000000U

Filter bit 25

#define CAN_F5R1_FB26   0x04000000U

Filter bit 26

#define CAN_F5R1_FB27   0x08000000U

Filter bit 27

#define CAN_F5R1_FB28   0x10000000U

Filter bit 28

#define CAN_F5R1_FB29   0x20000000U

Filter bit 29

#define CAN_F5R1_FB3   0x00000008U

Filter bit 3

#define CAN_F5R1_FB30   0x40000000U

Filter bit 30

#define CAN_F5R1_FB31   0x80000000U

Filter bit 31

#define CAN_F5R1_FB4   0x00000010U

Filter bit 4

#define CAN_F5R1_FB5   0x00000020U

Filter bit 5

#define CAN_F5R1_FB6   0x00000040U

Filter bit 6

#define CAN_F5R1_FB7   0x00000080U

Filter bit 7

#define CAN_F5R1_FB8   0x00000100U

Filter bit 8

#define CAN_F5R1_FB9   0x00000200U

Filter bit 9

#define CAN_F5R2_FB0   0x00000001U

Filter bit 0

#define CAN_F5R2_FB1   0x00000002U

Filter bit 1

#define CAN_F5R2_FB10   0x00000400U

Filter bit 10

#define CAN_F5R2_FB11   0x00000800U

Filter bit 11

#define CAN_F5R2_FB12   0x00001000U

Filter bit 12

#define CAN_F5R2_FB13   0x00002000U

Filter bit 13

#define CAN_F5R2_FB14   0x00004000U

Filter bit 14

#define CAN_F5R2_FB15   0x00008000U

Filter bit 15

#define CAN_F5R2_FB16   0x00010000U

Filter bit 16

#define CAN_F5R2_FB17   0x00020000U

Filter bit 17

#define CAN_F5R2_FB18   0x00040000U

Filter bit 18

#define CAN_F5R2_FB19   0x00080000U

Filter bit 19

#define CAN_F5R2_FB2   0x00000004U

Filter bit 2

#define CAN_F5R2_FB20   0x00100000U

Filter bit 20

#define CAN_F5R2_FB21   0x00200000U

Filter bit 21

#define CAN_F5R2_FB22   0x00400000U

Filter bit 22

#define CAN_F5R2_FB23   0x00800000U

Filter bit 23

#define CAN_F5R2_FB24   0x01000000U

Filter bit 24

#define CAN_F5R2_FB25   0x02000000U

Filter bit 25

#define CAN_F5R2_FB26   0x04000000U

Filter bit 26

#define CAN_F5R2_FB27   0x08000000U

Filter bit 27

#define CAN_F5R2_FB28   0x10000000U

Filter bit 28

#define CAN_F5R2_FB29   0x20000000U

Filter bit 29

#define CAN_F5R2_FB3   0x00000008U

Filter bit 3

#define CAN_F5R2_FB30   0x40000000U

Filter bit 30

#define CAN_F5R2_FB31   0x80000000U

Filter bit 31

#define CAN_F5R2_FB4   0x00000010U

Filter bit 4

#define CAN_F5R2_FB5   0x00000020U

Filter bit 5

#define CAN_F5R2_FB6   0x00000040U

Filter bit 6

#define CAN_F5R2_FB7   0x00000080U

Filter bit 7

#define CAN_F5R2_FB8   0x00000100U

Filter bit 8

#define CAN_F5R2_FB9   0x00000200U

Filter bit 9

#define CAN_F6R1_FB0   0x00000001U

Filter bit 0

#define CAN_F6R1_FB1   0x00000002U

Filter bit 1

#define CAN_F6R1_FB10   0x00000400U

Filter bit 10

#define CAN_F6R1_FB11   0x00000800U

Filter bit 11

#define CAN_F6R1_FB12   0x00001000U

Filter bit 12

#define CAN_F6R1_FB13   0x00002000U

Filter bit 13

#define CAN_F6R1_FB14   0x00004000U

Filter bit 14

#define CAN_F6R1_FB15   0x00008000U

Filter bit 15

#define CAN_F6R1_FB16   0x00010000U

Filter bit 16

#define CAN_F6R1_FB17   0x00020000U

Filter bit 17

#define CAN_F6R1_FB18   0x00040000U

Filter bit 18

#define CAN_F6R1_FB19   0x00080000U

Filter bit 19

#define CAN_F6R1_FB2   0x00000004U

Filter bit 2

#define CAN_F6R1_FB20   0x00100000U

Filter bit 20

#define CAN_F6R1_FB21   0x00200000U

Filter bit 21

#define CAN_F6R1_FB22   0x00400000U

Filter bit 22

#define CAN_F6R1_FB23   0x00800000U

Filter bit 23

#define CAN_F6R1_FB24   0x01000000U

Filter bit 24

#define CAN_F6R1_FB25   0x02000000U

Filter bit 25

#define CAN_F6R1_FB26   0x04000000U

Filter bit 26

#define CAN_F6R1_FB27   0x08000000U

Filter bit 27

#define CAN_F6R1_FB28   0x10000000U

Filter bit 28

#define CAN_F6R1_FB29   0x20000000U

Filter bit 29

#define CAN_F6R1_FB3   0x00000008U

Filter bit 3

#define CAN_F6R1_FB30   0x40000000U

Filter bit 30

#define CAN_F6R1_FB31   0x80000000U

Filter bit 31

#define CAN_F6R1_FB4   0x00000010U

Filter bit 4

#define CAN_F6R1_FB5   0x00000020U

Filter bit 5

#define CAN_F6R1_FB6   0x00000040U

Filter bit 6

#define CAN_F6R1_FB7   0x00000080U

Filter bit 7

#define CAN_F6R1_FB8   0x00000100U

Filter bit 8

#define CAN_F6R1_FB9   0x00000200U

Filter bit 9

#define CAN_F6R2_FB0   0x00000001U

Filter bit 0

#define CAN_F6R2_FB1   0x00000002U

Filter bit 1

#define CAN_F6R2_FB10   0x00000400U

Filter bit 10

#define CAN_F6R2_FB11   0x00000800U

Filter bit 11

#define CAN_F6R2_FB12   0x00001000U

Filter bit 12

#define CAN_F6R2_FB13   0x00002000U

Filter bit 13

#define CAN_F6R2_FB14   0x00004000U

Filter bit 14

#define CAN_F6R2_FB15   0x00008000U

Filter bit 15

#define CAN_F6R2_FB16   0x00010000U

Filter bit 16

#define CAN_F6R2_FB17   0x00020000U

Filter bit 17

#define CAN_F6R2_FB18   0x00040000U

Filter bit 18

#define CAN_F6R2_FB19   0x00080000U

Filter bit 19

#define CAN_F6R2_FB2   0x00000004U

Filter bit 2

#define CAN_F6R2_FB20   0x00100000U

Filter bit 20

#define CAN_F6R2_FB21   0x00200000U

Filter bit 21

#define CAN_F6R2_FB22   0x00400000U

Filter bit 22

#define CAN_F6R2_FB23   0x00800000U

Filter bit 23

#define CAN_F6R2_FB24   0x01000000U

Filter bit 24

#define CAN_F6R2_FB25   0x02000000U

Filter bit 25

#define CAN_F6R2_FB26   0x04000000U

Filter bit 26

#define CAN_F6R2_FB27   0x08000000U

Filter bit 27

#define CAN_F6R2_FB28   0x10000000U

Filter bit 28

#define CAN_F6R2_FB29   0x20000000U

Filter bit 29

#define CAN_F6R2_FB3   0x00000008U

Filter bit 3

#define CAN_F6R2_FB30   0x40000000U

Filter bit 30

#define CAN_F6R2_FB31   0x80000000U

Filter bit 31

#define CAN_F6R2_FB4   0x00000010U

Filter bit 4

#define CAN_F6R2_FB5   0x00000020U

Filter bit 5

#define CAN_F6R2_FB6   0x00000040U

Filter bit 6

#define CAN_F6R2_FB7   0x00000080U

Filter bit 7

#define CAN_F6R2_FB8   0x00000100U

Filter bit 8

#define CAN_F6R2_FB9   0x00000200U

Filter bit 9

#define CAN_F7R1_FB0   0x00000001U

Filter bit 0

#define CAN_F7R1_FB1   0x00000002U

Filter bit 1

#define CAN_F7R1_FB10   0x00000400U

Filter bit 10

#define CAN_F7R1_FB11   0x00000800U

Filter bit 11

#define CAN_F7R1_FB12   0x00001000U

Filter bit 12

#define CAN_F7R1_FB13   0x00002000U

Filter bit 13

#define CAN_F7R1_FB14   0x00004000U

Filter bit 14

#define CAN_F7R1_FB15   0x00008000U

Filter bit 15

#define CAN_F7R1_FB16   0x00010000U

Filter bit 16

#define CAN_F7R1_FB17   0x00020000U

Filter bit 17

#define CAN_F7R1_FB18   0x00040000U

Filter bit 18

#define CAN_F7R1_FB19   0x00080000U

Filter bit 19

#define CAN_F7R1_FB2   0x00000004U

Filter bit 2

#define CAN_F7R1_FB20   0x00100000U

Filter bit 20

#define CAN_F7R1_FB21   0x00200000U

Filter bit 21

#define CAN_F7R1_FB22   0x00400000U

Filter bit 22

#define CAN_F7R1_FB23   0x00800000U

Filter bit 23

#define CAN_F7R1_FB24   0x01000000U

Filter bit 24

#define CAN_F7R1_FB25   0x02000000U

Filter bit 25

#define CAN_F7R1_FB26   0x04000000U

Filter bit 26

#define CAN_F7R1_FB27   0x08000000U

Filter bit 27

#define CAN_F7R1_FB28   0x10000000U

Filter bit 28

#define CAN_F7R1_FB29   0x20000000U

Filter bit 29

#define CAN_F7R1_FB3   0x00000008U

Filter bit 3

#define CAN_F7R1_FB30   0x40000000U

Filter bit 30

#define CAN_F7R1_FB31   0x80000000U

Filter bit 31

#define CAN_F7R1_FB4   0x00000010U

Filter bit 4

#define CAN_F7R1_FB5   0x00000020U

Filter bit 5

#define CAN_F7R1_FB6   0x00000040U

Filter bit 6

#define CAN_F7R1_FB7   0x00000080U

Filter bit 7

#define CAN_F7R1_FB8   0x00000100U

Filter bit 8

#define CAN_F7R1_FB9   0x00000200U

Filter bit 9

#define CAN_F7R2_FB0   0x00000001U

Filter bit 0

#define CAN_F7R2_FB1   0x00000002U

Filter bit 1

#define CAN_F7R2_FB10   0x00000400U

Filter bit 10

#define CAN_F7R2_FB11   0x00000800U

Filter bit 11

#define CAN_F7R2_FB12   0x00001000U

Filter bit 12

#define CAN_F7R2_FB13   0x00002000U

Filter bit 13

#define CAN_F7R2_FB14   0x00004000U

Filter bit 14

#define CAN_F7R2_FB15   0x00008000U

Filter bit 15

#define CAN_F7R2_FB16   0x00010000U

Filter bit 16

#define CAN_F7R2_FB17   0x00020000U

Filter bit 17

#define CAN_F7R2_FB18   0x00040000U

Filter bit 18

#define CAN_F7R2_FB19   0x00080000U

Filter bit 19

#define CAN_F7R2_FB2   0x00000004U

Filter bit 2

#define CAN_F7R2_FB20   0x00100000U

Filter bit 20

#define CAN_F7R2_FB21   0x00200000U

Filter bit 21

#define CAN_F7R2_FB22   0x00400000U

Filter bit 22

#define CAN_F7R2_FB23   0x00800000U

Filter bit 23

#define CAN_F7R2_FB24   0x01000000U

Filter bit 24

#define CAN_F7R2_FB25   0x02000000U

Filter bit 25

#define CAN_F7R2_FB26   0x04000000U

Filter bit 26

#define CAN_F7R2_FB27   0x08000000U

Filter bit 27

#define CAN_F7R2_FB28   0x10000000U

Filter bit 28

#define CAN_F7R2_FB29   0x20000000U

Filter bit 29

#define CAN_F7R2_FB3   0x00000008U

Filter bit 3

#define CAN_F7R2_FB30   0x40000000U

Filter bit 30

#define CAN_F7R2_FB31   0x80000000U

Filter bit 31

#define CAN_F7R2_FB4   0x00000010U

Filter bit 4

#define CAN_F7R2_FB5   0x00000020U

Filter bit 5

#define CAN_F7R2_FB6   0x00000040U

Filter bit 6

#define CAN_F7R2_FB7   0x00000080U

Filter bit 7

#define CAN_F7R2_FB8   0x00000100U

Filter bit 8

#define CAN_F7R2_FB9   0x00000200U

Filter bit 9

#define CAN_F8R1_FB0   0x00000001U

Filter bit 0

#define CAN_F8R1_FB1   0x00000002U

Filter bit 1

#define CAN_F8R1_FB10   0x00000400U

Filter bit 10

#define CAN_F8R1_FB11   0x00000800U

Filter bit 11

#define CAN_F8R1_FB12   0x00001000U

Filter bit 12

#define CAN_F8R1_FB13   0x00002000U

Filter bit 13

#define CAN_F8R1_FB14   0x00004000U

Filter bit 14

#define CAN_F8R1_FB15   0x00008000U

Filter bit 15

#define CAN_F8R1_FB16   0x00010000U

Filter bit 16

#define CAN_F8R1_FB17   0x00020000U

Filter bit 17

#define CAN_F8R1_FB18   0x00040000U

Filter bit 18

#define CAN_F8R1_FB19   0x00080000U

Filter bit 19

#define CAN_F8R1_FB2   0x00000004U

Filter bit 2

#define CAN_F8R1_FB20   0x00100000U

Filter bit 20

#define CAN_F8R1_FB21   0x00200000U

Filter bit 21

#define CAN_F8R1_FB22   0x00400000U

Filter bit 22

#define CAN_F8R1_FB23   0x00800000U

Filter bit 23

#define CAN_F8R1_FB24   0x01000000U

Filter bit 24

#define CAN_F8R1_FB25   0x02000000U

Filter bit 25

#define CAN_F8R1_FB26   0x04000000U

Filter bit 26

#define CAN_F8R1_FB27   0x08000000U

Filter bit 27

#define CAN_F8R1_FB28   0x10000000U

Filter bit 28

#define CAN_F8R1_FB29   0x20000000U

Filter bit 29

#define CAN_F8R1_FB3   0x00000008U

Filter bit 3

#define CAN_F8R1_FB30   0x40000000U

Filter bit 30

#define CAN_F8R1_FB31   0x80000000U

Filter bit 31

#define CAN_F8R1_FB4   0x00000010U

Filter bit 4

#define CAN_F8R1_FB5   0x00000020U

Filter bit 5

#define CAN_F8R1_FB6   0x00000040U

Filter bit 6

#define CAN_F8R1_FB7   0x00000080U

Filter bit 7

#define CAN_F8R1_FB8   0x00000100U

Filter bit 8

#define CAN_F8R1_FB9   0x00000200U

Filter bit 9

#define CAN_F8R2_FB0   0x00000001U

Filter bit 0

#define CAN_F8R2_FB1   0x00000002U

Filter bit 1

#define CAN_F8R2_FB10   0x00000400U

Filter bit 10

#define CAN_F8R2_FB11   0x00000800U

Filter bit 11

#define CAN_F8R2_FB12   0x00001000U

Filter bit 12

#define CAN_F8R2_FB13   0x00002000U

Filter bit 13

#define CAN_F8R2_FB14   0x00004000U

Filter bit 14

#define CAN_F8R2_FB15   0x00008000U

Filter bit 15

#define CAN_F8R2_FB16   0x00010000U

Filter bit 16

#define CAN_F8R2_FB17   0x00020000U

Filter bit 17

#define CAN_F8R2_FB18   0x00040000U

Filter bit 18

#define CAN_F8R2_FB19   0x00080000U

Filter bit 19

#define CAN_F8R2_FB2   0x00000004U

Filter bit 2

#define CAN_F8R2_FB20   0x00100000U

Filter bit 20

#define CAN_F8R2_FB21   0x00200000U

Filter bit 21

#define CAN_F8R2_FB22   0x00400000U

Filter bit 22

#define CAN_F8R2_FB23   0x00800000U

Filter bit 23

#define CAN_F8R2_FB24   0x01000000U

Filter bit 24

#define CAN_F8R2_FB25   0x02000000U

Filter bit 25

#define CAN_F8R2_FB26   0x04000000U

Filter bit 26

#define CAN_F8R2_FB27   0x08000000U

Filter bit 27

#define CAN_F8R2_FB28   0x10000000U

Filter bit 28

#define CAN_F8R2_FB29   0x20000000U

Filter bit 29

#define CAN_F8R2_FB3   0x00000008U

Filter bit 3

#define CAN_F8R2_FB30   0x40000000U

Filter bit 30

#define CAN_F8R2_FB31   0x80000000U

Filter bit 31

#define CAN_F8R2_FB4   0x00000010U

Filter bit 4

#define CAN_F8R2_FB5   0x00000020U

Filter bit 5

#define CAN_F8R2_FB6   0x00000040U

Filter bit 6

#define CAN_F8R2_FB7   0x00000080U

Filter bit 7

#define CAN_F8R2_FB8   0x00000100U

Filter bit 8

#define CAN_F8R2_FB9   0x00000200U

Filter bit 9

#define CAN_F9R1_FB0   0x00000001U

Filter bit 0

#define CAN_F9R1_FB1   0x00000002U

Filter bit 1

#define CAN_F9R1_FB10   0x00000400U

Filter bit 10

#define CAN_F9R1_FB11   0x00000800U

Filter bit 11

#define CAN_F9R1_FB12   0x00001000U

Filter bit 12

#define CAN_F9R1_FB13   0x00002000U

Filter bit 13

#define CAN_F9R1_FB14   0x00004000U

Filter bit 14

#define CAN_F9R1_FB15   0x00008000U

Filter bit 15

#define CAN_F9R1_FB16   0x00010000U

Filter bit 16

#define CAN_F9R1_FB17   0x00020000U

Filter bit 17

#define CAN_F9R1_FB18   0x00040000U

Filter bit 18

#define CAN_F9R1_FB19   0x00080000U

Filter bit 19

#define CAN_F9R1_FB2   0x00000004U

Filter bit 2

#define CAN_F9R1_FB20   0x00100000U

Filter bit 20

#define CAN_F9R1_FB21   0x00200000U

Filter bit 21

#define CAN_F9R1_FB22   0x00400000U

Filter bit 22

#define CAN_F9R1_FB23   0x00800000U

Filter bit 23

#define CAN_F9R1_FB24   0x01000000U

Filter bit 24

#define CAN_F9R1_FB25   0x02000000U

Filter bit 25

#define CAN_F9R1_FB26   0x04000000U

Filter bit 26

#define CAN_F9R1_FB27   0x08000000U

Filter bit 27

#define CAN_F9R1_FB28   0x10000000U

Filter bit 28

#define CAN_F9R1_FB29   0x20000000U

Filter bit 29

#define CAN_F9R1_FB3   0x00000008U

Filter bit 3

#define CAN_F9R1_FB30   0x40000000U

Filter bit 30

#define CAN_F9R1_FB31   0x80000000U

Filter bit 31

#define CAN_F9R1_FB4   0x00000010U

Filter bit 4

#define CAN_F9R1_FB5   0x00000020U

Filter bit 5

#define CAN_F9R1_FB6   0x00000040U

Filter bit 6

#define CAN_F9R1_FB7   0x00000080U

Filter bit 7

#define CAN_F9R1_FB8   0x00000100U

Filter bit 8

#define CAN_F9R1_FB9   0x00000200U

Filter bit 9

#define CAN_F9R2_FB0   0x00000001U

Filter bit 0

#define CAN_F9R2_FB1   0x00000002U

Filter bit 1

#define CAN_F9R2_FB10   0x00000400U

Filter bit 10

#define CAN_F9R2_FB11   0x00000800U

Filter bit 11

#define CAN_F9R2_FB12   0x00001000U

Filter bit 12

#define CAN_F9R2_FB13   0x00002000U

Filter bit 13

#define CAN_F9R2_FB14   0x00004000U

Filter bit 14

#define CAN_F9R2_FB15   0x00008000U

Filter bit 15

#define CAN_F9R2_FB16   0x00010000U

Filter bit 16

#define CAN_F9R2_FB17   0x00020000U

Filter bit 17

#define CAN_F9R2_FB18   0x00040000U

Filter bit 18

#define CAN_F9R2_FB19   0x00080000U

Filter bit 19

#define CAN_F9R2_FB2   0x00000004U

Filter bit 2

#define CAN_F9R2_FB20   0x00100000U

Filter bit 20

#define CAN_F9R2_FB21   0x00200000U

Filter bit 21

#define CAN_F9R2_FB22   0x00400000U

Filter bit 22

#define CAN_F9R2_FB23   0x00800000U

Filter bit 23

#define CAN_F9R2_FB24   0x01000000U

Filter bit 24

#define CAN_F9R2_FB25   0x02000000U

Filter bit 25

#define CAN_F9R2_FB26   0x04000000U

Filter bit 26

#define CAN_F9R2_FB27   0x08000000U

Filter bit 27

#define CAN_F9R2_FB28   0x10000000U

Filter bit 28

#define CAN_F9R2_FB29   0x20000000U

Filter bit 29

#define CAN_F9R2_FB3   0x00000008U

Filter bit 3

#define CAN_F9R2_FB30   0x40000000U

Filter bit 30

#define CAN_F9R2_FB31   0x80000000U

Filter bit 31

#define CAN_F9R2_FB4   0x00000010U

Filter bit 4

#define CAN_F9R2_FB5   0x00000020U

Filter bit 5

#define CAN_F9R2_FB6   0x00000040U

Filter bit 6

#define CAN_F9R2_FB7   0x00000080U

Filter bit 7

#define CAN_F9R2_FB8   0x00000100U

Filter bit 8

#define CAN_F9R2_FB9   0x00000200U

Filter bit 9

#define CAN_FA1R_FACT   0x00003FFFU

Filter Active

#define CAN_FA1R_FACT0   0x00000001U

Filter 0 Active

#define CAN_FA1R_FACT1   0x00000002U

Filter 1 Active

#define CAN_FA1R_FACT10   0x00000400U

Filter 10 Active

#define CAN_FA1R_FACT11   0x00000800U

Filter 11 Active

#define CAN_FA1R_FACT12   0x00001000U

Filter 12 Active

#define CAN_FA1R_FACT13   0x00002000U

Filter 13 Active

#define CAN_FA1R_FACT2   0x00000004U

Filter 2 Active

#define CAN_FA1R_FACT3   0x00000008U

Filter 3 Active

#define CAN_FA1R_FACT4   0x00000010U

Filter 4 Active

#define CAN_FA1R_FACT5   0x00000020U

Filter 5 Active

#define CAN_FA1R_FACT6   0x00000040U

Filter 6 Active

#define CAN_FA1R_FACT7   0x00000080U

Filter 7 Active

#define CAN_FA1R_FACT8   0x00000100U

Filter 8 Active

#define CAN_FA1R_FACT9   0x00000200U

Filter 9 Active

#define CAN_FFA1R_FFA   0x00003FFFU

Filter FIFO Assignment

#define CAN_FFA1R_FFA0   0x00000001U

Filter FIFO Assignment for Filter 0

#define CAN_FFA1R_FFA1   0x00000002U

Filter FIFO Assignment for Filter 1

#define CAN_FFA1R_FFA10   0x00000400U

Filter FIFO Assignment for Filter 10

#define CAN_FFA1R_FFA11   0x00000800U

Filter FIFO Assignment for Filter 11

#define CAN_FFA1R_FFA12   0x00001000U

Filter FIFO Assignment for Filter 12

#define CAN_FFA1R_FFA13   0x00002000U

Filter FIFO Assignment for Filter 13

#define CAN_FFA1R_FFA2   0x00000004U

Filter FIFO Assignment for Filter 2

#define CAN_FFA1R_FFA3   0x00000008U

Filter FIFO Assignment for Filter 3

#define CAN_FFA1R_FFA4   0x00000010U

Filter FIFO Assignment for Filter 4

#define CAN_FFA1R_FFA5   0x00000020U

Filter FIFO Assignment for Filter 5

#define CAN_FFA1R_FFA6   0x00000040U

Filter FIFO Assignment for Filter 6

#define CAN_FFA1R_FFA7   0x00000080U

Filter FIFO Assignment for Filter 7

#define CAN_FFA1R_FFA8   0x00000100U

Filter FIFO Assignment for Filter 8

#define CAN_FFA1R_FFA9   0x00000200U

Filter FIFO Assignment for Filter 9

#define CAN_FM1R_FBM   0x3FFFU

Filter Mode

#define CAN_FM1R_FBM0   0x0001U

Filter Init Mode bit 0

#define CAN_FM1R_FBM1   0x0002U

Filter Init Mode bit 1

#define CAN_FM1R_FBM10   0x0400U

Filter Init Mode bit 10

#define CAN_FM1R_FBM11   0x0800U

Filter Init Mode bit 11

#define CAN_FM1R_FBM12   0x1000U

Filter Init Mode bit 12

#define CAN_FM1R_FBM13   0x2000U

Filter Init Mode bit 13

#define CAN_FM1R_FBM2   0x0004U

Filter Init Mode bit 2

#define CAN_FM1R_FBM3   0x0008U

Filter Init Mode bit 3

#define CAN_FM1R_FBM4   0x0010U

Filter Init Mode bit 4

#define CAN_FM1R_FBM5   0x0020U

Filter Init Mode bit 5

#define CAN_FM1R_FBM6   0x0040U

Filter Init Mode bit 6

#define CAN_FM1R_FBM7   0x0080U

Filter Init Mode bit 7

#define CAN_FM1R_FBM8   0x0100U

Filter Init Mode bit 8

#define CAN_FM1R_FBM9   0x0200U

Filter Init Mode bit 9

#define CAN_FMR_CAN2SB   0x00003F00U

CAN2 start bank

#define CAN_FMR_FINIT   ((uint8_t)0x01U)

Filter Init Mode

#define CAN_FS1R_FSC   0x00003FFFU

Filter Scale Configuration

#define CAN_FS1R_FSC0   0x00000001U

Filter Scale Configuration bit 0

#define CAN_FS1R_FSC1   0x00000002U

Filter Scale Configuration bit 1

#define CAN_FS1R_FSC10   0x00000400U

Filter Scale Configuration bit 10

#define CAN_FS1R_FSC11   0x00000800U

Filter Scale Configuration bit 11

#define CAN_FS1R_FSC12   0x00001000U

Filter Scale Configuration bit 12

#define CAN_FS1R_FSC13   0x00002000U

Filter Scale Configuration bit 13

#define CAN_FS1R_FSC2   0x00000004U

Filter Scale Configuration bit 2

#define CAN_FS1R_FSC3   0x00000008U

Filter Scale Configuration bit 3

#define CAN_FS1R_FSC4   0x00000010U

Filter Scale Configuration bit 4

#define CAN_FS1R_FSC5   0x00000020U

Filter Scale Configuration bit 5

#define CAN_FS1R_FSC6   0x00000040U

Filter Scale Configuration bit 6

#define CAN_FS1R_FSC7   0x00000080U

Filter Scale Configuration bit 7

#define CAN_FS1R_FSC8   0x00000100U

Filter Scale Configuration bit 8

#define CAN_FS1R_FSC9   0x00000200U

Filter Scale Configuration bit 9

#define CAN_IER_BOFIE   0x00000400U

Bus-Off Interrupt Enable

#define CAN_IER_EPVIE   0x00000200U

Error Passive Interrupt Enable

#define CAN_IER_ERRIE   0x00008000U

Error Interrupt Enable

#define CAN_IER_EWGIE   0x00000100U

Error Warning Interrupt Enable

#define CAN_IER_FFIE0   0x00000004U

FIFO Full Interrupt Enable

#define CAN_IER_FFIE1   0x00000020U

FIFO Full Interrupt Enable

#define CAN_IER_FMPIE0   0x00000002U

FIFO Message Pending Interrupt Enable

#define CAN_IER_FMPIE1   0x00000010U

FIFO Message Pending Interrupt Enable

#define CAN_IER_FOVIE0   0x00000008U

FIFO Overrun Interrupt Enable

#define CAN_IER_FOVIE1   0x00000040U

FIFO Overrun Interrupt Enable

#define CAN_IER_LECIE   0x00000800U

Last Error Code Interrupt Enable

#define CAN_IER_SLKIE   0x00020000U

Sleep Interrupt Enable

#define CAN_IER_TMEIE   0x00000001U

Transmit Mailbox Empty Interrupt Enable

#define CAN_IER_WKUIE   0x00010000U

Wakeup Interrupt Enable

#define CAN_MCR_ABOM   0x00000040U

Automatic Bus-Off Management

#define CAN_MCR_AWUM   0x00000020U

Automatic Wakeup Mode

#define CAN_MCR_INRQ   0x00000001U

<CAN control and status registers Initialization Request

#define CAN_MCR_NART   0x00000010U

No Automatic Retransmission

#define CAN_MCR_RESET   0x00008000U

bxCAN software master reset

#define CAN_MCR_RFLM   0x00000008U

Receive FIFO Locked Mode

#define CAN_MCR_SLEEP   0x00000002U

Sleep Mode Request

#define CAN_MCR_TTCM   0x00000080U

Time Triggered Communication Mode

#define CAN_MCR_TXFP   0x00000004U

Transmit FIFO Priority

#define CAN_MSR_ERRI   0x00000004U

Error Interrupt

#define CAN_MSR_INAK   0x00000001U

Initialization Acknowledge

#define CAN_MSR_RX   0x00000800U

CAN Rx Signal

#define CAN_MSR_RXM   0x00000200U

Receive Mode

#define CAN_MSR_SAMP   0x00000400U

Last Sample Point

#define CAN_MSR_SLAK   0x00000002U

Sleep Acknowledge

#define CAN_MSR_SLAKI   0x00000010U

Sleep Acknowledge Interrupt

#define CAN_MSR_TXM   0x00000100U

Transmit Mode

#define CAN_MSR_WKUI   0x00000008U

Wakeup Interrupt

#define CAN_RDH0R_DATA4   0x000000FFU

Data byte 4

#define CAN_RDH0R_DATA5   0x0000FF00U

Data byte 5

#define CAN_RDH0R_DATA6   0x00FF0000U

Data byte 6

#define CAN_RDH0R_DATA7   0xFF000000U

Data byte 7

#define CAN_RDH1R_DATA4   0x000000FFU

Data byte 4

#define CAN_RDH1R_DATA5   0x0000FF00U

Data byte 5

#define CAN_RDH1R_DATA6   0x00FF0000U

Data byte 6

#define CAN_RDH1R_DATA7   0xFF000000U

Data byte 7 CAN filter registers

#define CAN_RDL0R_DATA0   0x000000FFU

Data byte 0

#define CAN_RDL0R_DATA1   0x0000FF00U

Data byte 1

#define CAN_RDL0R_DATA2   0x00FF0000U

Data byte 2

#define CAN_RDL0R_DATA3   0xFF000000U

Data byte 3

#define CAN_RDL1R_DATA0   0x000000FFU

Data byte 0

#define CAN_RDL1R_DATA1   0x0000FF00U

Data byte 1

#define CAN_RDL1R_DATA2   0x00FF0000U

Data byte 2

#define CAN_RDL1R_DATA3   0xFF000000U

Data byte 3

#define CAN_RDT0R_DLC   0x0000000FU

Data Length Code

#define CAN_RDT0R_FMI   0x0000FF00U

Filter Match Index

#define CAN_RDT0R_TIME   0xFFFF0000U

Message Time Stamp

#define CAN_RDT1R_DLC   0x0000000FU

Data Length Code

#define CAN_RDT1R_FMI   0x0000FF00U

Filter Match Index

#define CAN_RDT1R_TIME   0xFFFF0000U

Message Time Stamp

#define CAN_RF0R_FMP0   0x00000003U

FIFO 0 Message Pending

#define CAN_RF0R_FOVR0   0x00000010U

FIFO 0 Overrun

#define CAN_RF0R_FULL0   0x00000008U

FIFO 0 Full

#define CAN_RF0R_RFOM0   0x00000020U

Release FIFO 0 Output Mailbox

#define CAN_RF1R_FMP1   0x00000003U

FIFO 1 Message Pending

#define CAN_RF1R_FOVR1   0x00000010U

FIFO 1 Overrun

#define CAN_RF1R_FULL1   0x00000008U

FIFO 1 Full

#define CAN_RF1R_RFOM1   0x00000020U

Release FIFO 1 Output Mailbox

#define CAN_RI0R_EXID   0x001FFFF8U

Extended Identifier

#define CAN_RI0R_IDE   0x00000004U

Identifier Extension

#define CAN_RI0R_RTR   0x00000002U

Remote Transmission Request

#define CAN_RI0R_STID   0xFFE00000U

Standard Identifier or Extended Identifier

#define CAN_RI1R_EXID   0x001FFFF8U

Extended identifier

#define CAN_RI1R_IDE   0x00000004U

Identifier Extension

#define CAN_RI1R_RTR   0x00000002U

Remote Transmission Request

#define CAN_RI1R_STID   0xFFE00000U

Standard Identifier or Extended Identifier

#define CAN_TDH0R_DATA4   0x000000FFU

Data byte 4

#define CAN_TDH0R_DATA5   0x0000FF00U

Data byte 5

#define CAN_TDH0R_DATA6   0x00FF0000U

Data byte 6

#define CAN_TDH0R_DATA7   0xFF000000U

Data byte 7

#define CAN_TDH1R_DATA4   0x000000FFU

Data byte 4

#define CAN_TDH1R_DATA5   0x0000FF00U

Data byte 5

#define CAN_TDH1R_DATA6   0x00FF0000U

Data byte 6

#define CAN_TDH1R_DATA7   0xFF000000U

Data byte 7

#define CAN_TDH2R_DATA4   0x000000FFU

Data byte 4

#define CAN_TDH2R_DATA5   0x0000FF00U

Data byte 5

#define CAN_TDH2R_DATA6   0x00FF0000U

Data byte 6

#define CAN_TDH2R_DATA7   0xFF000000U

Data byte 7

#define CAN_TDL0R_DATA0   0x000000FFU

Data byte 0

#define CAN_TDL0R_DATA1   0x0000FF00U

Data byte 1

#define CAN_TDL0R_DATA2   0x00FF0000U

Data byte 2

#define CAN_TDL0R_DATA3   0xFF000000U

Data byte 3

#define CAN_TDL1R_DATA0   0x000000FFU

Data byte 0

#define CAN_TDL1R_DATA1   0x0000FF00U

Data byte 1

#define CAN_TDL1R_DATA2   0x00FF0000U

Data byte 2

#define CAN_TDL1R_DATA3   0xFF000000U

Data byte 3

#define CAN_TDL2R_DATA0   0x000000FFU

Data byte 0

#define CAN_TDL2R_DATA1   0x0000FF00U

Data byte 1

#define CAN_TDL2R_DATA2   0x00FF0000U

Data byte 2

#define CAN_TDL2R_DATA3   0xFF000000U

Data byte 3

#define CAN_TDT0R_DLC   0x0000000FU

Data Length Code

#define CAN_TDT0R_TGT   0x00000100U

Transmit Global Time

#define CAN_TDT0R_TIME   0xFFFF0000U

Message Time Stamp

#define CAN_TDT1R_DLC   0x0000000FU

Data Length Code

#define CAN_TDT1R_TGT   0x00000100U

Transmit Global Time

#define CAN_TDT1R_TIME   0xFFFF0000U

Message Time Stamp

#define CAN_TDT2R_DLC   0x0000000FU

Data Length Code

#define CAN_TDT2R_TGT   0x00000100U

Transmit Global Time

#define CAN_TDT2R_TIME   0xFFFF0000U

Message Time Stamp

#define CAN_TI0R_EXID   0x001FFFF8U

Extended Identifier

#define CAN_TI0R_IDE   0x00000004U

Identifier Extension

#define CAN_TI0R_RTR   0x00000002U

Remote Transmission Request

#define CAN_TI0R_STID   0xFFE00000U

Standard Identifier or Extended Identifier

#define CAN_TI0R_TXRQ   0x00000001U

Transmit Mailbox Request

#define CAN_TI1R_EXID   0x001FFFF8U

Extended Identifier

#define CAN_TI1R_IDE   0x00000004U

Identifier Extension

#define CAN_TI1R_RTR   0x00000002U

Remote Transmission Request

#define CAN_TI1R_STID   0xFFE00000U

Standard Identifier or Extended Identifier

#define CAN_TI1R_TXRQ   0x00000001U

Transmit Mailbox Request

#define CAN_TI2R_EXID   0x001FFFF8U

Extended identifier

#define CAN_TI2R_IDE   0x00000004U

Identifier Extension

#define CAN_TI2R_RTR   0x00000002U

Remote Transmission Request

#define CAN_TI2R_STID   0xFFE00000U

Standard Identifier or Extended Identifier

#define CAN_TI2R_TXRQ   0x00000001U

Transmit Mailbox Request

#define CAN_TSR_ABRQ0   0x00000080U

Abort Request for Mailbox0

#define CAN_TSR_ABRQ1   0x00008000U

Abort Request for Mailbox 1

#define CAN_TSR_ABRQ2   0x00800000U

Abort Request for Mailbox 2

#define CAN_TSR_ALST0   0x00000004U

Arbitration Lost for Mailbox0

#define CAN_TSR_ALST1   0x00000400U

Arbitration Lost for Mailbox1

#define CAN_TSR_ALST2   0x00040000U

Arbitration Lost for mailbox 2

#define CAN_TSR_CODE   0x03000000U

Mailbox Code

#define CAN_TSR_LOW   0xE0000000U

LOW[2:0] bits

#define CAN_TSR_LOW0   0x20000000U

Lowest Priority Flag for Mailbox 0

#define CAN_TSR_LOW1   0x40000000U

Lowest Priority Flag for Mailbox 1

#define CAN_TSR_LOW2   0x80000000U

Lowest Priority Flag for Mailbox 2

#define CAN_TSR_RQCP0   0x00000001U

Request Completed Mailbox0

#define CAN_TSR_RQCP1   0x00000100U

Request Completed Mailbox1

#define CAN_TSR_RQCP2   0x00010000U

Request Completed Mailbox2

#define CAN_TSR_TERR0   0x00000008U

Transmission Error of Mailbox0

#define CAN_TSR_TERR1   0x00000800U

Transmission Error of Mailbox1

#define CAN_TSR_TERR2   0x00080000U

Transmission Error of Mailbox 2

#define CAN_TSR_TME   0x1C000000U

TME[2:0] bits

#define CAN_TSR_TME0   0x04000000U

Transmit Mailbox 0 Empty

#define CAN_TSR_TME1   0x08000000U

Transmit Mailbox 1 Empty

#define CAN_TSR_TME2   0x10000000U

Transmit Mailbox 2 Empty

#define CAN_TSR_TXOK0   0x00000002U

Transmission OK of Mailbox0

#define CAN_TSR_TXOK1   0x00000200U

Transmission OK of Mailbox1

#define CAN_TSR_TXOK2   0x00020000U

Transmission OK of Mailbox 2

#define CEC_CFGR_BRDNOGEN   0x00000080U

CEC Broadcast no Error generation

#define CEC_CFGR_BREGEN   0x00000020U

CEC Bit Rising Error generation

#define CEC_CFGR_BRESTP   0x00000010U

CEC Rx Stop

#define CEC_CFGR_LBPEGEN   0x00000040U

CEC Long Period Error generation

#define CEC_CFGR_LSTN   0x80000000U

CEC Listen mode

#define CEC_CFGR_OAR   0x7FFF0000U

CEC Own Address

#define CEC_CFGR_RXTOL   0x00000008U

CEC Tolerance

#define CEC_CFGR_SFT   0x00000007U

CEC Signal Free Time

#define CEC_CFGR_SFTOPT   0x00000100U

CEC Signal Free Time optional

#define CEC_CR_CECEN   0x00000001U

CEC Enable

#define CEC_CR_TXEOM   0x00000004U

CEC Tx End Of Message

#define CEC_CR_TXSOM   0x00000002U

CEC Tx Start Of Message

#define CEC_IER_ARBLSTIE   0x00000080U

CEC Arbitration Lost IT Enable

#define CEC_IER_BREIE   0x00000008U

CEC Rx Bit Rising Error IT Enable

#define CEC_IER_LBPEIE   0x00000020U

CEC Rx Long Bit period Error IT Enable

#define CEC_IER_RXACKEIE   0x00000040U

CEC Rx Missing Acknowledge IT Enable

#define CEC_IER_RXBRIE   0x00000001U

CEC Rx-Byte Received IT Enable

#define CEC_IER_RXENDIE   0x00000002U

CEC End Of Reception IT Enable

#define CEC_IER_RXOVRIE   0x00000004U

CEC Rx-Overrun IT Enable

#define CEC_IER_SBPEIE   0x00000010U

CEC Rx Short Bit period Error IT Enable

#define CEC_IER_TXACKEIE   0x00001000U

CEC Tx Missing Acknowledge IT Enable

#define CEC_IER_TXBRIE   0x00000100U

CEC Tx Byte Request IT Enable

#define CEC_IER_TXENDIE   0x00000200U

CEC End of Transmission IT Enable

#define CEC_IER_TXERRIE   0x00000800U

CEC Tx-Error IT Enable

#define CEC_IER_TXUDRIE   0x00000400U

CEC Tx-Buffer Underrun IT Enable

#define CEC_ISR_ARBLST   0x00000080U

CEC Arbitration Lost

#define CEC_ISR_BRE   0x00000008U

CEC Rx Bit Rising Error

#define CEC_ISR_LBPE   0x00000020U

CEC Rx Long Bit period Error

#define CEC_ISR_RXACKE   0x00000040U

CEC Rx Missing Acknowledge

#define CEC_ISR_RXBR   0x00000001U

CEC Rx-Byte Received

#define CEC_ISR_RXEND   0x00000002U

CEC End Of Reception

#define CEC_ISR_RXOVR   0x00000004U

CEC Rx-Overrun

#define CEC_ISR_SBPE   0x00000010U

CEC Rx Short Bit period Error

#define CEC_ISR_TXACKE   0x00001000U

CEC Tx Missing Acknowledge

#define CEC_ISR_TXBR   0x00000100U

CEC Tx Byte Request

#define CEC_ISR_TXEND   0x00000200U

CEC End of Transmission

#define CEC_ISR_TXERR   0x00000800U

CEC Tx-Error

#define CEC_ISR_TXUDR   0x00000400U

CEC Tx-Buffer Underrun

#define CEC_TXDR_RXD   0x000000FFU

CEC Rx Data

#define CEC_TXDR_TXD   0x000000FFU

CEC Tx Data

#define CRC_CR_POLYSIZE   0x00000018U

Polynomial size bits

#define CRC_CR_POLYSIZE_0   0x00000008U

Polynomial size bit 0

#define CRC_CR_POLYSIZE_1   0x00000010U

Polynomial size bit 1

#define CRC_CR_RESET   0x00000001U

RESET the CRC computation unit bit

#define CRC_CR_REV_IN   0x00000060U

REV_IN Reverse Input Data bits

#define CRC_CR_REV_IN_0   0x00000020U

Bit 0

#define CRC_CR_REV_IN_1   0x00000040U

Bit 1

#define CRC_CR_REV_OUT   0x00000080U

REV_OUT Reverse Output Data bits

#define CRC_DR_DR   0xFFFFFFFFU

Data register bits

#define CRC_IDR_IDR   0x000000FFU

General-purpose 8-bit data register bits

#define CRC_INIT_INIT   0xFFFFFFFFU

Initial CRC value bits

#define CRC_POL_POL   0xFFFFFFFFU

Coefficients of the polynomial

#define DAC_CR_BOFF1   0x00000002U

DAC channel1 output buffer disable

#define DAC_CR_BOFF2   0x00020000U

DAC channel2 output buffer disable

#define DAC_CR_DMAEN1   0x00001000U

DAC channel1 DMA enable

#define DAC_CR_DMAEN2   0x10000000U

DAC channel2 DMA enable

#define DAC_CR_DMAUDRIE1   0x00002000U

DAC channel1 DMA underrun interrupt enable

#define DAC_CR_DMAUDRIE2   0x20000000U

DAC channel2 DMA underrun interrupt enable

#define DAC_CR_EN1   0x00000001U

DAC channel1 enable

#define DAC_CR_EN2   0x00010000U

DAC channel2 enable

#define DAC_CR_MAMP1   0x00000F00U

MAMP13:0

#define DAC_CR_MAMP1_0   0x00000100U

Bit 0

#define DAC_CR_MAMP1_1   0x00000200U

Bit 1

#define DAC_CR_MAMP1_2   0x00000400U

Bit 2

#define DAC_CR_MAMP1_3   0x00000800U

Bit 3

#define DAC_CR_MAMP2   0x0F000000U

MAMP23:0

#define DAC_CR_MAMP2_0   0x01000000U

Bit 0

#define DAC_CR_MAMP2_1   0x02000000U

Bit 1

#define DAC_CR_MAMP2_2   0x04000000U

Bit 2

#define DAC_CR_MAMP2_3   0x08000000U

Bit 3

#define DAC_CR_TEN1   0x00000004U

DAC channel1 Trigger enable

#define DAC_CR_TEN2   0x00040000U

DAC channel2 Trigger enable

#define DAC_CR_TSEL1   0x00000038U

TSEL1[2:0] (DAC channel1 Trigger selection)

#define DAC_CR_TSEL1_0   0x00000008U

Bit 0

#define DAC_CR_TSEL1_1   0x00000010U

Bit 1

#define DAC_CR_TSEL1_2   0x00000020U

Bit 2

#define DAC_CR_TSEL2   0x00380000U

TSEL2[2:0] (DAC channel2 Trigger selection)

#define DAC_CR_TSEL2_0   0x00080000U

Bit 0

#define DAC_CR_TSEL2_1   0x00100000U

Bit 1

#define DAC_CR_TSEL2_2   0x00200000U

Bit 2

#define DAC_CR_WAVE1   0x000000C0U

WAVE11:0

#define DAC_CR_WAVE1_0   0x00000040U

Bit 0

#define DAC_CR_WAVE1_1   0x00000080U

Bit 1

#define DAC_CR_WAVE2   0x00C00000U

WAVE21:0

#define DAC_CR_WAVE2_0   0x00400000U

Bit 0

#define DAC_CR_WAVE2_1   0x00800000U

Bit 1

#define DAC_DHR12L1_DACC1DHR   0xFFF0U

DAC channel1 12-bit Left aligned data

#define DAC_DHR12L2_DACC2DHR   0xFFF0U

DAC channel2 12-bit Left aligned data

#define DAC_DHR12LD_DACC1DHR   0x0000FFF0U

DAC channel1 12-bit Left aligned data

#define DAC_DHR12LD_DACC2DHR   0xFFF00000U

DAC channel2 12-bit Left aligned data

#define DAC_DHR12R1_DACC1DHR   0x0FFFU

DAC channel1 12-bit Right aligned data

#define DAC_DHR12R2_DACC2DHR   0x0FFFU

DAC channel2 12-bit Right aligned data

#define DAC_DHR12RD_DACC1DHR   0x00000FFFU

DAC channel1 12-bit Right aligned data

#define DAC_DHR12RD_DACC2DHR   0x0FFF0000U

DAC channel2 12-bit Right aligned data

#define DAC_DHR8R1_DACC1DHR   0xFFU

DAC channel1 8-bit Right aligned data

#define DAC_DHR8R2_DACC2DHR   0xFFU

DAC channel2 8-bit Right aligned data

#define DAC_DHR8RD_DACC1DHR   0x00FFU

DAC channel1 8-bit Right aligned data

#define DAC_DHR8RD_DACC2DHR   0xFF00U

DAC channel2 8-bit Right aligned data

#define DAC_DOR1_DACC1DOR   0x0FFFU

DAC channel1 data output

#define DAC_DOR2_DACC2DOR   0x0FFFU

DAC channel2 data output

#define DAC_SR_DMAUDR1   0x00002000U

DAC channel1 DMA underrun flag

#define DAC_SR_DMAUDR2   0x20000000U

DAC channel2 DMA underrun flag

#define DAC_SWTRIGR_SWTRIG1   0x01U

DAC channel1 software trigger

#define DAC_SWTRIGR_SWTRIG2   0x02U

DAC channel2 software trigger

#define DBGMCU_APB1_FZ_DBG_CAN1_STOP   0x02000000U
#define DBGMCU_APB1_FZ_DBG_CAN2_STOP   0x04000000U
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   0x00200000U
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   0x00400000U
#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT   0x00800000U
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP   0x00001000U
#define DBGMCU_APB1_FZ_DBG_RTC_STOP   0x00000400U
#define DBGMCU_APB1_FZ_DBG_TIM12_STOP   0x00000040U
#define DBGMCU_APB1_FZ_DBG_TIM13_STOP   0x00000080U
#define DBGMCU_APB1_FZ_DBG_TIM14_STOP   0x00000100U
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP   0x00000001U
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP   0x00000002U
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP   0x00000004U
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP   0x00000008U
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP   0x00000010U
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP   0x00000020U
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP   0x00000800U
#define DBGMCU_APB2_FZ_DBG_TIM10_STOP   0x00020000U
#define DBGMCU_APB2_FZ_DBG_TIM11_STOP   0x00040000U
#define DBGMCU_APB2_FZ_DBG_TIM1_STOP   0x00000001U
#define DBGMCU_APB2_FZ_DBG_TIM8_STOP   0x00000002U
#define DBGMCU_APB2_FZ_DBG_TIM9_STOP   0x00010000U
#define DBGMCU_CR_DBG_SLEEP   0x00000001U
#define DBGMCU_CR_DBG_STANDBY   0x00000004U
#define DBGMCU_CR_DBG_STOP   0x00000002U
#define DBGMCU_CR_TRACE_IOEN   0x00000020U
#define DBGMCU_CR_TRACE_MODE   0x000000C0U
#define DBGMCU_CR_TRACE_MODE_0   0x00000040U

Bit 0

#define DBGMCU_CR_TRACE_MODE_1   0x00000080U

Bit 1

#define DBGMCU_IDCODE_DEV_ID   0x00000FFFU
#define DBGMCU_IDCODE_REV_ID   0xFFFF0000U
#define DCMI_CR_BSM   0x00030000U
#define DCMI_CR_BSM_0   0x00010000U
#define DCMI_CR_BSM_1   0x00020000U
#define DCMI_CR_CAPTURE   0x00000001U
#define DCMI_CR_CM   0x00000002U
#define DCMI_CR_CRE   0x00001000U
#define DCMI_CR_CROP   0x00000004U
#define DCMI_CR_EDM_0   0x00000400U
#define DCMI_CR_EDM_1   0x00000800U
#define DCMI_CR_ENABLE   0x00004000U
#define DCMI_CR_ESS   0x00000010U
#define DCMI_CR_FCRC_0   0x00000100U
#define DCMI_CR_FCRC_1   0x00000200U
#define DCMI_CR_HSPOL   0x00000040U
#define DCMI_CR_JPEG   0x00000008U
#define DCMI_CR_LSM   0x00080000U
#define DCMI_CR_OEBS   0x00040000U
#define DCMI_CR_OELS   0x00100000U
#define DCMI_CR_PCKPOL   0x00000020U
#define DCMI_CR_VSPOL   0x00000080U
#define DCMI_CWSIZE_CAPCNT   0x00003FFFU
#define DCMI_CWSIZE_VLINE   0x3FFF0000U
#define DCMI_CWSTRT_HOFFCNT   0x00003FFFU
#define DCMI_CWSTRT_VST   0x1FFF0000U
#define DCMI_DR_BYTE0   0x000000FFU
#define DCMI_DR_BYTE1   0x0000FF00U
#define DCMI_DR_BYTE2   0x00FF0000U
#define DCMI_DR_BYTE3   0xFF000000U
#define DCMI_ESCR_FEC   0xFF000000U
#define DCMI_ESCR_FSC   0x000000FFU
#define DCMI_ESCR_LEC   0x00FF0000U
#define DCMI_ESCR_LSC   0x0000FF00U
#define DCMI_ESUR_FEU   0xFF000000U
#define DCMI_ESUR_FSU   0x000000FFU
#define DCMI_ESUR_LEU   0x00FF0000U
#define DCMI_ESUR_LSU   0x0000FF00U
#define DCMI_ICR_ERR_ISC   0x00000004U
#define DCMI_ICR_FRAME_ISC   0x00000001U
#define DCMI_ICR_LINE_ISC   0x00000010U
#define DCMI_ICR_OVF_ISC   DCMI_ICR_OVR_ISC
#define DCMI_ICR_OVR_ISC   0x00000002U
#define DCMI_ICR_VSYNC_ISC   0x00000008U
#define DCMI_IER_ERR_IE   0x00000004U
#define DCMI_IER_FRAME_IE   0x00000001U
#define DCMI_IER_LINE_IE   0x00000010U
#define DCMI_IER_OVF_IE   DCMI_IER_OVR_IE
#define DCMI_IER_OVR_IE   0x00000002U
#define DCMI_IER_VSYNC_IE   0x00000008U
#define DCMI_MIS_ERR_MIS   0x00000004U
#define DCMI_MIS_FRAME_MIS   0x00000001U
#define DCMI_MIS_LINE_MIS   0x00000010U
#define DCMI_MIS_OVR_MIS   0x00000002U
#define DCMI_MIS_VSYNC_MIS   0x00000008U
#define DCMI_MISR_ERR_MIS   DCMI_MIS_ERR_MIS
#define DCMI_MISR_FRAME_MIS   DCMI_MIS_FRAME_MIS
#define DCMI_MISR_LINE_MIS   DCMI_MIS_LINE_MIS
#define DCMI_MISR_OVF_MIS   DCMI_MIS_OVR_MIS
#define DCMI_MISR_VSYNC_MIS   DCMI_MIS_VSYNC_MIS
#define DCMI_RIS_ERR_RIS   0x00000004U
#define DCMI_RIS_FRAME_RIS   0x00000001U
#define DCMI_RIS_LINE_RIS   0x00000010U
#define DCMI_RIS_OVR_RIS   0x00000002U
#define DCMI_RIS_VSYNC_RIS   0x00000008U
#define DCMI_RISR_ERR_RIS   DCMI_RIS_ERR_RIS
#define DCMI_RISR_FRAME_RIS   DCMI_RIS_FRAME_RIS
#define DCMI_RISR_LINE_RIS   DCMI_RIS_LINE_RIS
#define DCMI_RISR_OVF_RIS   DCMI_RIS_OVR_RIS
#define DCMI_RISR_VSYNC_RIS   DCMI_RIS_VSYNC_RIS
#define DCMI_SR_FNE   0x00000004U
#define DCMI_SR_HSYNC   0x00000001U
#define DCMI_SR_VSYNC   0x00000002U
#define DMA2D_AMTCR_DT   0x0000FF00U

Dead Time

#define DMA2D_AMTCR_EN   0x00000001U

Enable

#define DMA2D_BGCMAR_MA   0xFFFFFFFFU

Memory Address

#define DMA2D_BGCOLR_BLUE   0x000000FFU

Blue Value

#define DMA2D_BGCOLR_GREEN   0x0000FF00U

Green Value

#define DMA2D_BGCOLR_RED   0x00FF0000U

Red Value

#define DMA2D_BGMAR_MA   0xFFFFFFFFU

Memory Address

#define DMA2D_BGOR_LO   0x00003FFFU

Line Offset

#define DMA2D_BGPFCCR_ALPHA   0xFF000000U

background Input Alpha value

#define DMA2D_BGPFCCR_AM   0x00030000U

Alpha mode AM[1:0]

#define DMA2D_BGPFCCR_AM_0   0x00010000U

Alpha mode AM bit 0

#define DMA2D_BGPFCCR_AM_1   0x00020000U

Alpha mode AM bit 1

#define DMA2D_BGPFCCR_CCM   0x00000010U

CLUT Color mode

#define DMA2D_BGPFCCR_CM   0x0000000FU

Input color mode CM[3:0]

#define DMA2D_BGPFCCR_CM_0   0x00000001U

Input color mode CM bit 0

#define DMA2D_BGPFCCR_CM_1   0x00000002U

Input color mode CM bit 1

#define DMA2D_BGPFCCR_CM_2   0x00000004U

Input color mode CM bit 2

#define DMA2D_BGPFCCR_CS   0x0000FF00U

CLUT size

#define DMA2D_BGPFCCR_START   0x00000020U

Start

#define DMA2D_CR_ABORT   0x00000004U

Abort transfer

#define DMA2D_CR_CAEIE   0x00000800U

CLUT Access Error Interrupt Enable

#define DMA2D_CR_CEIE   0x00002000U

Configuration Error Interrupt Enable

#define DMA2D_CR_CTCIE   0x00001000U

CLUT Transfer Complete Interrupt Enable

#define DMA2D_CR_MODE   0x00030000U

DMA2D Mode[1:0]

#define DMA2D_CR_MODE_0   0x00010000U

DMA2D Mode bit 0

#define DMA2D_CR_MODE_1   0x00020000U

DMA2D Mode bit 1

#define DMA2D_CR_START   0x00000001U

Start transfer

#define DMA2D_CR_SUSP   0x00000002U

Suspend transfer

#define DMA2D_CR_TCIE   0x00000200U

Transfer Complete Interrupt Enable

#define DMA2D_CR_TEIE   0x00000100U

Transfer Error Interrupt Enable

#define DMA2D_CR_TWIE   0x00000400U

Transfer Watermark Interrupt Enable

#define DMA2D_FGCMAR_MA   0xFFFFFFFFU

Memory Address

#define DMA2D_FGCOLR_BLUE   0x000000FFU

Blue Value

#define DMA2D_FGCOLR_GREEN   0x0000FF00U

Green Value

#define DMA2D_FGCOLR_RED   0x00FF0000U

Red Value

#define DMA2D_FGMAR_MA   0xFFFFFFFFU

Memory Address

#define DMA2D_FGOR_LO   0x00003FFFU

Line Offset

#define DMA2D_FGPFCCR_ALPHA   0xFF000000U

Alpha value

#define DMA2D_FGPFCCR_AM   0x00030000U

Alpha mode AM[1:0]

#define DMA2D_FGPFCCR_AM_0   0x00010000U

Alpha mode AM bit 0

#define DMA2D_FGPFCCR_AM_1   0x00020000U

Alpha mode AM bit 1

#define DMA2D_FGPFCCR_CCM   0x00000010U

CLUT Color mode

#define DMA2D_FGPFCCR_CM   0x0000000FU

Input color mode CM[3:0]

#define DMA2D_FGPFCCR_CM_0   0x00000001U

Input color mode CM bit 0

#define DMA2D_FGPFCCR_CM_1   0x00000002U

Input color mode CM bit 1

#define DMA2D_FGPFCCR_CM_2   0x00000004U

Input color mode CM bit 2

#define DMA2D_FGPFCCR_CM_3   0x00000008U

Input color mode CM bit 3

#define DMA2D_FGPFCCR_CM_3   0x00000008U

Input color mode CM bit 3

#define DMA2D_FGPFCCR_CS   0x0000FF00U

CLUT size

#define DMA2D_FGPFCCR_START   0x00000020U

Start

#define DMA2D_IFCR_CAECIF   0x00000008U

Clears CLUT Access Error Interrupt Flag

#define DMA2D_IFCR_CCEIF   0x00000020U

Clears Configuration Error Interrupt Flag

#define DMA2D_IFCR_CCTCIF   0x00000010U

Clears CLUT Transfer Complete Interrupt Flag

#define DMA2D_IFCR_CTCIF   0x00000002U

Clears Transfer Complete Interrupt Flag

#define DMA2D_IFCR_CTEIF   0x00000001U

Clears Transfer Error Interrupt Flag

#define DMA2D_IFCR_CTWIF   0x00000004U

Clears Transfer Watermark Interrupt Flag

#define DMA2D_IFSR_CCAEIF   DMA2D_IFCR_CAECIF

Clears CLUT Access Error Interrupt Flag

#define DMA2D_IFSR_CCEIF   DMA2D_IFCR_CCEIF

Clears Configuration Error Interrupt Flag

#define DMA2D_IFSR_CCTCIF   DMA2D_IFCR_CCTCIF

Clears CLUT Transfer Complete Interrupt Flag

#define DMA2D_IFSR_CTCIF   DMA2D_IFCR_CTCIF

Clears Transfer Complete Interrupt Flag

#define DMA2D_IFSR_CTEIF   DMA2D_IFCR_CTEIF

Clears Transfer Error Interrupt Flag

#define DMA2D_IFSR_CTWIF   DMA2D_IFCR_CTWIF

Clears Transfer Watermark Interrupt Flag

#define DMA2D_ISR_CAEIF   0x00000008U

CLUT Access Error Interrupt Flag

#define DMA2D_ISR_CEIF   0x00000020U

Configuration Error Interrupt Flag

#define DMA2D_ISR_CTCIF   0x00000010U

CLUT Transfer Complete Interrupt Flag

#define DMA2D_ISR_TCIF   0x00000002U

Transfer Complete Interrupt Flag

#define DMA2D_ISR_TEIF   0x00000001U

Transfer Error Interrupt Flag

#define DMA2D_ISR_TWIF   0x00000004U

Transfer Watermark Interrupt Flag

#define DMA2D_LWR_LW   0x0000FFFFU

Line Watermark

#define DMA2D_NLR_NL   0x0000FFFFU

Number of Lines

#define DMA2D_NLR_PL   0x3FFF0000U

Pixel per Lines

#define DMA2D_OCOLR_ALPHA_1   0xFF000000U

Alpha Channel Value Mode_RGB565

#define DMA2D_OCOLR_ALPHA_3   0x00008000U

Alpha Channel Value Mode_ARGB4444

#define DMA2D_OCOLR_ALPHA_4   0x0000F000U

Alpha Channel Value

#define DMA2D_OCOLR_BLUE_1   0x000000FFU

<Mode_ARGB8888/RGB888 BLUE Value

#define DMA2D_OCOLR_BLUE_2   0x0000001FU

BLUE Value

#define DMA2D_OCOLR_BLUE_3   0x0000001FU

BLUE Value

#define DMA2D_OCOLR_BLUE_4   0x0000000FU

BLUE Value

#define DMA2D_OCOLR_GREEN_1   0x0000FF00U

GREEN Value

#define DMA2D_OCOLR_GREEN_2   0x000007E0U

GREEN Value

#define DMA2D_OCOLR_GREEN_3   0x000003E0U

GREEN Value

#define DMA2D_OCOLR_GREEN_4   0x000000F0U

GREEN Value

#define DMA2D_OCOLR_RED_1   0x00FF0000U

Red Value

#define DMA2D_OCOLR_RED_2   0x0000F800U

Red Value Mode_ARGB1555

#define DMA2D_OCOLR_RED_3   0x00007C00U

Red Value

#define DMA2D_OCOLR_RED_4   0x00000F00U

Red Value

#define DMA2D_OMAR_MA   0xFFFFFFFFU

Memory Address

#define DMA2D_OOR_LO   0x00003FFFU

Line Offset

#define DMA2D_OPFCCR_CM   0x00000007U

Color mode CM[2:0]

#define DMA2D_OPFCCR_CM_0   0x00000001U

Color mode CM bit 0

#define DMA2D_OPFCCR_CM_1   0x00000002U

Color mode CM bit 1

#define DMA2D_OPFCCR_CM_2   0x00000004U

Color mode CM bit 2

#define DMA_HIFCR_CDMEIF4   0x00000004U
#define DMA_HIFCR_CDMEIF5   0x00000100U
#define DMA_HIFCR_CDMEIF6   0x00040000U
#define DMA_HIFCR_CDMEIF7   0x01000000U
#define DMA_HIFCR_CFEIF4   0x00000001U
#define DMA_HIFCR_CFEIF5   0x00000040U
#define DMA_HIFCR_CFEIF6   0x00010000U
#define DMA_HIFCR_CFEIF7   0x00400000U
#define DMA_HIFCR_CHTIF4   0x00000010U
#define DMA_HIFCR_CHTIF5   0x00000400U
#define DMA_HIFCR_CHTIF6   0x00100000U
#define DMA_HIFCR_CHTIF7   0x04000000U
#define DMA_HIFCR_CTCIF4   0x00000020U
#define DMA_HIFCR_CTCIF5   0x00000800U
#define DMA_HIFCR_CTCIF6   0x00200000U
#define DMA_HIFCR_CTCIF7   0x08000000U
#define DMA_HIFCR_CTEIF4   0x00000008U
#define DMA_HIFCR_CTEIF5   0x00000200U
#define DMA_HIFCR_CTEIF6   0x00080000U
#define DMA_HIFCR_CTEIF7   0x02000000U
#define DMA_HISR_DMEIF4   0x00000004U
#define DMA_HISR_DMEIF5   0x00000100U
#define DMA_HISR_DMEIF6   0x00040000U
#define DMA_HISR_DMEIF7   0x01000000U
#define DMA_HISR_FEIF4   0x00000001U
#define DMA_HISR_FEIF5   0x00000040U
#define DMA_HISR_FEIF6   0x00010000U
#define DMA_HISR_FEIF7   0x00400000U
#define DMA_HISR_HTIF4   0x00000010U
#define DMA_HISR_HTIF5   0x00000400U
#define DMA_HISR_HTIF6   0x00100000U
#define DMA_HISR_HTIF7   0x04000000U
#define DMA_HISR_TCIF4   0x00000020U
#define DMA_HISR_TCIF5   0x00000800U
#define DMA_HISR_TCIF6   0x00200000U
#define DMA_HISR_TCIF7   0x08000000U
#define DMA_HISR_TEIF4   0x00000008U
#define DMA_HISR_TEIF5   0x00000200U
#define DMA_HISR_TEIF6   0x00080000U
#define DMA_HISR_TEIF7   0x02000000U
#define DMA_LIFCR_CDMEIF0   0x00000004U
#define DMA_LIFCR_CDMEIF1   0x00000100U
#define DMA_LIFCR_CDMEIF2   0x00040000U
#define DMA_LIFCR_CDMEIF3   0x01000000U
#define DMA_LIFCR_CFEIF0   0x00000001U
#define DMA_LIFCR_CFEIF1   0x00000040U
#define DMA_LIFCR_CFEIF2   0x00010000U
#define DMA_LIFCR_CFEIF3   0x00400000U
#define DMA_LIFCR_CHTIF0   0x00000010U
#define DMA_LIFCR_CHTIF1   0x00000400U
#define DMA_LIFCR_CHTIF2   0x00100000U
#define DMA_LIFCR_CHTIF3   0x04000000U
#define DMA_LIFCR_CTCIF0   0x00000020U
#define DMA_LIFCR_CTCIF1   0x00000800U
#define DMA_LIFCR_CTCIF2   0x00200000U
#define DMA_LIFCR_CTCIF3   0x08000000U
#define DMA_LIFCR_CTEIF0   0x00000008U
#define DMA_LIFCR_CTEIF1   0x00000200U
#define DMA_LIFCR_CTEIF2   0x00080000U
#define DMA_LIFCR_CTEIF3   0x02000000U
#define DMA_LISR_DMEIF0   0x00000004U
#define DMA_LISR_DMEIF1   0x00000100U
#define DMA_LISR_DMEIF2   0x00040000U
#define DMA_LISR_DMEIF3   0x01000000U
#define DMA_LISR_FEIF0   0x00000001U
#define DMA_LISR_FEIF1   0x00000040U
#define DMA_LISR_FEIF2   0x00010000U
#define DMA_LISR_FEIF3   0x00400000U
#define DMA_LISR_HTIF0   0x00000010U
#define DMA_LISR_HTIF1   0x00000400U
#define DMA_LISR_HTIF2   0x00100000U
#define DMA_LISR_HTIF3   0x04000000U
#define DMA_LISR_TCIF0   0x00000020U
#define DMA_LISR_TCIF1   0x00000800U
#define DMA_LISR_TCIF2   0x00200000U
#define DMA_LISR_TCIF3   0x08000000U
#define DMA_LISR_TEIF0   0x00000008U
#define DMA_LISR_TEIF1   0x00000200U
#define DMA_LISR_TEIF2   0x00080000U
#define DMA_LISR_TEIF3   0x02000000U
#define DMA_SxCR_CHSEL   0x0E000000U
#define DMA_SxCR_CHSEL_0   0x02000000U
#define DMA_SxCR_CHSEL_1   0x04000000U
#define DMA_SxCR_CHSEL_2   0x08000000U
#define DMA_SxCR_CIRC   0x00000100U
#define DMA_SxCR_CT   0x00080000U
#define DMA_SxCR_DBM   0x00040000U
#define DMA_SxCR_DIR   0x000000C0U
#define DMA_SxCR_DIR_0   0x00000040U
#define DMA_SxCR_DIR_1   0x00000080U
#define DMA_SxCR_DMEIE   0x00000002U
#define DMA_SxCR_EN   0x00000001U
#define DMA_SxCR_HTIE   0x00000008U
#define DMA_SxCR_MBURST   0x01800000U
#define DMA_SxCR_MBURST_0   0x00800000U
#define DMA_SxCR_MBURST_1   0x01000000U
#define DMA_SxCR_MINC   0x00000400U
#define DMA_SxCR_MSIZE   0x00006000U
#define DMA_SxCR_MSIZE_0   0x00002000U
#define DMA_SxCR_MSIZE_1   0x00004000U
#define DMA_SxCR_PBURST   0x00600000U
#define DMA_SxCR_PBURST_0   0x00200000U
#define DMA_SxCR_PBURST_1   0x00400000U
#define DMA_SxCR_PFCTRL   0x00000020U
#define DMA_SxCR_PINC   0x00000200U
#define DMA_SxCR_PINCOS   0x00008000U
#define DMA_SxCR_PL   0x00030000U
#define DMA_SxCR_PL_0   0x00010000U
#define DMA_SxCR_PL_1   0x00020000U
#define DMA_SxCR_PSIZE   0x00001800U
#define DMA_SxCR_PSIZE_0   0x00000800U
#define DMA_SxCR_PSIZE_1   0x00001000U
#define DMA_SxCR_TCIE   0x00000010U
#define DMA_SxCR_TEIE   0x00000004U
#define DMA_SxFCR_DMDIS   0x00000004U
#define DMA_SxFCR_FEIE   0x00000080U
#define DMA_SxFCR_FS   0x00000038U
#define DMA_SxFCR_FS_0   0x00000008U
#define DMA_SxFCR_FS_1   0x00000010U
#define DMA_SxFCR_FS_2   0x00000020U
#define DMA_SxFCR_FTH   0x00000003U
#define DMA_SxFCR_FTH_0   0x00000001U
#define DMA_SxFCR_FTH_1   0x00000002U
#define DMA_SxNDT   0x0000FFFFU
#define DMA_SxNDT_0   0x00000001U
#define DMA_SxNDT_1   0x00000002U
#define DMA_SxNDT_10   0x00000400U
#define DMA_SxNDT_11   0x00000800U
#define DMA_SxNDT_12   0x00001000U
#define DMA_SxNDT_13   0x00002000U
#define DMA_SxNDT_14   0x00004000U
#define DMA_SxNDT_15   0x00008000U
#define DMA_SxNDT_2   0x00000004U
#define DMA_SxNDT_3   0x00000008U
#define DMA_SxNDT_4   0x00000010U
#define DMA_SxNDT_5   0x00000020U
#define DMA_SxNDT_6   0x00000040U
#define DMA_SxNDT_7   0x00000080U
#define DMA_SxNDT_8   0x00000100U
#define DMA_SxNDT_9   0x00000200U
#define ETH_DMABMR_AAB   0x02000000U /* Address-Aligned beats */
#define ETH_DMABMR_DA   0x00000002U /* DMA arbitration scheme */
#define ETH_DMABMR_DSL   0x0000007CU /* Descriptor Skip Length */
#define ETH_DMABMR_EDE   0x00000080U /* Enhanced Descriptor Enable */
#define ETH_DMABMR_FB   0x00010000U /* Fixed Burst */
#define ETH_DMABMR_FPM   0x01000000U /* 4xPBL mode */
#define ETH_DMABMR_PBL   0x00003F00U /* Programmable burst length */
#define ETH_DMABMR_PBL_16Beat   0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_DMABMR_PBL_1Beat   0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
#define ETH_DMABMR_PBL_2Beat   0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
#define ETH_DMABMR_PBL_32Beat   0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_DMABMR_PBL_4Beat   0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_DMABMR_PBL_4xPBL_128Beat   0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
#define ETH_DMABMR_PBL_4xPBL_16Beat   0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_DMABMR_PBL_4xPBL_32Beat   0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_DMABMR_PBL_4xPBL_4Beat   0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_DMABMR_PBL_4xPBL_64Beat   0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
#define ETH_DMABMR_PBL_4xPBL_8Beat   0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_DMABMR_PBL_8Beat   0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_DMABMR_RDP   0x007E0000U /* RxDMA PBL */
#define ETH_DMABMR_RDP_16Beat   0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_DMABMR_RDP_1Beat   0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
#define ETH_DMABMR_RDP_2Beat   0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
#define ETH_DMABMR_RDP_32Beat   0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_DMABMR_RDP_4Beat   0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_DMABMR_RDP_4xPBL_128Beat   0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
#define ETH_DMABMR_RDP_4xPBL_16Beat   0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_DMABMR_RDP_4xPBL_32Beat   0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_DMABMR_RDP_4xPBL_4Beat   0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_DMABMR_RDP_4xPBL_64Beat   0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
#define ETH_DMABMR_RDP_4xPBL_8Beat   0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_DMABMR_RDP_8Beat   0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_DMABMR_RTPR   0x0000C000U /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_1_1   0x00000000U /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_2_1   0x00004000U /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_3_1   0x00008000U /* Rx Tx priority ratio */
#define ETH_DMABMR_RTPR_4_1   0x0000C000U /* Rx Tx priority ratio */
#define ETH_DMABMR_SR   0x00000001U /* Software reset */
#define ETH_DMABMR_USP   0x00800000U /* Use separate PBL */
#define ETH_DMACHRBAR_HRBAP   0xFFFFFFFFU /* Host receive buffer address pointer */
#define ETH_DMACHRDR_HRDAP   0xFFFFFFFFU /* Host receive descriptor address pointer */
#define ETH_DMACHTBAR_HTBAP   0xFFFFFFFFU /* Host transmit buffer address pointer */
#define ETH_DMACHTDR_HTDAP   0xFFFFFFFFU /* Host transmit descriptor address pointer */
#define ETH_DMAIER_AISE   0x00008000U /* Abnormal interrupt summary enable */
#define ETH_DMAIER_ERIE   0x00004000U /* Early receive interrupt enable */
#define ETH_DMAIER_ETIE   0x00000400U /* Early transmit interrupt enable */
#define ETH_DMAIER_FBEIE   0x00002000U /* Fatal bus error interrupt enable */
#define ETH_DMAIER_NISE   0x00010000U /* Normal interrupt summary enable */
#define ETH_DMAIER_RBUIE   0x00000080U /* Receive buffer unavailable interrupt enable */
#define ETH_DMAIER_RIE   0x00000040U /* Receive interrupt enable */
#define ETH_DMAIER_ROIE   0x00000010U /* Receive Overflow interrupt enable */
#define ETH_DMAIER_RPSIE   0x00000100U /* Receive process stopped interrupt enable */
#define ETH_DMAIER_RWTIE   0x00000200U /* Receive watchdog timeout interrupt enable */
#define ETH_DMAIER_TBUIE   0x00000004U /* Transmit buffer unavailable interrupt enable */
#define ETH_DMAIER_TIE   0x00000001U /* Transmit interrupt enable */
#define ETH_DMAIER_TJTIE   0x00000008U /* Transmit jabber timeout interrupt enable */
#define ETH_DMAIER_TPSIE   0x00000002U /* Transmit process stopped interrupt enable */
#define ETH_DMAIER_TUIE   0x00000020U /* Transmit Underflow interrupt enable */
#define ETH_DMAMFBOCR_MFA   0x0FFE0000U /* Number of frames missed by the application */
#define ETH_DMAMFBOCR_MFC   0x0000FFFFU /* Number of frames missed by the controller */
#define ETH_DMAMFBOCR_OFOC   0x10000000U /* Overflow bit for FIFO overflow counter */
#define ETH_DMAMFBOCR_OMFC   0x00010000U /* Overflow bit for missed frame counter */
#define ETH_DMAOMR_DFRF   0x01000000U /* Disable flushing of received frames */
#define ETH_DMAOMR_DTCEFD   0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
#define ETH_DMAOMR_FEF   0x00000080U /* Forward error frames */
#define ETH_DMAOMR_FTF   0x00100000U /* Flush transmit FIFO */
#define ETH_DMAOMR_FUGF   0x00000040U /* Forward undersized good frames */
#define ETH_DMAOMR_OSF   0x00000004U /* operate on second frame */
#define ETH_DMAOMR_RSF   0x02000000U /* Receive store and forward */
#define ETH_DMAOMR_RTC   0x00000018U /* receive threshold control */
#define ETH_DMAOMR_RTC_128Bytes   0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
#define ETH_DMAOMR_RTC_32Bytes   0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
#define ETH_DMAOMR_RTC_64Bytes   0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
#define ETH_DMAOMR_RTC_96Bytes   0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
#define ETH_DMAOMR_SR   0x00000002U /* Start/stop receive */
#define ETH_DMAOMR_ST   0x00002000U /* Start/stop transmission command */
#define ETH_DMAOMR_TSF   0x00200000U /* Transmit store and forward */
#define ETH_DMAOMR_TTC   0x0001C000U /* Transmit threshold control */
#define ETH_DMAOMR_TTC_128Bytes   0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
#define ETH_DMAOMR_TTC_16Bytes   0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
#define ETH_DMAOMR_TTC_192Bytes   0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
#define ETH_DMAOMR_TTC_24Bytes   0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
#define ETH_DMAOMR_TTC_256Bytes   0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
#define ETH_DMAOMR_TTC_32Bytes   0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
#define ETH_DMAOMR_TTC_40Bytes   0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
#define ETH_DMAOMR_TTC_64Bytes   0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
#define ETH_DMARDLAR_SRL   0xFFFFFFFFU /* Start of receive list */
#define ETH_DMARPDR_RPD   0xFFFFFFFFU /* Receive poll demand */
#define ETH_DMASR_AIS   0x00008000U /* Abnormal interrupt summary */
#define ETH_DMASR_EBS   0x03800000U /* Error bits status */
#define ETH_DMASR_EBS_DataTransfTx   0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
#define ETH_DMASR_EBS_DescAccess   0x02000000U /* Error bits 0-data buffer, 1-desc. access */
#define ETH_DMASR_EBS_ReadTransf   0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
#define ETH_DMASR_ERS   0x00004000U /* Early receive status */
#define ETH_DMASR_ETS   0x00000400U /* Early transmit status */
#define ETH_DMASR_FBES   0x00002000U /* Fatal bus error status */
#define ETH_DMASR_MMCS   0x08000000U /* MMC status */
#define ETH_DMASR_NIS   0x00010000U /* Normal interrupt summary */
#define ETH_DMASR_PMTS   0x10000000U /* PMT status */
#define ETH_DMASR_RBUS   0x00000080U /* Receive buffer unavailable status */
#define ETH_DMASR_ROS   0x00000010U /* Receive overflow status */
#define ETH_DMASR_RPS   0x000E0000U /* Receive process state */
#define ETH_DMASR_RPS_Closing   0x000A0000U /* Running - closing descriptor */
#define ETH_DMASR_RPS_Fetching   0x00020000U /* Running - fetching the Rx descriptor */
#define ETH_DMASR_RPS_Queuing   0x000E0000U /* Running - queuing the recieve frame into host memory */
#define ETH_DMASR_RPS_Stopped   0x00000000U /* Stopped - Reset or Stop Rx Command issued */
#define ETH_DMASR_RPS_Suspended   0x00080000U /* Suspended - Rx Descriptor unavailable */
#define ETH_DMASR_RPS_Waiting   0x00060000U /* Running - waiting for packet */
#define ETH_DMASR_RPSS   0x00000100U /* Receive process stopped status */
#define ETH_DMASR_RS   0x00000040U /* Receive status */
#define ETH_DMASR_RWTS   0x00000200U /* Receive watchdog timeout status */
#define ETH_DMASR_TBUS   0x00000004U /* Transmit buffer unavailable status */
#define ETH_DMASR_TJTS   0x00000008U /* Transmit jabber timeout status */
#define ETH_DMASR_TPS   0x00700000U /* Transmit process state */
#define ETH_DMASR_TPS_Closing   0x00700000U /* Running - closing Rx descriptor */
#define ETH_DMASR_TPS_Fetching   0x00100000U /* Running - fetching the Tx descriptor */
#define ETH_DMASR_TPS_Reading   0x00300000U /* Running - reading the data from host memory */
#define ETH_DMASR_TPS_Stopped   0x00000000U /* Stopped - Reset or Stop Tx Command issued */
#define ETH_DMASR_TPS_Suspended   0x00600000U /* Suspended - Tx Descriptor unavailabe */
#define ETH_DMASR_TPS_Waiting   0x00200000U /* Running - waiting for status */
#define ETH_DMASR_TPSS   0x00000002U /* Transmit process stopped status */
#define ETH_DMASR_TS   0x00000001U /* Transmit status */
#define ETH_DMASR_TSTS   0x20000000U /* Time-stamp trigger status */
#define ETH_DMASR_TUS   0x00000020U /* Transmit underflow status */
#define ETH_DMATDLAR_STL   0xFFFFFFFFU /* Start of transmit list */
#define ETH_DMATPDR_TPD   0xFFFFFFFFU /* Transmit poll demand */
#define ETH_MACA0HR_MACA0H   0x0000FFFFU /* MAC address0 high */
#define ETH_MACA0LR_MACA0L   0xFFFFFFFFU /* MAC address0 low */
#define ETH_MACA1HR_AE   0x80000000U /* Address enable */
#define ETH_MACA1HR_MACA1H   0x0000FFFFU /* MAC address1 high */
#define ETH_MACA1HR_MBC   0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
#define ETH_MACA1HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA1HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA1HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA1HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA1HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA1HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [7:0] */
#define ETH_MACA1HR_SA   0x40000000U /* Source address */
#define ETH_MACA1LR_MACA1L   0xFFFFFFFFU /* MAC address1 low */
#define ETH_MACA2HR_AE   0x80000000U /* Address enable */
#define ETH_MACA2HR_MACA2H   0x0000FFFFU /* MAC address1 high */
#define ETH_MACA2HR_MBC   0x3F000000U /* Mask byte control */
#define ETH_MACA2HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA2HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA2HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA2HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA2HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA2HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [70] */
#define ETH_MACA2HR_SA   0x40000000U /* Source address */
#define ETH_MACA2LR_MACA2L   0xFFFFFFFFU /* MAC address2 low */
#define ETH_MACA3HR_AE   0x80000000U /* Address enable */
#define ETH_MACA3HR_MACA3H   0x0000FFFFU /* MAC address3 high */
#define ETH_MACA3HR_MBC   0x3F000000U /* Mask byte control */
#define ETH_MACA3HR_MBC_HBits15_8   0x20000000U /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACA3HR_MBC_HBits7_0   0x10000000U /* Mask MAC Address high reg bits [7:0] */
#define ETH_MACA3HR_MBC_LBits15_8   0x02000000U /* Mask MAC Address low reg bits [15:8] */
#define ETH_MACA3HR_MBC_LBits23_16   0x04000000U /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACA3HR_MBC_LBits31_24   0x08000000U /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACA3HR_MBC_LBits7_0   0x01000000U /* Mask MAC Address low reg bits [70] */
#define ETH_MACA3HR_SA   0x40000000U /* Source address */
#define ETH_MACA3LR_MACA3L   0xFFFFFFFFU /* MAC address3 low */
#define ETH_MACCR_APCS   0x00000080U /* Automatic Pad/CRC stripping */
#define ETH_MACCR_BL
Value:
0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
a transmission attempt during retries after a collision: 0 =< r <2^k */
#define ETH_MACCR_BL_1   0x00000060U /* k = min (n, 1) */
#define ETH_MACCR_BL_10   0x00000000U /* k = min (n, 10) */
#define ETH_MACCR_BL_4   0x00000040U /* k = min (n, 4) */
#define ETH_MACCR_BL_8   0x00000020U /* k = min (n, 8) */
#define ETH_MACCR_CSD   0x00010000U /* Carrier sense disable (during transmission) */
#define ETH_MACCR_DC   0x00000010U /* Defferal check */
#define ETH_MACCR_DM   0x00000800U /* Duplex mode */
#define ETH_MACCR_FES   0x00004000U /* Fast ethernet speed */
#define ETH_MACCR_IFG   0x000E0000U /* Inter-frame gap */
#define ETH_MACCR_IFG_40Bit   0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
#define ETH_MACCR_IFG_48Bit   0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
#define ETH_MACCR_IFG_56Bit   0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
#define ETH_MACCR_IFG_64Bit   0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
#define ETH_MACCR_IFG_72Bit   0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
#define ETH_MACCR_IFG_80Bit   0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
#define ETH_MACCR_IFG_88Bit   0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
#define ETH_MACCR_IFG_96Bit   0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
#define ETH_MACCR_IPCO   0x00000400U /* IP Checksum offload */
#define ETH_MACCR_JD   0x00400000U /* Jabber disable */
#define ETH_MACCR_LM   0x00001000U /* loopback mode */
#define ETH_MACCR_RD   0x00000200U /* Retry disable */
#define ETH_MACCR_RE   0x00000004U /* Receiver enable */
#define ETH_MACCR_ROD   0x00002000U /* Receive own disable */
#define ETH_MACCR_TE   0x00000008U /* Transmitter enable */
#define ETH_MACCR_WD   0x00800000U /* Watchdog disable */
#define ETH_MACFCR_FCBBPA   0x00000001U /* Flow control busy/backpressure activate */
#define ETH_MACFCR_PLT   0x00000030U /* Pause low threshold: 4 cases */
#define ETH_MACFCR_PLT_Minus144   0x00000020U /* Pause time minus 144 slot times */
#define ETH_MACFCR_PLT_Minus256   0x00000030U /* Pause time minus 256 slot times */
#define ETH_MACFCR_PLT_Minus28   0x00000010U /* Pause time minus 28 slot times */
#define ETH_MACFCR_PLT_Minus4   0x00000000U /* Pause time minus 4 slot times */
#define ETH_MACFCR_PT   0xFFFF0000U /* Pause time */
#define ETH_MACFCR_RFCE   0x00000004U /* Receive flow control enable */
#define ETH_MACFCR_TFCE   0x00000002U /* Transmit flow control enable */
#define ETH_MACFCR_UPFD   0x00000008U /* Unicast pause frame detect */
#define ETH_MACFCR_ZQPD   0x00000080U /* Zero-quanta pause disable */
#define ETH_MACFFR_BFD   0x00000020U /* Broadcast frame disable */
#define ETH_MACFFR_DAIF   0x00000008U /* DA Inverse filtering */
#define ETH_MACFFR_HM   0x00000004U /* Hash multicast */
#define ETH_MACFFR_HPF   0x00000400U /* Hash or perfect filter */
#define ETH_MACFFR_HU   0x00000002U /* Hash unicast */
#define ETH_MACFFR_PAM   0x00000010U /* Pass all mutlicast */
#define ETH_MACFFR_PCF   0x000000C0U /* Pass control frames: 3 cases */
#define ETH_MACFFR_PCF_BlockAll   0x00000040U /* MAC filters all control frames from reaching the application */
#define ETH_MACFFR_PCF_ForwardAll   0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_MACFFR_PCF_ForwardPassedAddrFilter   0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
#define ETH_MACFFR_PM   0x00000001U /* Promiscuous mode */
#define ETH_MACFFR_RA   0x80000000U /* Receive all */
#define ETH_MACFFR_SAF   0x00000200U /* Source address filter enable */
#define ETH_MACFFR_SAIF   0x00000100U /* SA inverse filtering */
#define ETH_MACHTHR_HTH   0xFFFFFFFFU /* Hash table high */
#define ETH_MACHTLR_HTL   0xFFFFFFFFU /* Hash table low */
#define ETH_MACIMR_PMTIM   0x00000008U /* PMT interrupt mask */
#define ETH_MACIMR_TSTIM   0x00000200U /* Time stamp trigger interrupt mask */
#define ETH_MACMIIAR_CR   0x0000001CU /* CR clock range: 6 cases */
#define ETH_MACMIIAR_CR_Div102   0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
#define ETH_MACMIIAR_CR_Div16   0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
#define ETH_MACMIIAR_CR_Div26   0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
#define ETH_MACMIIAR_CR_Div42   0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
#define ETH_MACMIIAR_CR_Div62   0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
#define ETH_MACMIIAR_MB   0x00000001U /* MII busy */
#define ETH_MACMIIAR_MR   0x000007C0U /* MII register in the selected PHY */
#define ETH_MACMIIAR_MW   0x00000002U /* MII write */
#define ETH_MACMIIAR_PA   0x0000F800U /* Physical layer address */
#define ETH_MACMIIDR_MD   0x0000FFFFU /* MII data: read/write data from/to PHY */
#define ETH_MACPMTCSR_GU   0x00000200U /* Global Unicast */
#define ETH_MACPMTCSR_MPE   0x00000002U /* Magic Packet Enable */
#define ETH_MACPMTCSR_MPR   0x00000020U /* Magic Packet Received */
#define ETH_MACPMTCSR_PD   0x00000001U /* Power Down */
#define ETH_MACPMTCSR_WFE   0x00000004U /* Wake-Up Frame Enable */
#define ETH_MACPMTCSR_WFFRPR   0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
#define ETH_MACPMTCSR_WFR   0x00000040U /* Wake-Up Frame Received */
#define ETH_MACRWUFFR_D   0xFFFFFFFFU /* Wake-up frame filter register data */
#define ETH_MACSR_MMCS   0x00000010U /* MMC status */
#define ETH_MACSR_MMCTS   0x00000040U /* MMC transmit status */
#define ETH_MACSR_MMMCRS   0x00000020U /* MMC receive status */
#define ETH_MACSR_PMTS   0x00000008U /* PMT status */
#define ETH_MACSR_TSTS   0x00000200U /* Time stamp trigger status */
#define ETH_MACVLANTR_VLANTC   0x00010000U /* 12-bit VLAN tag comparison */
#define ETH_MACVLANTR_VLANTI   0x0000FFFFU /* VLAN tag identifier (for receive frames) */
#define ETH_MMCCR_CR   0x00000001U /* Counters Reset */
#define ETH_MMCCR_CSR   0x00000002U /* Counter Stop Rollover */
#define ETH_MMCCR_MCF   0x00000008U /* MMC Counter Freeze */
#define ETH_MMCCR_MCFHP   0x00000020U /* MMC counter Full-Half preset */
#define ETH_MMCCR_MCP   0x00000010U /* MMC counter preset */
#define ETH_MMCCR_ROR   0x00000004U /* Reset on Read */
#define ETH_MMCRFAECR_RFAEC   0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
#define ETH_MMCRFCECR_RFCEC   0xFFFFFFFFU /* Number of frames received with CRC error. */
#define ETH_MMCRGUFCR_RGUFC   0xFFFFFFFFU /* Number of good unicast frames received. */
#define ETH_MMCRIMR_RFAEM   0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRIMR_RFCEM   0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
#define ETH_MMCRIMR_RGUFM   0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMCRIR_RFAES   0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRIR_RFCES   0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
#define ETH_MMCRIR_RGUFS   0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMCTGFCR_TGFC   0xFFFFFFFFU /* Number of good frames transmitted. */
#define ETH_MMCTGFMSCCR_TGFMSCC   0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
#define ETH_MMCTGFSCCR_TGFSCC   0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
#define ETH_MMCTIMR_TGFM   0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
#define ETH_MMCTIMR_TGFMSCM   0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
#define ETH_MMCTIMR_TGFSCM   0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
#define ETH_MMCTIR_TGFMSCS   0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
#define ETH_MMCTIR_TGFS   0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
#define ETH_MMCTIR_TGFSCS   0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
#define ETH_PTPSSIR_STSSI   0x000000FFU /* System time Sub-second increment value */
#define ETH_PTPTSAR_TSA   0xFFFFFFFFU /* Time stamp addend */
#define ETH_PTPTSCR_TSARU   0x00000020U /* Addend register update */
#define ETH_PTPTSCR_TSCNT   0x00030000U /* Time stamp clock node type */
#define ETH_PTPTSCR_TSE   0x00000001U /* Time stamp enable */
#define ETH_PTPTSCR_TSFCU   0x00000002U /* Time stamp fine or coarse update */
#define ETH_PTPTSCR_TSITE   0x00000010U /* Time stamp interrupt trigger enable */
#define ETH_PTPTSCR_TSSTI   0x00000004U /* Time stamp initialize */
#define ETH_PTPTSCR_TSSTU   0x00000008U /* Time stamp update */
#define ETH_PTPTSHR_STS   0xFFFFFFFFU /* System Time second */
#define ETH_PTPTSHUR_TSUS   0xFFFFFFFFU /* Time stamp update seconds */
#define ETH_PTPTSLR_STPNS   0x80000000U /* System Time Positive or negative time */
#define ETH_PTPTSLR_STSS   0x7FFFFFFFU /* System Time sub-seconds */
#define ETH_PTPTSLUR_TSUPNS   0x80000000U /* Time stamp update Positive or negative time */
#define ETH_PTPTSLUR_TSUSS   0x7FFFFFFFU /* Time stamp update sub-seconds */
#define ETH_PTPTSSR_TSPTPPSV2E   0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
#define ETH_PTPTSSR_TSSARFE   0x00000100U /* Time stamp snapshot for all received frames enable */
#define ETH_PTPTSSR_TSSEME   0x00004000U /* Time stamp snapshot for event message enable */
#define ETH_PTPTSSR_TSSIPV4FE   0x00002000U /* Time stamp snapshot for IPv4 frames enable */
#define ETH_PTPTSSR_TSSIPV6FE   0x00001000U /* Time stamp snapshot for IPv6 frames enable */
#define ETH_PTPTSSR_TSSMRME   0x00008000U /* Time stamp snapshot for message relevant to master enable */
#define ETH_PTPTSSR_TSSO   0x00000010U /* Time stamp seconds overflow */
#define ETH_PTPTSSR_TSSPTPOEFE   0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
#define ETH_PTPTSSR_TSSSR   0x00000200U /* Time stamp Sub-seconds rollover */
#define ETH_PTPTSSR_TSTTR   0x00000020U /* Time stamp target time reached */
#define ETH_PTPTTHR_TTSH   0xFFFFFFFFU /* Target time stamp high */
#define ETH_PTPTTLR_TTSL   0xFFFFFFFFU /* Target time stamp low */
#define EXTI_EMR_EM0   EXTI_EMR_MR0
#define EXTI_EMR_EM1   EXTI_EMR_MR1
#define EXTI_EMR_EM10   EXTI_EMR_MR10
#define EXTI_EMR_EM11   EXTI_EMR_MR11
#define EXTI_EMR_EM12   EXTI_EMR_MR12
#define EXTI_EMR_EM13   EXTI_EMR_MR13
#define EXTI_EMR_EM14   EXTI_EMR_MR14
#define EXTI_EMR_EM15   EXTI_EMR_MR15
#define EXTI_EMR_EM16   EXTI_EMR_MR16
#define EXTI_EMR_EM17   EXTI_EMR_MR17
#define EXTI_EMR_EM18   EXTI_EMR_MR18
#define EXTI_EMR_EM19   EXTI_EMR_MR19
#define EXTI_EMR_EM2   EXTI_EMR_MR2
#define EXTI_EMR_EM20   EXTI_EMR_MR20
#define EXTI_EMR_EM21   EXTI_EMR_MR21
#define EXTI_EMR_EM22   EXTI_EMR_MR22
#define EXTI_EMR_EM23   EXTI_EMR_MR23
#define EXTI_EMR_EM3   EXTI_EMR_MR3
#define EXTI_EMR_EM4   EXTI_EMR_MR4
#define EXTI_EMR_EM5   EXTI_EMR_MR5
#define EXTI_EMR_EM6   EXTI_EMR_MR6
#define EXTI_EMR_EM7   EXTI_EMR_MR7
#define EXTI_EMR_EM8   EXTI_EMR_MR8
#define EXTI_EMR_EM9   EXTI_EMR_MR9
#define EXTI_EMR_MR0   0x00000001U

Event Mask on line 0

#define EXTI_EMR_MR1   0x00000002U

Event Mask on line 1

#define EXTI_EMR_MR10   0x00000400U

Event Mask on line 10

#define EXTI_EMR_MR11   0x00000800U

Event Mask on line 11

#define EXTI_EMR_MR12   0x00001000U

Event Mask on line 12

#define EXTI_EMR_MR13   0x00002000U

Event Mask on line 13

#define EXTI_EMR_MR14   0x00004000U

Event Mask on line 14

#define EXTI_EMR_MR15   0x00008000U

Event Mask on line 15

#define EXTI_EMR_MR16   0x00010000U

Event Mask on line 16

#define EXTI_EMR_MR17   0x00020000U

Event Mask on line 17

#define EXTI_EMR_MR18   0x00040000U

Event Mask on line 18

#define EXTI_EMR_MR19   0x00080000U

Event Mask on line 19

#define EXTI_EMR_MR2   0x00000004U

Event Mask on line 2

#define EXTI_EMR_MR20   0x00100000U

Event Mask on line 20

#define EXTI_EMR_MR21   0x00200000U

Event Mask on line 21

#define EXTI_EMR_MR22   0x00400000U

Event Mask on line 22

#define EXTI_EMR_MR23   0x00800000U

Event Mask on line 23

#define EXTI_EMR_MR3   0x00000008U

Event Mask on line 3

#define EXTI_EMR_MR4   0x00000010U

Event Mask on line 4

#define EXTI_EMR_MR5   0x00000020U

Event Mask on line 5

#define EXTI_EMR_MR6   0x00000040U

Event Mask on line 6

#define EXTI_EMR_MR7   0x00000080U

Event Mask on line 7

#define EXTI_EMR_MR8   0x00000100U

Event Mask on line 8

#define EXTI_EMR_MR9   0x00000200U

Event Mask on line 9

#define EXTI_FTSR_TR0   0x00000001U

Falling trigger event configuration bit of line 0

#define EXTI_FTSR_TR1   0x00000002U

Falling trigger event configuration bit of line 1

#define EXTI_FTSR_TR10   0x00000400U

Falling trigger event configuration bit of line 10

#define EXTI_FTSR_TR11   0x00000800U

Falling trigger event configuration bit of line 11

#define EXTI_FTSR_TR12   0x00001000U

Falling trigger event configuration bit of line 12

#define EXTI_FTSR_TR13   0x00002000U

Falling trigger event configuration bit of line 13

#define EXTI_FTSR_TR14   0x00004000U

Falling trigger event configuration bit of line 14

#define EXTI_FTSR_TR15   0x00008000U

Falling trigger event configuration bit of line 15

#define EXTI_FTSR_TR16   0x00010000U

Falling trigger event configuration bit of line 16

#define EXTI_FTSR_TR17   0x00020000U

Falling trigger event configuration bit of line 17

#define EXTI_FTSR_TR18   0x00040000U

Falling trigger event configuration bit of line 18

#define EXTI_FTSR_TR19   0x00080000U

Falling trigger event configuration bit of line 19

#define EXTI_FTSR_TR2   0x00000004U

Falling trigger event configuration bit of line 2

#define EXTI_FTSR_TR20   0x00100000U

Falling trigger event configuration bit of line 20

#define EXTI_FTSR_TR21   0x00200000U

Falling trigger event configuration bit of line 21

#define EXTI_FTSR_TR22   0x00400000U

Falling trigger event configuration bit of line 22

#define EXTI_FTSR_TR23   0x00800000U

Falling trigger event configuration bit of line 23

#define EXTI_FTSR_TR3   0x00000008U

Falling trigger event configuration bit of line 3

#define EXTI_FTSR_TR4   0x00000010U

Falling trigger event configuration bit of line 4

#define EXTI_FTSR_TR5   0x00000020U

Falling trigger event configuration bit of line 5

#define EXTI_FTSR_TR6   0x00000040U

Falling trigger event configuration bit of line 6

#define EXTI_FTSR_TR7   0x00000080U

Falling trigger event configuration bit of line 7

#define EXTI_FTSR_TR8   0x00000100U

Falling trigger event configuration bit of line 8

#define EXTI_FTSR_TR9   0x00000200U

Falling trigger event configuration bit of line 9

#define EXTI_IMR_IM   0x00FFFFFFU

Interrupt Mask All

#define EXTI_IMR_IM0   EXTI_IMR_MR0
#define EXTI_IMR_IM1   EXTI_IMR_MR1
#define EXTI_IMR_IM10   EXTI_IMR_MR10
#define EXTI_IMR_IM11   EXTI_IMR_MR11
#define EXTI_IMR_IM12   EXTI_IMR_MR12
#define EXTI_IMR_IM13   EXTI_IMR_MR13
#define EXTI_IMR_IM14   EXTI_IMR_MR14
#define EXTI_IMR_IM15   EXTI_IMR_MR15
#define EXTI_IMR_IM16   EXTI_IMR_MR16
#define EXTI_IMR_IM17   EXTI_IMR_MR17
#define EXTI_IMR_IM18   EXTI_IMR_MR18
#define EXTI_IMR_IM19   EXTI_IMR_MR19
#define EXTI_IMR_IM2   EXTI_IMR_MR2
#define EXTI_IMR_IM20   EXTI_IMR_MR20
#define EXTI_IMR_IM21   EXTI_IMR_MR21
#define EXTI_IMR_IM22   EXTI_IMR_MR22
#define EXTI_IMR_IM23   EXTI_IMR_MR23
#define EXTI_IMR_IM3   EXTI_IMR_MR3
#define EXTI_IMR_IM4   EXTI_IMR_MR4
#define EXTI_IMR_IM5   EXTI_IMR_MR5
#define EXTI_IMR_IM6   EXTI_IMR_MR6
#define EXTI_IMR_IM7   EXTI_IMR_MR7
#define EXTI_IMR_IM8   EXTI_IMR_MR8
#define EXTI_IMR_IM9   EXTI_IMR_MR9
#define EXTI_IMR_MR0   0x00000001U

Interrupt Mask on line 0

#define EXTI_IMR_MR1   0x00000002U

Interrupt Mask on line 1

#define EXTI_IMR_MR10   0x00000400U

Interrupt Mask on line 10

#define EXTI_IMR_MR11   0x00000800U

Interrupt Mask on line 11

#define EXTI_IMR_MR12   0x00001000U

Interrupt Mask on line 12

#define EXTI_IMR_MR13   0x00002000U

Interrupt Mask on line 13

#define EXTI_IMR_MR14   0x00004000U

Interrupt Mask on line 14

#define EXTI_IMR_MR15   0x00008000U

Interrupt Mask on line 15

#define EXTI_IMR_MR16   0x00010000U

Interrupt Mask on line 16

#define EXTI_IMR_MR17   0x00020000U

Interrupt Mask on line 17

#define EXTI_IMR_MR18   0x00040000U

Interrupt Mask on line 18

#define EXTI_IMR_MR19   0x00080000U

Interrupt Mask on line 19

#define EXTI_IMR_MR2   0x00000004U

Interrupt Mask on line 2

#define EXTI_IMR_MR20   0x00100000U

Interrupt Mask on line 20

#define EXTI_IMR_MR21   0x00200000U

Interrupt Mask on line 21

#define EXTI_IMR_MR22   0x00400000U

Interrupt Mask on line 22

#define EXTI_IMR_MR23   0x00800000U

Interrupt Mask on line 23

#define EXTI_IMR_MR3   0x00000008U

Interrupt Mask on line 3

#define EXTI_IMR_MR4   0x00000010U

Interrupt Mask on line 4

#define EXTI_IMR_MR5   0x00000020U

Interrupt Mask on line 5

#define EXTI_IMR_MR6   0x00000040U

Interrupt Mask on line 6

#define EXTI_IMR_MR7   0x00000080U

Interrupt Mask on line 7

#define EXTI_IMR_MR8   0x00000100U

Interrupt Mask on line 8

#define EXTI_IMR_MR9   0x00000200U

Interrupt Mask on line 9

#define EXTI_PR_PR0   0x00000001U

Pending bit for line 0

#define EXTI_PR_PR1   0x00000002U

Pending bit for line 1

#define EXTI_PR_PR10   0x00000400U

Pending bit for line 10

#define EXTI_PR_PR11   0x00000800U

Pending bit for line 11

#define EXTI_PR_PR12   0x00001000U

Pending bit for line 12

#define EXTI_PR_PR13   0x00002000U

Pending bit for line 13

#define EXTI_PR_PR14   0x00004000U

Pending bit for line 14

#define EXTI_PR_PR15   0x00008000U

Pending bit for line 15

#define EXTI_PR_PR16   0x00010000U

Pending bit for line 16

#define EXTI_PR_PR17   0x00020000U

Pending bit for line 17

#define EXTI_PR_PR18   0x00040000U

Pending bit for line 18

#define EXTI_PR_PR19   0x00080000U

Pending bit for line 19

#define EXTI_PR_PR2   0x00000004U

Pending bit for line 2

#define EXTI_PR_PR20   0x00100000U

Pending bit for line 20

#define EXTI_PR_PR21   0x00200000U

Pending bit for line 21

#define EXTI_PR_PR22   0x00400000U

Pending bit for line 22

#define EXTI_PR_PR23   0x00800000U

Pending bit for line 23

#define EXTI_PR_PR3   0x00000008U

Pending bit for line 3

#define EXTI_PR_PR4   0x00000010U

Pending bit for line 4

#define EXTI_PR_PR5   0x00000020U

Pending bit for line 5

#define EXTI_PR_PR6   0x00000040U

Pending bit for line 6

#define EXTI_PR_PR7   0x00000080U

Pending bit for line 7

#define EXTI_PR_PR8   0x00000100U

Pending bit for line 8

#define EXTI_PR_PR9   0x00000200U

Pending bit for line 9

#define EXTI_RTSR_TR0   0x00000001U

Rising trigger event configuration bit of line 0

#define EXTI_RTSR_TR1   0x00000002U

Rising trigger event configuration bit of line 1

#define EXTI_RTSR_TR10   0x00000400U

Rising trigger event configuration bit of line 10

#define EXTI_RTSR_TR11   0x00000800U

Rising trigger event configuration bit of line 11

#define EXTI_RTSR_TR12   0x00001000U

Rising trigger event configuration bit of line 12

#define EXTI_RTSR_TR13   0x00002000U

Rising trigger event configuration bit of line 13

#define EXTI_RTSR_TR14   0x00004000U

Rising trigger event configuration bit of line 14

#define EXTI_RTSR_TR15   0x00008000U

Rising trigger event configuration bit of line 15

#define EXTI_RTSR_TR16   0x00010000U

Rising trigger event configuration bit of line 16

#define EXTI_RTSR_TR17   0x00020000U

Rising trigger event configuration bit of line 17

#define EXTI_RTSR_TR18   0x00040000U

Rising trigger event configuration bit of line 18

#define EXTI_RTSR_TR19   0x00080000U

Rising trigger event configuration bit of line 19

#define EXTI_RTSR_TR2   0x00000004U

Rising trigger event configuration bit of line 2

#define EXTI_RTSR_TR20   0x00100000U

Rising trigger event configuration bit of line 20

#define EXTI_RTSR_TR21   0x00200000U

Rising trigger event configuration bit of line 21

#define EXTI_RTSR_TR22   0x00400000U

Rising trigger event configuration bit of line 22

#define EXTI_RTSR_TR23   0x00800000U

Rising trigger event configuration bit of line 23

#define EXTI_RTSR_TR3   0x00000008U

Rising trigger event configuration bit of line 3

#define EXTI_RTSR_TR4   0x00000010U

Rising trigger event configuration bit of line 4

#define EXTI_RTSR_TR5   0x00000020U

Rising trigger event configuration bit of line 5

#define EXTI_RTSR_TR6   0x00000040U

Rising trigger event configuration bit of line 6

#define EXTI_RTSR_TR7   0x00000080U

Rising trigger event configuration bit of line 7

#define EXTI_RTSR_TR8   0x00000100U

Rising trigger event configuration bit of line 8

#define EXTI_RTSR_TR9   0x00000200U

Rising trigger event configuration bit of line 9

#define EXTI_SWIER_SWIER0   0x00000001U

Software Interrupt on line 0

#define EXTI_SWIER_SWIER1   0x00000002U

Software Interrupt on line 1

#define EXTI_SWIER_SWIER10   0x00000400U

Software Interrupt on line 10

#define EXTI_SWIER_SWIER11   0x00000800U

Software Interrupt on line 11

#define EXTI_SWIER_SWIER12   0x00001000U

Software Interrupt on line 12

#define EXTI_SWIER_SWIER13   0x00002000U

Software Interrupt on line 13

#define EXTI_SWIER_SWIER14   0x00004000U

Software Interrupt on line 14

#define EXTI_SWIER_SWIER15   0x00008000U

Software Interrupt on line 15

#define EXTI_SWIER_SWIER16   0x00010000U

Software Interrupt on line 16

#define EXTI_SWIER_SWIER17   0x00020000U

Software Interrupt on line 17

#define EXTI_SWIER_SWIER18   0x00040000U

Software Interrupt on line 18

#define EXTI_SWIER_SWIER19   0x00080000U

Software Interrupt on line 19

#define EXTI_SWIER_SWIER2   0x00000004U

Software Interrupt on line 2

#define EXTI_SWIER_SWIER20   0x00100000U

Software Interrupt on line 20

#define EXTI_SWIER_SWIER21   0x00200000U

Software Interrupt on line 21

#define EXTI_SWIER_SWIER22   0x00400000U

Software Interrupt on line 22

#define EXTI_SWIER_SWIER23   0x00800000U

Software Interrupt on line 23

#define EXTI_SWIER_SWIER3   0x00000008U

Software Interrupt on line 3

#define EXTI_SWIER_SWIER4   0x00000010U

Software Interrupt on line 4

#define EXTI_SWIER_SWIER5   0x00000020U

Software Interrupt on line 5

#define EXTI_SWIER_SWIER6   0x00000040U

Software Interrupt on line 6

#define EXTI_SWIER_SWIER7   0x00000080U

Software Interrupt on line 7

#define EXTI_SWIER_SWIER8   0x00000100U

Software Interrupt on line 8

#define EXTI_SWIER_SWIER9   0x00000200U

Software Interrupt on line 9

#define FLASH_ACR_ARTEN   0x00000200U
#define FLASH_ACR_ARTRST   0x00000800U
#define FLASH_ACR_LATENCY   0x0000000FU
#define FLASH_ACR_LATENCY_0WS   0x00000000U
#define FLASH_ACR_LATENCY_10WS   0x0000000AU
#define FLASH_ACR_LATENCY_11WS   0x0000000BU
#define FLASH_ACR_LATENCY_12WS   0x0000000CU
#define FLASH_ACR_LATENCY_13WS   0x0000000DU
#define FLASH_ACR_LATENCY_14WS   0x0000000EU
#define FLASH_ACR_LATENCY_15WS   0x0000000FU
#define FLASH_ACR_LATENCY_1WS   0x00000001U
#define FLASH_ACR_LATENCY_2WS   0x00000002U
#define FLASH_ACR_LATENCY_3WS   0x00000003U
#define FLASH_ACR_LATENCY_4WS   0x00000004U
#define FLASH_ACR_LATENCY_5WS   0x00000005U
#define FLASH_ACR_LATENCY_6WS   0x00000006U
#define FLASH_ACR_LATENCY_7WS   0x00000007U
#define FLASH_ACR_LATENCY_8WS   0x00000008U
#define FLASH_ACR_LATENCY_9WS   0x00000009U
#define FLASH_ACR_PRFTEN   0x00000100U
#define FLASH_CR_EOPIE   0x01000000U
#define FLASH_CR_ERRIE   0x02000000U
#define FLASH_CR_LOCK   0x80000000U
#define FLASH_CR_MER   0x00000004U
#define FLASH_CR_PG   0x00000001U
#define FLASH_CR_PSIZE   0x00000300U
#define FLASH_CR_PSIZE_0   0x00000100U
#define FLASH_CR_PSIZE_1   0x00000200U
#define FLASH_CR_SER   0x00000002U
#define FLASH_CR_SNB   0x00000078U
#define FLASH_CR_SNB_0   0x00000008U
#define FLASH_CR_SNB_1   0x00000010U
#define FLASH_CR_SNB_2   0x00000020U
#define FLASH_CR_SNB_3   0x00000040U
#define FLASH_CR_STRT   0x00010000U
#define FLASH_OPTCR1_BOOT_ADD0   0x0000FFFFU
#define FLASH_OPTCR1_BOOT_ADD1   0xFFFF0000U
#define FLASH_OPTCR_BOR_LEV   0x0000000CU
#define FLASH_OPTCR_BOR_LEV_0   0x00000004U
#define FLASH_OPTCR_BOR_LEV_1   0x00000008U
#define FLASH_OPTCR_IWDG_STDBY   0x40000000U
#define FLASH_OPTCR_IWDG_STOP   0x80000000U
#define FLASH_OPTCR_IWDG_SW   0x00000020U
#define FLASH_OPTCR_nRST_STDBY   0x00000080U
#define FLASH_OPTCR_nRST_STOP   0x00000040U
#define FLASH_OPTCR_nWRP   0x00FF0000U
#define FLASH_OPTCR_nWRP_0   0x00010000U
#define FLASH_OPTCR_nWRP_1   0x00020000U
#define FLASH_OPTCR_nWRP_2   0x00040000U
#define FLASH_OPTCR_nWRP_3   0x00080000U
#define FLASH_OPTCR_nWRP_4   0x00100000U
#define FLASH_OPTCR_nWRP_5   0x00200000U
#define FLASH_OPTCR_nWRP_6   0x00400000U
#define FLASH_OPTCR_nWRP_7   0x00800000U
#define FLASH_OPTCR_OPTLOCK   0x00000001U
#define FLASH_OPTCR_OPTSTRT   0x00000002U
#define FLASH_OPTCR_RDP   0x0000FF00U
#define FLASH_OPTCR_RDP_0   0x00000100U
#define FLASH_OPTCR_RDP_1   0x00000200U
#define FLASH_OPTCR_RDP_2   0x00000400U
#define FLASH_OPTCR_RDP_3   0x00000800U
#define FLASH_OPTCR_RDP_4   0x00001000U
#define FLASH_OPTCR_RDP_5   0x00002000U
#define FLASH_OPTCR_RDP_6   0x00004000U
#define FLASH_OPTCR_RDP_7   0x00008000U
#define FLASH_OPTCR_WWDG_SW   0x00000010U
#define FLASH_SECTOR_TOTAL   8
#define FLASH_SR_BSY   0x00010000U
#define FLASH_SR_EOP   0x00000001U
#define FLASH_SR_ERSERR   0x00000080U
#define FLASH_SR_OPERR   0x00000002U
#define FLASH_SR_PGAERR   0x00000020U
#define FLASH_SR_PGPERR   0x00000040U
#define FLASH_SR_WRPERR   0x00000010U
#define FMC_BCR1_ASYNCWAIT   0x00008000U

Asynchronous wait

#define FMC_BCR1_BURSTEN   0x00000100U

Burst enable bit

#define FMC_BCR1_CBURSTRW   0x00080000U

Write burst enable

#define FMC_BCR1_CCLKEN   0x00100000U

Continous clock enable

#define FMC_BCR1_CPSIZE   0x00070000U

CRAM page size

#define FMC_BCR1_CPSIZE_0   0x00010000U

Bit 0

#define FMC_BCR1_CPSIZE_1   0x00020000U

Bit 1

#define FMC_BCR1_CPSIZE_2   0x00040000U

Bit 2

#define FMC_BCR1_EXTMOD   0x00004000U

Extended mode enable

#define FMC_BCR1_FACCEN   0x00000040U

Flash access enable

#define FMC_BCR1_MBKEN   0x00000001U

Memory bank enable bit

#define FMC_BCR1_MTYP   0x0000000CU

MTYP[1:0] bits (Memory type)

#define FMC_BCR1_MTYP_0   0x00000004U

Bit 0

#define FMC_BCR1_MTYP_1   0x00000008U

Bit 1

#define FMC_BCR1_MUXEN   0x00000002U

Address/data multiplexing enable bit

#define FMC_BCR1_MWID   0x00000030U

MWID[1:0] bits (Memory data bus width)

#define FMC_BCR1_MWID_0   0x00000010U

Bit 0

#define FMC_BCR1_MWID_1   0x00000020U

Bit 1

#define FMC_BCR1_WAITCFG   0x00000800U

Wait timing configuration

#define FMC_BCR1_WAITEN   0x00002000U

Wait enable bit

#define FMC_BCR1_WAITPOL   0x00000200U

Wait signal polarity bit

#define FMC_BCR1_WFDIS   0x00200000U

Write FIFO Disable

#define FMC_BCR1_WRAPMOD   0x00000400U

Wrapped burst mode support

#define FMC_BCR1_WREN   0x00001000U

Write enable bit

#define FMC_BCR2_ASYNCWAIT   0x00008000U

Asynchronous wait

#define FMC_BCR2_BURSTEN   0x00000100U

Burst enable bit

#define FMC_BCR2_CBURSTRW   0x00080000U

Write burst enable

#define FMC_BCR2_CPSIZE   0x00070000U

CRAM page size

#define FMC_BCR2_CPSIZE_0   0x00010000U

Bit 0

#define FMC_BCR2_CPSIZE_1   0x00020000U

Bit 1

#define FMC_BCR2_CPSIZE_2   0x00040000U

Bit 2

#define FMC_BCR2_EXTMOD   0x00004000U

Extended mode enable

#define FMC_BCR2_FACCEN   0x00000040U

Flash access enable

#define FMC_BCR2_MBKEN   0x00000001U

Memory bank enable bit

#define FMC_BCR2_MTYP   0x0000000CU

MTYP[1:0] bits (Memory type)

#define FMC_BCR2_MTYP_0   0x00000004U

Bit 0

#define FMC_BCR2_MTYP_1   0x00000008U

Bit 1

#define FMC_BCR2_MUXEN   0x00000002U

Address/data multiplexing enable bit

#define FMC_BCR2_MWID   0x00000030U

MWID[1:0] bits (Memory data bus width)

#define FMC_BCR2_MWID_0   0x00000010U

Bit 0

#define FMC_BCR2_MWID_1   0x00000020U

Bit 1

#define FMC_BCR2_WAITCFG   0x00000800U

Wait timing configuration

#define FMC_BCR2_WAITEN   0x00002000U

Wait enable bit

#define FMC_BCR2_WAITPOL   0x00000200U

Wait signal polarity bit

#define FMC_BCR2_WRAPMOD   0x00000400U

Wrapped burst mode support

#define FMC_BCR2_WREN   0x00001000U

Write enable bit

#define FMC_BCR3_ASYNCWAIT   0x00008000U

Asynchronous wait

#define FMC_BCR3_BURSTEN   0x00000100U

Burst enable bit

#define FMC_BCR3_CBURSTRW   0x00080000U

Write burst enable

#define FMC_BCR3_CPSIZE   0x00070000U

CRAM page size

#define FMC_BCR3_CPSIZE_0   0x00010000U

Bit 0

#define FMC_BCR3_CPSIZE_1   0x00020000U

Bit 1

#define FMC_BCR3_CPSIZE_2   0x00040000U

Bit 2

#define FMC_BCR3_EXTMOD   0x00004000U

Extended mode enable

#define FMC_BCR3_FACCEN   0x00000040U

Flash access enable

#define FMC_BCR3_MBKEN   0x00000001U

Memory bank enable bit

#define FMC_BCR3_MTYP   0x0000000CU

MTYP[1:0] bits (Memory type)

#define FMC_BCR3_MTYP_0   0x00000004U

Bit 0

#define FMC_BCR3_MTYP_1   0x00000008U

Bit 1

#define FMC_BCR3_MUXEN   0x00000002U

Address/data multiplexing enable bit

#define FMC_BCR3_MWID   0x00000030U

MWID[1:0] bits (Memory data bus width)

#define FMC_BCR3_MWID_0   0x00000010U

Bit 0

#define FMC_BCR3_MWID_1   0x00000020U

Bit 1

#define FMC_BCR3_WAITCFG   0x00000800U

Wait timing configuration

#define FMC_BCR3_WAITEN   0x00002000U

Wait enable bit

#define FMC_BCR3_WAITPOL   0x00000200U

Wait signal polarity bit

#define FMC_BCR3_WRAPMOD   0x00000400U

Wrapped burst mode support

#define FMC_BCR3_WREN   0x00001000U

Write enable bit

#define FMC_BCR4_ASYNCWAIT   0x00008000U

Asynchronous wait

#define FMC_BCR4_BURSTEN   0x00000100U

Burst enable bit

#define FMC_BCR4_CBURSTRW   0x00080000U

Write burst enable

#define FMC_BCR4_CPSIZE   0x00070000U

CRAM page size

#define FMC_BCR4_CPSIZE_0   0x00010000U

Bit 0

#define FMC_BCR4_CPSIZE_1   0x00020000U

Bit 1

#define FMC_BCR4_CPSIZE_2   0x00040000U

Bit 2

#define FMC_BCR4_EXTMOD   0x00004000U

Extended mode enable

#define FMC_BCR4_FACCEN   0x00000040U

Flash access enable

#define FMC_BCR4_MBKEN   0x00000001U

Memory bank enable bit

#define FMC_BCR4_MTYP   0x0000000CU

MTYP[1:0] bits (Memory type)

#define FMC_BCR4_MTYP_0   0x00000004U

Bit 0

#define FMC_BCR4_MTYP_1   0x00000008U

Bit 1

#define FMC_BCR4_MUXEN   0x00000002U

Address/data multiplexing enable bit

#define FMC_BCR4_MWID   0x00000030U

MWID[1:0] bits (Memory data bus width)

#define FMC_BCR4_MWID_0   0x00000010U

Bit 0

#define FMC_BCR4_MWID_1   0x00000020U

Bit 1

#define FMC_BCR4_WAITCFG   0x00000800U

Wait timing configuration

#define FMC_BCR4_WAITEN   0x00002000U

Wait enable bit

#define FMC_BCR4_WAITPOL   0x00000200U

Wait signal polarity bit

#define FMC_BCR4_WRAPMOD   0x00000400U

Wrapped burst mode support

#define FMC_BCR4_WREN   0x00001000U

Write enable bit

#define FMC_BTR1_ACCMOD   0x30000000U

ACCMOD[1:0] bits (Access mode)

#define FMC_BTR1_ACCMOD_0   0x10000000U

Bit 0

#define FMC_BTR1_ACCMOD_1   0x20000000U

Bit 1

#define FMC_BTR1_ADDHLD   0x000000F0U

ADDHLD[3:0] bits (Address-hold phase duration)

#define FMC_BTR1_ADDHLD_0   0x00000010U

Bit 0

#define FMC_BTR1_ADDHLD_1   0x00000020U

Bit 1

#define FMC_BTR1_ADDHLD_2   0x00000040U

Bit 2

#define FMC_BTR1_ADDHLD_3   0x00000080U

Bit 3

#define FMC_BTR1_ADDSET   0x0000000FU

ADDSET[3:0] bits (Address setup phase duration)

#define FMC_BTR1_ADDSET_0   0x00000001U

Bit 0

#define FMC_BTR1_ADDSET_1   0x00000002U

Bit 1

#define FMC_BTR1_ADDSET_2   0x00000004U

Bit 2

#define FMC_BTR1_ADDSET_3   0x00000008U

Bit 3

#define FMC_BTR1_BUSTURN   0x000F0000U

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FMC_BTR1_BUSTURN_0   0x00010000U

Bit 0

#define FMC_BTR1_BUSTURN_1   0x00020000U

Bit 1

#define FMC_BTR1_BUSTURN_2   0x00040000U

Bit 2

#define FMC_BTR1_BUSTURN_3   0x00080000U

Bit 3

#define FMC_BTR1_CLKDIV   0x00F00000U

CLKDIV[3:0] bits (Clock divide ratio)

#define FMC_BTR1_CLKDIV_0   0x00100000U

Bit 0

#define FMC_BTR1_CLKDIV_1   0x00200000U

Bit 1

#define FMC_BTR1_CLKDIV_2   0x00400000U

Bit 2

#define FMC_BTR1_CLKDIV_3   0x00800000U

Bit 3

#define FMC_BTR1_DATAST   0x0000FF00U

DATAST [3:0] bits (Data-phase duration)

#define FMC_BTR1_DATAST_0   0x00000100U

Bit 0

#define FMC_BTR1_DATAST_1   0x00000200U

Bit 1

#define FMC_BTR1_DATAST_2   0x00000400U

Bit 2

#define FMC_BTR1_DATAST_3   0x00000800U

Bit 3

#define FMC_BTR1_DATAST_4   0x00001000U

Bit 4

#define FMC_BTR1_DATAST_5   0x00002000U

Bit 5

#define FMC_BTR1_DATAST_6   0x00004000U

Bit 6

#define FMC_BTR1_DATAST_7   0x00008000U

Bit 7

#define FMC_BTR1_DATLAT   0x0F000000U

DATLA[3:0] bits (Data latency)

#define FMC_BTR1_DATLAT_0   0x01000000U

Bit 0

#define FMC_BTR1_DATLAT_1   0x02000000U

Bit 1

#define FMC_BTR1_DATLAT_2   0x04000000U

Bit 2

#define FMC_BTR1_DATLAT_3   0x08000000U

Bit 3

#define FMC_BTR2_ACCMOD   0x30000000U

ACCMOD[1:0] bits (Access mode)

#define FMC_BTR2_ACCMOD_0   0x10000000U

Bit 0

#define FMC_BTR2_ACCMOD_1   0x20000000U

Bit 1

#define FMC_BTR2_ADDHLD   0x000000F0U

ADDHLD[3:0] bits (Address-hold phase duration)

#define FMC_BTR2_ADDHLD_0   0x00000010U

Bit 0

#define FMC_BTR2_ADDHLD_1   0x00000020U

Bit 1

#define FMC_BTR2_ADDHLD_2   0x00000040U

Bit 2

#define FMC_BTR2_ADDHLD_3   0x00000080U

Bit 3

#define FMC_BTR2_ADDSET   0x0000000FU

ADDSET[3:0] bits (Address setup phase duration)

#define FMC_BTR2_ADDSET_0   0x00000001U

Bit 0

#define FMC_BTR2_ADDSET_1   0x00000002U

Bit 1

#define FMC_BTR2_ADDSET_2   0x00000004U

Bit 2

#define FMC_BTR2_ADDSET_3   0x00000008U

Bit 3

#define FMC_BTR2_BUSTURN   0x000F0000U

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FMC_BTR2_BUSTURN_0   0x00010000U

Bit 0

#define FMC_BTR2_BUSTURN_1   0x00020000U

Bit 1

#define FMC_BTR2_BUSTURN_2   0x00040000U

Bit 2

#define FMC_BTR2_BUSTURN_3   0x00080000U

Bit 3

#define FMC_BTR2_CLKDIV   0x00F00000U

CLKDIV[3:0] bits (Clock divide ratio)

#define FMC_BTR2_CLKDIV_0   0x00100000U

Bit 0

#define FMC_BTR2_CLKDIV_1   0x00200000U

Bit 1

#define FMC_BTR2_CLKDIV_2   0x00400000U

Bit 2

#define FMC_BTR2_CLKDIV_3   0x00800000U

Bit 3

#define FMC_BTR2_DATAST   0x0000FF00U

DATAST [3:0] bits (Data-phase duration)

#define FMC_BTR2_DATAST_0   0x00000100U

Bit 0

#define FMC_BTR2_DATAST_1   0x00000200U

Bit 1

#define FMC_BTR2_DATAST_2   0x00000400U

Bit 2

#define FMC_BTR2_DATAST_3   0x00000800U

Bit 3

#define FMC_BTR2_DATAST_4   0x00001000U

Bit 4

#define FMC_BTR2_DATAST_5   0x00002000U

Bit 5

#define FMC_BTR2_DATAST_6   0x00004000U

Bit 6

#define FMC_BTR2_DATAST_7   0x00008000U

Bit 7

#define FMC_BTR2_DATLAT   0x0F000000U

DATLA[3:0] bits (Data latency)

#define FMC_BTR2_DATLAT_0   0x01000000U

Bit 0

#define FMC_BTR2_DATLAT_1   0x02000000U

Bit 1

#define FMC_BTR2_DATLAT_2   0x04000000U

Bit 2

#define FMC_BTR2_DATLAT_3   0x08000000U

Bit 3

#define FMC_BTR3_ACCMOD   0x30000000U

ACCMOD[1:0] bits (Access mode)

#define FMC_BTR3_ACCMOD_0   0x10000000U

Bit 0

#define FMC_BTR3_ACCMOD_1   0x20000000U

Bit 1

#define FMC_BTR3_ADDHLD   0x000000F0U

ADDHLD[3:0] bits (Address-hold phase duration)

#define FMC_BTR3_ADDHLD_0   0x00000010U

Bit 0

#define FMC_BTR3_ADDHLD_1   0x00000020U

Bit 1

#define FMC_BTR3_ADDHLD_2   0x00000040U

Bit 2

#define FMC_BTR3_ADDHLD_3   0x00000080U

Bit 3

#define FMC_BTR3_ADDSET   0x0000000FU

ADDSET[3:0] bits (Address setup phase duration)

#define FMC_BTR3_ADDSET_0   0x00000001U

Bit 0

#define FMC_BTR3_ADDSET_1   0x00000002U

Bit 1

#define FMC_BTR3_ADDSET_2   0x00000004U

Bit 2

#define FMC_BTR3_ADDSET_3   0x00000008U

Bit 3

#define FMC_BTR3_BUSTURN   0x000F0000U

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FMC_BTR3_BUSTURN_0   0x00010000U

Bit 0

#define FMC_BTR3_BUSTURN_1   0x00020000U

Bit 1

#define FMC_BTR3_BUSTURN_2   0x00040000U

Bit 2

#define FMC_BTR3_BUSTURN_3   0x00080000U

Bit 3

#define FMC_BTR3_CLKDIV   0x00F00000U

CLKDIV[3:0] bits (Clock divide ratio)

#define FMC_BTR3_CLKDIV_0   0x00100000U

Bit 0

#define FMC_BTR3_CLKDIV_1   0x00200000U

Bit 1

#define FMC_BTR3_CLKDIV_2   0x00400000U

Bit 2

#define FMC_BTR3_CLKDIV_3   0x00800000U

Bit 3

#define FMC_BTR3_DATAST   0x0000FF00U

DATAST [3:0] bits (Data-phase duration)

#define FMC_BTR3_DATAST_0   0x00000100U

Bit 0

#define FMC_BTR3_DATAST_1   0x00000200U

Bit 1

#define FMC_BTR3_DATAST_2   0x00000400U

Bit 2

#define FMC_BTR3_DATAST_3   0x00000800U

Bit 3

#define FMC_BTR3_DATAST_4   0x00001000U

Bit 4

#define FMC_BTR3_DATAST_5   0x00002000U

Bit 5

#define FMC_BTR3_DATAST_6   0x00004000U

Bit 6

#define FMC_BTR3_DATAST_7   0x00008000U

Bit 7

#define FMC_BTR3_DATLAT   0x0F000000U

DATLA[3:0] bits (Data latency)

#define FMC_BTR3_DATLAT_0   0x01000000U

Bit 0

#define FMC_BTR3_DATLAT_1   0x02000000U

Bit 1

#define FMC_BTR3_DATLAT_2   0x04000000U

Bit 2

#define FMC_BTR3_DATLAT_3   0x08000000U

Bit 3

#define FMC_BTR4_ACCMOD   0x30000000U

ACCMOD[1:0] bits (Access mode)

#define FMC_BTR4_ACCMOD_0   0x10000000U

Bit 0

#define FMC_BTR4_ACCMOD_1   0x20000000U

Bit 1

#define FMC_BTR4_ADDHLD   0x000000F0U

ADDHLD[3:0] bits (Address-hold phase duration)

#define FMC_BTR4_ADDHLD_0   0x00000010U

Bit 0

#define FMC_BTR4_ADDHLD_1   0x00000020U

Bit 1

#define FMC_BTR4_ADDHLD_2   0x00000040U

Bit 2

#define FMC_BTR4_ADDHLD_3   0x00000080U

Bit 3

#define FMC_BTR4_ADDSET   0x0000000FU

ADDSET[3:0] bits (Address setup phase duration)

#define FMC_BTR4_ADDSET_0   0x00000001U

Bit 0

#define FMC_BTR4_ADDSET_1   0x00000002U

Bit 1

#define FMC_BTR4_ADDSET_2   0x00000004U

Bit 2

#define FMC_BTR4_ADDSET_3   0x00000008U

Bit 3

#define FMC_BTR4_BUSTURN   0x000F0000U

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FMC_BTR4_BUSTURN_0   0x00010000U

Bit 0

#define FMC_BTR4_BUSTURN_1   0x00020000U

Bit 1

#define FMC_BTR4_BUSTURN_2   0x00040000U

Bit 2

#define FMC_BTR4_BUSTURN_3   0x00080000U

Bit 3

#define FMC_BTR4_CLKDIV   0x00F00000U

CLKDIV[3:0] bits (Clock divide ratio)

#define FMC_BTR4_CLKDIV_0   0x00100000U

Bit 0

#define FMC_BTR4_CLKDIV_1   0x00200000U

Bit 1

#define FMC_BTR4_CLKDIV_2   0x00400000U

Bit 2

#define FMC_BTR4_CLKDIV_3   0x00800000U

Bit 3

#define FMC_BTR4_DATAST   0x0000FF00U

DATAST [3:0] bits (Data-phase duration)

#define FMC_BTR4_DATAST_0   0x00000100U

Bit 0

#define FMC_BTR4_DATAST_1   0x00000200U

Bit 1

#define FMC_BTR4_DATAST_2   0x00000400U

Bit 2

#define FMC_BTR4_DATAST_3   0x00000800U

Bit 3

#define FMC_BTR4_DATAST_4   0x00001000U

Bit 4

#define FMC_BTR4_DATAST_5   0x00002000U

Bit 5

#define FMC_BTR4_DATAST_6   0x00004000U

Bit 6

#define FMC_BTR4_DATAST_7   0x00008000U

Bit 7

#define FMC_BTR4_DATLAT   0x0F000000U

DATLA[3:0] bits (Data latency)

#define FMC_BTR4_DATLAT_0   0x01000000U

Bit 0

#define FMC_BTR4_DATLAT_1   0x02000000U

Bit 1

#define FMC_BTR4_DATLAT_2   0x04000000U

Bit 2

#define FMC_BTR4_DATLAT_3   0x08000000U

Bit 3

#define FMC_BWTR1_ACCMOD   0x30000000U

ACCMOD[1:0] bits (Access mode)

#define FMC_BWTR1_ACCMOD_0   0x10000000U

Bit 0

#define FMC_BWTR1_ACCMOD_1   0x20000000U

Bit 1

#define FMC_BWTR1_ADDHLD   0x000000F0U

ADDHLD[3:0] bits (Address-hold phase duration)

#define FMC_BWTR1_ADDHLD_0   0x00000010U

Bit 0

#define FMC_BWTR1_ADDHLD_1   0x00000020U

Bit 1

#define FMC_BWTR1_ADDHLD_2   0x00000040U

Bit 2

#define FMC_BWTR1_ADDHLD_3   0x00000080U

Bit 3

#define FMC_BWTR1_ADDSET   0x0000000FU

ADDSET[3:0] bits (Address setup phase duration)

#define FMC_BWTR1_ADDSET_0   0x00000001U

Bit 0

#define FMC_BWTR1_ADDSET_1   0x00000002U

Bit 1

#define FMC_BWTR1_ADDSET_2   0x00000004U

Bit 2

#define FMC_BWTR1_ADDSET_3   0x00000008U

Bit 3

#define FMC_BWTR1_BUSTURN   0x000F0000U

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FMC_BWTR1_BUSTURN_0   0x00010000U

Bit 0

#define FMC_BWTR1_BUSTURN_1   0x00020000U

Bit 1

#define FMC_BWTR1_BUSTURN_2   0x00040000U

Bit 2

#define FMC_BWTR1_BUSTURN_3   0x00080000U

Bit 3

#define FMC_BWTR1_DATAST   0x0000FF00U

DATAST [3:0] bits (Data-phase duration)

#define FMC_BWTR1_DATAST_0   0x00000100U

Bit 0

#define FMC_BWTR1_DATAST_1   0x00000200U

Bit 1

#define FMC_BWTR1_DATAST_2   0x00000400U

Bit 2

#define FMC_BWTR1_DATAST_3   0x00000800U

Bit 3

#define FMC_BWTR1_DATAST_4   0x00001000U

Bit 4

#define FMC_BWTR1_DATAST_5   0x00002000U

Bit 5

#define FMC_BWTR1_DATAST_6   0x00004000U

Bit 6

#define FMC_BWTR1_DATAST_7   0x00008000U

Bit 7

#define FMC_BWTR2_ACCMOD   0x30000000U

ACCMOD[1:0] bits (Access mode)

#define FMC_BWTR2_ACCMOD_0   0x10000000U

Bit 0

#define FMC_BWTR2_ACCMOD_1   0x20000000U

Bit 1

#define FMC_BWTR2_ADDHLD   0x000000F0U

ADDHLD[3:0] bits (Address-hold phase duration)

#define FMC_BWTR2_ADDHLD_0   0x00000010U

Bit 0

#define FMC_BWTR2_ADDHLD_1   0x00000020U

Bit 1

#define FMC_BWTR2_ADDHLD_2   0x00000040U

Bit 2

#define FMC_BWTR2_ADDHLD_3   0x00000080U

Bit 3

#define FMC_BWTR2_ADDSET   0x0000000FU

ADDSET[3:0] bits (Address setup phase duration)

#define FMC_BWTR2_ADDSET_0   0x00000001U

Bit 0

#define FMC_BWTR2_ADDSET_1   0x00000002U

Bit 1

#define FMC_BWTR2_ADDSET_2   0x00000004U

Bit 2

#define FMC_BWTR2_ADDSET_3   0x00000008U

Bit 3

#define FMC_BWTR2_BUSTURN   0x000F0000U

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FMC_BWTR2_BUSTURN_0   0x00010000U

Bit 0

#define FMC_BWTR2_BUSTURN_1   0x00020000U

Bit 1

#define FMC_BWTR2_BUSTURN_2   0x00040000U

Bit 2

#define FMC_BWTR2_BUSTURN_3   0x00080000U

Bit 3

#define FMC_BWTR2_DATAST   0x0000FF00U

DATAST [3:0] bits (Data-phase duration)

#define FMC_BWTR2_DATAST_0   0x00000100U

Bit 0

#define FMC_BWTR2_DATAST_1   0x00000200U

Bit 1

#define FMC_BWTR2_DATAST_2   0x00000400U

Bit 2

#define FMC_BWTR2_DATAST_3   0x00000800U

Bit 3

#define FMC_BWTR2_DATAST_4   0x00001000U

Bit 4

#define FMC_BWTR2_DATAST_5   0x00002000U

Bit 5

#define FMC_BWTR2_DATAST_6   0x00004000U

Bit 6

#define FMC_BWTR2_DATAST_7   0x00008000U

Bit 7

#define FMC_BWTR3_ACCMOD   0x30000000U

ACCMOD[1:0] bits (Access mode)

#define FMC_BWTR3_ACCMOD_0   0x10000000U

Bit 0

#define FMC_BWTR3_ACCMOD_1   0x20000000U

Bit 1

#define FMC_BWTR3_ADDHLD   0x000000F0U

ADDHLD[3:0] bits (Address-hold phase duration)

#define FMC_BWTR3_ADDHLD_0   0x00000010U

Bit 0

#define FMC_BWTR3_ADDHLD_1   0x00000020U

Bit 1

#define FMC_BWTR3_ADDHLD_2   0x00000040U

Bit 2

#define FMC_BWTR3_ADDHLD_3   0x00000080U

Bit 3

#define FMC_BWTR3_ADDSET   0x0000000FU

ADDSET[3:0] bits (Address setup phase duration)

#define FMC_BWTR3_ADDSET_0   0x00000001U

Bit 0

#define FMC_BWTR3_ADDSET_1   0x00000002U

Bit 1

#define FMC_BWTR3_ADDSET_2   0x00000004U

Bit 2

#define FMC_BWTR3_ADDSET_3   0x00000008U

Bit 3

#define FMC_BWTR3_BUSTURN   0x000F0000U

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FMC_BWTR3_BUSTURN_0   0x00010000U

Bit 0

#define FMC_BWTR3_BUSTURN_1   0x00020000U

Bit 1

#define FMC_BWTR3_BUSTURN_2   0x00040000U

Bit 2

#define FMC_BWTR3_BUSTURN_3   0x00080000U

Bit 3

#define FMC_BWTR3_DATAST   0x0000FF00U

DATAST [3:0] bits (Data-phase duration)

#define FMC_BWTR3_DATAST_0   0x00000100U

Bit 0

#define FMC_BWTR3_DATAST_1   0x00000200U

Bit 1

#define FMC_BWTR3_DATAST_2   0x00000400U

Bit 2

#define FMC_BWTR3_DATAST_3   0x00000800U

Bit 3

#define FMC_BWTR3_DATAST_4   0x00001000U

Bit 4

#define FMC_BWTR3_DATAST_5   0x00002000U

Bit 5

#define FMC_BWTR3_DATAST_6   0x00004000U

Bit 6

#define FMC_BWTR3_DATAST_7   0x00008000U

Bit 7

#define FMC_BWTR4_ACCMOD   0x30000000U

ACCMOD[1:0] bits (Access mode)

#define FMC_BWTR4_ACCMOD_0   0x10000000U

Bit 0

#define FMC_BWTR4_ACCMOD_1   0x20000000U

Bit 1

#define FMC_BWTR4_ADDHLD   0x000000F0U

ADDHLD[3:0] bits (Address-hold phase duration)

#define FMC_BWTR4_ADDHLD_0   0x00000010U

Bit 0

#define FMC_BWTR4_ADDHLD_1   0x00000020U

Bit 1

#define FMC_BWTR4_ADDHLD_2   0x00000040U

Bit 2

#define FMC_BWTR4_ADDHLD_3   0x00000080U

Bit 3

#define FMC_BWTR4_ADDSET   0x0000000FU

ADDSET[3:0] bits (Address setup phase duration)

#define FMC_BWTR4_ADDSET_0   0x00000001U

Bit 0

#define FMC_BWTR4_ADDSET_1   0x00000002U

Bit 1

#define FMC_BWTR4_ADDSET_2   0x00000004U

Bit 2

#define FMC_BWTR4_ADDSET_3   0x00000008U

Bit 3

#define FMC_BWTR4_BUSTURN   0x000F0000U

BUSTURN[3:0] bits (Bus turnaround phase duration)

#define FMC_BWTR4_BUSTURN_0   0x00010000U

Bit 0

#define FMC_BWTR4_BUSTURN_1   0x00020000U

Bit 1

#define FMC_BWTR4_BUSTURN_2   0x00040000U

Bit 2

#define FMC_BWTR4_BUSTURN_3   0x00080000U

Bit 3

#define FMC_BWTR4_DATAST   0x0000FF00U

DATAST [3:0] bits (Data-phase duration)

#define FMC_BWTR4_DATAST_0   0x00000100U

Bit 0

#define FMC_BWTR4_DATAST_1   0x00000200U

Bit 1

#define FMC_BWTR4_DATAST_2   0x00000400U

Bit 2

#define FMC_BWTR4_DATAST_3   0x00000800U

Bit 3

#define FMC_BWTR4_DATAST_4   0x00001000U

Bit 4

#define FMC_BWTR4_DATAST_5   0x00002000U

Bit 5

#define FMC_BWTR4_DATAST_6   0x00004000U

Bit 6

#define FMC_BWTR4_DATAST_7   0x00008000U

Bit 7

#define FMC_ECCR_ECC3   0xFFFFFFFFU

ECC result

#define FMC_PATT_ATTHIZ3   0xFF000000U

ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time)

#define FMC_PATT_ATTHIZ3_0   0x01000000U

Bit 0

#define FMC_PATT_ATTHIZ3_1   0x02000000U

Bit 1

#define FMC_PATT_ATTHIZ3_2   0x04000000U

Bit 2

#define FMC_PATT_ATTHIZ3_3   0x08000000U

Bit 3

#define FMC_PATT_ATTHIZ3_4   0x10000000U

Bit 4

#define FMC_PATT_ATTHIZ3_5   0x20000000U

Bit 5

#define FMC_PATT_ATTHIZ3_6   0x40000000U

Bit 6

#define FMC_PATT_ATTHIZ3_7   0x80000000U

Bit 7

#define FMC_PATT_ATTHOLD3   0x00FF0000U

ATTHOLD3[7:0] bits (Attribute memory 3 hold time)

#define FMC_PATT_ATTHOLD3_0   0x00010000U

Bit 0

#define FMC_PATT_ATTHOLD3_1   0x00020000U

Bit 1

#define FMC_PATT_ATTHOLD3_2   0x00040000U

Bit 2

#define FMC_PATT_ATTHOLD3_3   0x00080000U

Bit 3

#define FMC_PATT_ATTHOLD3_4   0x00100000U

Bit 4

#define FMC_PATT_ATTHOLD3_5   0x00200000U

Bit 5

#define FMC_PATT_ATTHOLD3_6   0x00400000U

Bit 6

#define FMC_PATT_ATTHOLD3_7   0x00800000U

Bit 7

#define FMC_PATT_ATTSET3   0x000000FFU

ATTSET3[7:0] bits (Attribute memory 3 setup time)

#define FMC_PATT_ATTSET3_0   0x00000001U

Bit 0

#define FMC_PATT_ATTSET3_1   0x00000002U

Bit 1

#define FMC_PATT_ATTSET3_2   0x00000004U

Bit 2

#define FMC_PATT_ATTSET3_3   0x00000008U

Bit 3

#define FMC_PATT_ATTSET3_4   0x00000010U

Bit 4

#define FMC_PATT_ATTSET3_5   0x00000020U

Bit 5

#define FMC_PATT_ATTSET3_6   0x00000040U

Bit 6

#define FMC_PATT_ATTSET3_7   0x00000080U

Bit 7

#define FMC_PATT_ATTWAIT3   0x0000FF00U

ATTWAIT3[7:0] bits (Attribute memory 3 wait time)

#define FMC_PATT_ATTWAIT3_0   0x00000100U

Bit 0

#define FMC_PATT_ATTWAIT3_1   0x00000200U

Bit 1

#define FMC_PATT_ATTWAIT3_2   0x00000400U

Bit 2

#define FMC_PATT_ATTWAIT3_3   0x00000800U

Bit 3

#define FMC_PATT_ATTWAIT3_4   0x00001000U

Bit 4

#define FMC_PATT_ATTWAIT3_5   0x00002000U

Bit 5

#define FMC_PATT_ATTWAIT3_6   0x00004000U

Bit 6

#define FMC_PATT_ATTWAIT3_7   0x00008000U

Bit 7

#define FMC_PCR_ECCEN   0x00000040U

ECC computation logic enable bit

#define FMC_PCR_ECCPS   0x000E0000U

ECCPS[2:0] bits (ECC page size)

#define FMC_PCR_ECCPS_0   0x00020000U

Bit 0

#define FMC_PCR_ECCPS_1   0x00040000U

Bit 1

#define FMC_PCR_ECCPS_2   0x00080000U

Bit 2

#define FMC_PCR_PBKEN   0x00000004U

PC Card/NAND Flash memory bank enable bit

#define FMC_PCR_PTYP   0x00000008U

Memory type

#define FMC_PCR_PWAITEN   0x00000002U

Wait feature enable bit

#define FMC_PCR_PWID   0x00000030U

PWID[1:0] bits (NAND Flash databus width)

#define FMC_PCR_PWID_0   0x00000010U

Bit 0

#define FMC_PCR_PWID_1   0x00000020U

Bit 1

#define FMC_PCR_TAR   0x0001E000U

TAR[3:0] bits (ALE to RE delay)

#define FMC_PCR_TAR_0   0x00002000U

Bit 0

#define FMC_PCR_TAR_1   0x00004000U

Bit 1

#define FMC_PCR_TAR_2   0x00008000U

Bit 2

#define FMC_PCR_TAR_3   0x00010000U

Bit 3

#define FMC_PCR_TCLR   0x00001E00U

TCLR[3:0] bits (CLE to RE delay)

#define FMC_PCR_TCLR_0   0x00000200U

Bit 0

#define FMC_PCR_TCLR_1   0x00000400U

Bit 1

#define FMC_PCR_TCLR_2   0x00000800U

Bit 2

#define FMC_PCR_TCLR_3   0x00001000U

Bit 3

#define FMC_PMEM_MEMHIZ3   0xFF000000U

MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time)

#define FMC_PMEM_MEMHIZ3_0   0x01000000U

Bit 0

#define FMC_PMEM_MEMHIZ3_1   0x02000000U

Bit 1

#define FMC_PMEM_MEMHIZ3_2   0x04000000U

Bit 2

#define FMC_PMEM_MEMHIZ3_3   0x08000000U

Bit 3

#define FMC_PMEM_MEMHIZ3_4   0x10000000U

Bit 4

#define FMC_PMEM_MEMHIZ3_5   0x20000000U

Bit 5

#define FMC_PMEM_MEMHIZ3_6   0x40000000U

Bit 6

#define FMC_PMEM_MEMHIZ3_7   0x80000000U

Bit 7

#define FMC_PMEM_MEMHOLD3   0x00FF0000U

MEMHOLD3[7:0] bits (Common memory 3 hold time)

#define FMC_PMEM_MEMHOLD3_0   0x00010000U

Bit 0

#define FMC_PMEM_MEMHOLD3_1   0x00020000U

Bit 1

#define FMC_PMEM_MEMHOLD3_2   0x00040000U

Bit 2

#define FMC_PMEM_MEMHOLD3_3   0x00080000U

Bit 3

#define FMC_PMEM_MEMHOLD3_4   0x00100000U

Bit 4

#define FMC_PMEM_MEMHOLD3_5   0x00200000U

Bit 5

#define FMC_PMEM_MEMHOLD3_6   0x00400000U

Bit 6

#define FMC_PMEM_MEMHOLD3_7   0x00800000U

Bit 7

#define FMC_PMEM_MEMSET3   0x000000FFU

MEMSET3[7:0] bits (Common memory 3 setup time)

#define FMC_PMEM_MEMSET3_0   0x00000001U

Bit 0

#define FMC_PMEM_MEMSET3_1   0x00000002U

Bit 1

#define FMC_PMEM_MEMSET3_2   0x00000004U

Bit 2

#define FMC_PMEM_MEMSET3_3   0x00000008U

Bit 3

#define FMC_PMEM_MEMSET3_4   0x00000010U

Bit 4

#define FMC_PMEM_MEMSET3_5   0x00000020U

Bit 5

#define FMC_PMEM_MEMSET3_6   0x00000040U

Bit 6

#define FMC_PMEM_MEMSET3_7   0x00000080U

Bit 7

#define FMC_PMEM_MEMWAIT3   0x0000FF00U

MEMWAIT3[7:0] bits (Common memory 3 wait time)

#define FMC_PMEM_MEMWAIT3_0   0x00000100U

Bit 0

#define FMC_PMEM_MEMWAIT3_1   0x00000200U

Bit 1

#define FMC_PMEM_MEMWAIT3_2   0x00000400U

Bit 2

#define FMC_PMEM_MEMWAIT3_3   0x00000800U

Bit 3

#define FMC_PMEM_MEMWAIT3_4   0x00001000U

Bit 4

#define FMC_PMEM_MEMWAIT3_5   0x00002000U

Bit 5

#define FMC_PMEM_MEMWAIT3_6   0x00004000U

Bit 6

#define FMC_PMEM_MEMWAIT3_7   0x00008000U

Bit 7

#define FMC_SDCMR_CTB1   0x00000010U

Command target 1

#define FMC_SDCMR_CTB2   0x00000008U

Command target 2

#define FMC_SDCMR_MODE   0x00000007U

MODE[2:0] bits (Command mode)

#define FMC_SDCMR_MODE_0   0x00000001U

Bit 0

#define FMC_SDCMR_MODE_1   0x00000002U

Bit 1

#define FMC_SDCMR_MODE_2   0x00000003U

Bit 2

#define FMC_SDCMR_MRD   0x003FFE00U

MRD[12:0] bits (Mode register definition)

#define FMC_SDCMR_NRFS   0x000001E0U

NRFS[3:0] bits (Number of auto-refresh)

#define FMC_SDCMR_NRFS_0   0x00000020U

Bit 0

#define FMC_SDCMR_NRFS_1   0x00000040U

Bit 1

#define FMC_SDCMR_NRFS_2   0x00000080U

Bit 2

#define FMC_SDCMR_NRFS_3   0x00000100U

Bit 3

#define FMC_SDCR1_CAS   0x00000180U

CAS[1:0] bits (CAS latency)

#define FMC_SDCR1_CAS_0   0x00000080U

Bit 0

#define FMC_SDCR1_CAS_1   0x00000100U

Bit 1

#define FMC_SDCR1_MWID   0x00000030U

NR[1:0] bits (Number of row bits)

#define FMC_SDCR1_MWID_0   0x00000010U

Bit 0

#define FMC_SDCR1_MWID_1   0x00000020U

Bit 1

#define FMC_SDCR1_NB   0x00000040U

Number of internal bank

#define FMC_SDCR1_NC   0x00000003U

NC[1:0] bits (Number of column bits)

#define FMC_SDCR1_NC_0   0x00000001U

Bit 0

#define FMC_SDCR1_NC_1   0x00000002U

Bit 1

#define FMC_SDCR1_NR   0x0000000CU

NR[1:0] bits (Number of row bits)

#define FMC_SDCR1_NR_0   0x00000004U

Bit 0

#define FMC_SDCR1_NR_1   0x00000008U

Bit 1

#define FMC_SDCR1_RBURST   0x00001000U

Read burst

#define FMC_SDCR1_RPIPE   0x00006000U

Write protection

#define FMC_SDCR1_RPIPE_0   0x00002000U

Bit 0

#define FMC_SDCR1_RPIPE_1   0x00004000U

Bit 1

#define FMC_SDCR1_SDCLK   0x00000C00U

SDRAM clock configuration

#define FMC_SDCR1_SDCLK_0   0x00000400U

Bit 0

#define FMC_SDCR1_SDCLK_1   0x00000800U

Bit 1

#define FMC_SDCR1_WP   0x00000200U

Write protection

#define FMC_SDCR2_CAS   0x00000180U

CAS[1:0] bits (CAS latency)

#define FMC_SDCR2_CAS_0   0x00000080U

Bit 0

#define FMC_SDCR2_CAS_1   0x00000100U

Bit 1

#define FMC_SDCR2_MWID   0x00000030U

NR[1:0] bits (Number of row bits)

#define FMC_SDCR2_MWID_0   0x00000010U

Bit 0

#define FMC_SDCR2_MWID_1   0x00000020U

Bit 1

#define FMC_SDCR2_NB   0x00000040U

Number of internal bank

#define FMC_SDCR2_NC   0x00000003U

NC[1:0] bits (Number of column bits)

#define FMC_SDCR2_NC_0   0x00000001U

Bit 0

#define FMC_SDCR2_NC_1   0x00000002U

Bit 1

#define FMC_SDCR2_NR   0x0000000CU

NR[1:0] bits (Number of row bits)

#define FMC_SDCR2_NR_0   0x00000004U

Bit 0

#define FMC_SDCR2_NR_1   0x00000008U

Bit 1

#define FMC_SDCR2_RBURST   0x00001000U

Read burst

#define FMC_SDCR2_RPIPE   0x00006000U

RPIPE[1:0](Read pipe)

#define FMC_SDCR2_RPIPE_0   0x00002000U

Bit 0

#define FMC_SDCR2_RPIPE_1   0x00004000U

Bit 1

#define FMC_SDCR2_SDCLK   0x00000C00U

SDCLK[1:0] (SDRAM clock configuration)

#define FMC_SDCR2_SDCLK_0   0x00000400U

Bit 0

#define FMC_SDCR2_SDCLK_1   0x00000800U

Bit 1

#define FMC_SDCR2_WP   0x00000200U

Write protection

#define FMC_SDRTR_COUNT   0x00003FFEU

COUNT[12:0] bits (Refresh timer count)

#define FMC_SDRTR_CRE   0x00000001U

Clear refresh error flag

#define FMC_SDRTR_REIE   0x00004000U

RES interupt enable

#define FMC_SDSR_BUSY   0x00000020U

Busy status

#define FMC_SDSR_MODES1   0x00000006U

MODES1[1:0]bits (Status mode for bank 1)

#define FMC_SDSR_MODES1_0   0x00000002U

Bit 0

#define FMC_SDSR_MODES1_1   0x00000004U

Bit 1

#define FMC_SDSR_MODES2   0x00000018U

MODES2[1:0]bits (Status mode for bank 2)

#define FMC_SDSR_MODES2_0   0x00000008U

Bit 0

#define FMC_SDSR_MODES2_1   0x00000010U

Bit 1

#define FMC_SDSR_RE   0x00000001U

Refresh error flag

#define FMC_SDTR1_TMRD   0x0000000FU

TMRD[3:0] bits (Load mode register to active)

#define FMC_SDTR1_TMRD_0   0x00000001U

Bit 0

#define FMC_SDTR1_TMRD_1   0x00000002U

Bit 1

#define FMC_SDTR1_TMRD_2   0x00000004U

Bit 2

#define FMC_SDTR1_TMRD_3   0x00000008U

Bit 3

#define FMC_SDTR1_TRAS   0x00000F00U

TRAS[3:0] bits (Self refresh time)

#define FMC_SDTR1_TRAS_0   0x00000100U

Bit 0

#define FMC_SDTR1_TRAS_1   0x00000200U

Bit 1

#define FMC_SDTR1_TRAS_2   0x00000400U

Bit 2

#define FMC_SDTR1_TRAS_3   0x00000800U

Bit 3

#define FMC_SDTR1_TRC   0x0000F000U

TRC[2:0] bits (Row cycle delay)

#define FMC_SDTR1_TRC_0   0x00001000U

Bit 0

#define FMC_SDTR1_TRC_1   0x00002000U

Bit 1

#define FMC_SDTR1_TRC_2   0x00004000U

Bit 2

#define FMC_SDTR1_TRCD   0x0F000000U

TRP[2:0] bits (Row to column delay)

#define FMC_SDTR1_TRCD_0   0x01000000U

Bit 0

#define FMC_SDTR1_TRCD_1   0x02000000U

Bit 1

#define FMC_SDTR1_TRCD_2   0x04000000U

Bit 2

#define FMC_SDTR1_TRP   0x00F00000U

TRP[2:0] bits (Row precharge delay)

#define FMC_SDTR1_TRP_0   0x00100000U

Bit 0

#define FMC_SDTR1_TRP_1   0x00200000U

Bit 1

#define FMC_SDTR1_TRP_2   0x00400000U

Bit 2

#define FMC_SDTR1_TWR   0x000F0000U

TRC[2:0] bits (Write recovery delay)

#define FMC_SDTR1_TWR_0   0x00010000U

Bit 0

#define FMC_SDTR1_TWR_1   0x00020000U

Bit 1

#define FMC_SDTR1_TWR_2   0x00040000U

Bit 2

#define FMC_SDTR1_TXSR   0x000000F0U

TXSR[3:0] bits (Exit self refresh)

#define FMC_SDTR1_TXSR_0   0x00000010U

Bit 0

#define FMC_SDTR1_TXSR_1   0x00000020U

Bit 1

#define FMC_SDTR1_TXSR_2   0x00000040U

Bit 2

#define FMC_SDTR1_TXSR_3   0x00000080U

Bit 3

#define FMC_SDTR2_TMRD   0x0000000FU

TMRD[3:0] bits (Load mode register to active)

#define FMC_SDTR2_TMRD_0   0x00000001U

Bit 0

#define FMC_SDTR2_TMRD_1   0x00000002U

Bit 1

#define FMC_SDTR2_TMRD_2   0x00000004U

Bit 2

#define FMC_SDTR2_TMRD_3   0x00000008U

Bit 3

#define FMC_SDTR2_TRAS   0x00000F00U

TRAS[3:0] bits (Self refresh time)

#define FMC_SDTR2_TRAS_0   0x00000100U

Bit 0

#define FMC_SDTR2_TRAS_1   0x00000200U

Bit 1

#define FMC_SDTR2_TRAS_2   0x00000400U

Bit 2

#define FMC_SDTR2_TRAS_3   0x00000800U

Bit 3

#define FMC_SDTR2_TRC   0x0000F000U

TRC[2:0] bits (Row cycle delay)

#define FMC_SDTR2_TRC_0   0x00001000U

Bit 0

#define FMC_SDTR2_TRC_1   0x00002000U

Bit 1

#define FMC_SDTR2_TRC_2   0x00004000U

Bit 2

#define FMC_SDTR2_TRCD   0x0F000000U

TRP[2:0] bits (Row to column delay)

#define FMC_SDTR2_TRCD_0   0x01000000U

Bit 0

#define FMC_SDTR2_TRCD_1   0x02000000U

Bit 1

#define FMC_SDTR2_TRCD_2   0x04000000U

Bit 2

#define FMC_SDTR2_TRP   0x00F00000U

TRP[2:0] bits (Row precharge delay)

#define FMC_SDTR2_TRP_0   0x00100000U

Bit 0

#define FMC_SDTR2_TRP_1   0x00200000U

Bit 1

#define FMC_SDTR2_TRP_2   0x00400000U

Bit 2

#define FMC_SDTR2_TWR   0x000F0000U

TRC[2:0] bits (Write recovery delay)

#define FMC_SDTR2_TWR_0   0x00010000U

Bit 0

#define FMC_SDTR2_TWR_1   0x00020000U

Bit 1

#define FMC_SDTR2_TWR_2   0x00040000U

Bit 2

#define FMC_SDTR2_TXSR   0x000000F0U

TXSR[3:0] bits (Exit self refresh)

#define FMC_SDTR2_TXSR_0   0x00000010U

Bit 0

#define FMC_SDTR2_TXSR_1   0x00000020U

Bit 1

#define FMC_SDTR2_TXSR_2   0x00000040U

Bit 2

#define FMC_SDTR2_TXSR_3   0x00000080U

Bit 3

#define FMC_SR_FEMPT   0x40U

FIFO empty

#define FMC_SR_IFEN   0x20U

Interrupt Falling Edge detection Enable bit

#define FMC_SR_IFS   0x04U

Interrupt Falling Edge status

#define FMC_SR_ILEN   0x10U

Interrupt Level detection Enable bit

#define FMC_SR_ILS   0x02U

Interrupt Level status

#define FMC_SR_IREN   0x08U

Interrupt Rising Edge detection Enable bit

#define FMC_SR_IRS   0x01U

Interrupt Rising Edge status

#define GPIO_BSRR_BR_0   0x00010000U
#define GPIO_BSRR_BR_1   0x00020000U
#define GPIO_BSRR_BR_10   0x04000000U
#define GPIO_BSRR_BR_11   0x08000000U
#define GPIO_BSRR_BR_12   0x10000000U
#define GPIO_BSRR_BR_13   0x20000000U
#define GPIO_BSRR_BR_14   0x40000000U
#define GPIO_BSRR_BR_15   0x80000000U
#define GPIO_BSRR_BR_2   0x00040000U
#define GPIO_BSRR_BR_3   0x00080000U
#define GPIO_BSRR_BR_4   0x00100000U
#define GPIO_BSRR_BR_5   0x00200000U
#define GPIO_BSRR_BR_6   0x00400000U
#define GPIO_BSRR_BR_7   0x00800000U
#define GPIO_BSRR_BR_8   0x01000000U
#define GPIO_BSRR_BR_9   0x02000000U
#define GPIO_BSRR_BS_0   0x00000001U
#define GPIO_BSRR_BS_1   0x00000002U
#define GPIO_BSRR_BS_10   0x00000400U
#define GPIO_BSRR_BS_11   0x00000800U
#define GPIO_BSRR_BS_12   0x00001000U
#define GPIO_BSRR_BS_13   0x00002000U
#define GPIO_BSRR_BS_14   0x00004000U
#define GPIO_BSRR_BS_15   0x00008000U
#define GPIO_BSRR_BS_2   0x00000004U
#define GPIO_BSRR_BS_3   0x00000008U
#define GPIO_BSRR_BS_4   0x00000010U
#define GPIO_BSRR_BS_5   0x00000020U
#define GPIO_BSRR_BS_6   0x00000040U
#define GPIO_BSRR_BS_7   0x00000080U
#define GPIO_BSRR_BS_8   0x00000100U
#define GPIO_BSRR_BS_9   0x00000200U
#define GPIO_IDR_IDR_0   0x00000001U
#define GPIO_IDR_IDR_1   0x00000002U
#define GPIO_IDR_IDR_10   0x00000400U
#define GPIO_IDR_IDR_11   0x00000800U
#define GPIO_IDR_IDR_12   0x00001000U
#define GPIO_IDR_IDR_13   0x00002000U
#define GPIO_IDR_IDR_14   0x00004000U
#define GPIO_IDR_IDR_15   0x00008000U
#define GPIO_IDR_IDR_2   0x00000004U
#define GPIO_IDR_IDR_3   0x00000008U
#define GPIO_IDR_IDR_4   0x00000010U
#define GPIO_IDR_IDR_5   0x00000020U
#define GPIO_IDR_IDR_6   0x00000040U
#define GPIO_IDR_IDR_7   0x00000080U
#define GPIO_IDR_IDR_8   0x00000100U
#define GPIO_IDR_IDR_9   0x00000200U
#define GPIO_LCKR_LCK0   0x00000001U
#define GPIO_LCKR_LCK1   0x00000002U
#define GPIO_LCKR_LCK10   0x00000400U
#define GPIO_LCKR_LCK11   0x00000800U
#define GPIO_LCKR_LCK12   0x00001000U
#define GPIO_LCKR_LCK13   0x00002000U
#define GPIO_LCKR_LCK14   0x00004000U
#define GPIO_LCKR_LCK15   0x00008000U
#define GPIO_LCKR_LCK2   0x00000004U
#define GPIO_LCKR_LCK3   0x00000008U
#define GPIO_LCKR_LCK4   0x00000010U
#define GPIO_LCKR_LCK5   0x00000020U
#define GPIO_LCKR_LCK6   0x00000040U
#define GPIO_LCKR_LCK7   0x00000080U
#define GPIO_LCKR_LCK8   0x00000100U
#define GPIO_LCKR_LCK9   0x00000200U
#define GPIO_LCKR_LCKK   0x00010000U
#define GPIO_MODER_MODER0   0x00000003U
#define GPIO_MODER_MODER0_0   0x00000001U
#define GPIO_MODER_MODER0_1   0x00000002U
#define GPIO_MODER_MODER1   0x0000000CU
#define GPIO_MODER_MODER10   0x00300000U
#define GPIO_MODER_MODER10_0   0x00100000U
#define GPIO_MODER_MODER10_1   0x00200000U
#define GPIO_MODER_MODER11   0x00C00000U
#define GPIO_MODER_MODER11_0   0x00400000U
#define GPIO_MODER_MODER11_1   0x00800000U
#define GPIO_MODER_MODER12   0x03000000U
#define GPIO_MODER_MODER12_0   0x01000000U
#define GPIO_MODER_MODER12_1   0x02000000U
#define GPIO_MODER_MODER13   0x0C000000U
#define GPIO_MODER_MODER13_0   0x04000000U
#define GPIO_MODER_MODER13_1   0x08000000U
#define GPIO_MODER_MODER14   0x30000000U
#define GPIO_MODER_MODER14_0   0x10000000U
#define GPIO_MODER_MODER14_1   0x20000000U
#define GPIO_MODER_MODER15   0xC0000000U
#define GPIO_MODER_MODER15_0   0x40000000U
#define GPIO_MODER_MODER15_1   0x80000000U
#define GPIO_MODER_MODER1_0   0x00000004U
#define GPIO_MODER_MODER1_1   0x00000008U
#define GPIO_MODER_MODER2   0x00000030U
#define GPIO_MODER_MODER2_0   0x00000010U
#define GPIO_MODER_MODER2_1   0x00000020U
#define GPIO_MODER_MODER3   0x000000C0U
#define GPIO_MODER_MODER3_0   0x00000040U
#define GPIO_MODER_MODER3_1   0x00000080U
#define GPIO_MODER_MODER4   0x00000300U
#define GPIO_MODER_MODER4_0   0x00000100U
#define GPIO_MODER_MODER4_1   0x00000200U
#define GPIO_MODER_MODER5   0x00000C00U
#define GPIO_MODER_MODER5_0   0x00000400U
#define GPIO_MODER_MODER5_1   0x00000800U
#define GPIO_MODER_MODER6   0x00003000U
#define GPIO_MODER_MODER6_0   0x00001000U
#define GPIO_MODER_MODER6_1   0x00002000U
#define GPIO_MODER_MODER7   0x0000C000U
#define GPIO_MODER_MODER7_0   0x00004000U
#define GPIO_MODER_MODER7_1   0x00008000U
#define GPIO_MODER_MODER8   0x00030000U
#define GPIO_MODER_MODER8_0   0x00010000U
#define GPIO_MODER_MODER8_1   0x00020000U
#define GPIO_MODER_MODER9   0x000C0000U
#define GPIO_MODER_MODER9_0   0x00040000U
#define GPIO_MODER_MODER9_1   0x00080000U
#define GPIO_ODR_ODR_0   0x00000001U
#define GPIO_ODR_ODR_1   0x00000002U
#define GPIO_ODR_ODR_10   0x00000400U
#define GPIO_ODR_ODR_11   0x00000800U
#define GPIO_ODR_ODR_12   0x00001000U
#define GPIO_ODR_ODR_13   0x00002000U
#define GPIO_ODR_ODR_14   0x00004000U
#define GPIO_ODR_ODR_15   0x00008000U
#define GPIO_ODR_ODR_2   0x00000004U
#define GPIO_ODR_ODR_3   0x00000008U
#define GPIO_ODR_ODR_4   0x00000010U
#define GPIO_ODR_ODR_5   0x00000020U
#define GPIO_ODR_ODR_6   0x00000040U
#define GPIO_ODR_ODR_7   0x00000080U
#define GPIO_ODR_ODR_8   0x00000100U
#define GPIO_ODR_ODR_9   0x00000200U
#define GPIO_OSPEEDER_OSPEEDR0   0x00000003U
#define GPIO_OSPEEDER_OSPEEDR0_0   0x00000001U
#define GPIO_OSPEEDER_OSPEEDR0_1   0x00000002U
#define GPIO_OSPEEDER_OSPEEDR1   0x0000000CU
#define GPIO_OSPEEDER_OSPEEDR10   0x00300000U
#define GPIO_OSPEEDER_OSPEEDR10_0   0x00100000U
#define GPIO_OSPEEDER_OSPEEDR10_1   0x00200000U
#define GPIO_OSPEEDER_OSPEEDR11   0x00C00000U
#define GPIO_OSPEEDER_OSPEEDR11_0   0x00400000U
#define GPIO_OSPEEDER_OSPEEDR11_1   0x00800000U
#define GPIO_OSPEEDER_OSPEEDR12   0x03000000U
#define GPIO_OSPEEDER_OSPEEDR12_0   0x01000000U
#define GPIO_OSPEEDER_OSPEEDR12_1   0x02000000U
#define GPIO_OSPEEDER_OSPEEDR13   0x0C000000U
#define GPIO_OSPEEDER_OSPEEDR13_0   0x04000000U
#define GPIO_OSPEEDER_OSPEEDR13_1   0x08000000U
#define GPIO_OSPEEDER_OSPEEDR14   0x30000000U
#define GPIO_OSPEEDER_OSPEEDR14_0   0x10000000U
#define GPIO_OSPEEDER_OSPEEDR14_1   0x20000000U
#define GPIO_OSPEEDER_OSPEEDR15   0xC0000000U
#define GPIO_OSPEEDER_OSPEEDR15_0   0x40000000U
#define GPIO_OSPEEDER_OSPEEDR15_1   0x80000000U
#define GPIO_OSPEEDER_OSPEEDR1_0   0x00000004U
#define GPIO_OSPEEDER_OSPEEDR1_1   0x00000008U
#define GPIO_OSPEEDER_OSPEEDR2   0x00000030U
#define GPIO_OSPEEDER_OSPEEDR2_0   0x00000010U
#define GPIO_OSPEEDER_OSPEEDR2_1   0x00000020U
#define GPIO_OSPEEDER_OSPEEDR3   0x000000C0U
#define GPIO_OSPEEDER_OSPEEDR3_0   0x00000040U
#define GPIO_OSPEEDER_OSPEEDR3_1   0x00000080U
#define GPIO_OSPEEDER_OSPEEDR4   0x00000300U
#define GPIO_OSPEEDER_OSPEEDR4_0   0x00000100U
#define GPIO_OSPEEDER_OSPEEDR4_1   0x00000200U
#define GPIO_OSPEEDER_OSPEEDR5   0x00000C00U
#define GPIO_OSPEEDER_OSPEEDR5_0   0x00000400U
#define GPIO_OSPEEDER_OSPEEDR5_1   0x00000800U
#define GPIO_OSPEEDER_OSPEEDR6   0x00003000U
#define GPIO_OSPEEDER_OSPEEDR6_0   0x00001000U
#define GPIO_OSPEEDER_OSPEEDR6_1   0x00002000U
#define GPIO_OSPEEDER_OSPEEDR7   0x0000C000U
#define GPIO_OSPEEDER_OSPEEDR7_0   0x00004000U
#define GPIO_OSPEEDER_OSPEEDR7_1   0x00008000U
#define GPIO_OSPEEDER_OSPEEDR8   0x00030000U
#define GPIO_OSPEEDER_OSPEEDR8_0   0x00010000U
#define GPIO_OSPEEDER_OSPEEDR8_1   0x00020000U
#define GPIO_OSPEEDER_OSPEEDR9   0x000C0000U
#define GPIO_OSPEEDER_OSPEEDR9_0   0x00040000U
#define GPIO_OSPEEDER_OSPEEDR9_1   0x00080000U
#define GPIO_OTYPER_OT_0   0x00000001U
#define GPIO_OTYPER_OT_1   0x00000002U
#define GPIO_OTYPER_OT_10   0x00000400U
#define GPIO_OTYPER_OT_11   0x00000800U
#define GPIO_OTYPER_OT_12   0x00001000U
#define GPIO_OTYPER_OT_13   0x00002000U
#define GPIO_OTYPER_OT_14   0x00004000U
#define GPIO_OTYPER_OT_15   0x00008000U
#define GPIO_OTYPER_OT_2   0x00000004U
#define GPIO_OTYPER_OT_3   0x00000008U
#define GPIO_OTYPER_OT_4   0x00000010U
#define GPIO_OTYPER_OT_5   0x00000020U
#define GPIO_OTYPER_OT_6   0x00000040U
#define GPIO_OTYPER_OT_7   0x00000080U
#define GPIO_OTYPER_OT_8   0x00000100U
#define GPIO_OTYPER_OT_9   0x00000200U
#define GPIO_PUPDR_PUPDR0   0x00000003U
#define GPIO_PUPDR_PUPDR0_0   0x00000001U
#define GPIO_PUPDR_PUPDR0_1   0x00000002U
#define GPIO_PUPDR_PUPDR1   0x0000000CU
#define GPIO_PUPDR_PUPDR10   0x00300000U
#define GPIO_PUPDR_PUPDR10_0   0x00100000U
#define GPIO_PUPDR_PUPDR10_1   0x00200000U
#define GPIO_PUPDR_PUPDR11   0x00C00000U
#define GPIO_PUPDR_PUPDR11_0   0x00400000U
#define GPIO_PUPDR_PUPDR11_1   0x00800000U
#define GPIO_PUPDR_PUPDR12   0x03000000U
#define GPIO_PUPDR_PUPDR12_0   0x01000000U
#define GPIO_PUPDR_PUPDR12_1   0x02000000U
#define GPIO_PUPDR_PUPDR13   0x0C000000U
#define GPIO_PUPDR_PUPDR13_0   0x04000000U
#define GPIO_PUPDR_PUPDR13_1   0x08000000U
#define GPIO_PUPDR_PUPDR14   0x30000000U
#define GPIO_PUPDR_PUPDR14_0   0x10000000U
#define GPIO_PUPDR_PUPDR14_1   0x20000000U
#define GPIO_PUPDR_PUPDR15   0xC0000000U
#define GPIO_PUPDR_PUPDR15_0   0x40000000U
#define GPIO_PUPDR_PUPDR15_1   0x80000000U
#define GPIO_PUPDR_PUPDR1_0   0x00000004U
#define GPIO_PUPDR_PUPDR1_1   0x00000008U
#define GPIO_PUPDR_PUPDR2   0x00000030U
#define GPIO_PUPDR_PUPDR2_0   0x00000010U
#define GPIO_PUPDR_PUPDR2_1   0x00000020U
#define GPIO_PUPDR_PUPDR3   0x000000C0U
#define GPIO_PUPDR_PUPDR3_0   0x00000040U
#define GPIO_PUPDR_PUPDR3_1   0x00000080U
#define GPIO_PUPDR_PUPDR4   0x00000300U
#define GPIO_PUPDR_PUPDR4_0   0x00000100U
#define GPIO_PUPDR_PUPDR4_1   0x00000200U
#define GPIO_PUPDR_PUPDR5   0x00000C00U
#define GPIO_PUPDR_PUPDR5_0   0x00000400U
#define GPIO_PUPDR_PUPDR5_1   0x00000800U
#define GPIO_PUPDR_PUPDR6   0x00003000U
#define GPIO_PUPDR_PUPDR6_0   0x00001000U
#define GPIO_PUPDR_PUPDR6_1   0x00002000U
#define GPIO_PUPDR_PUPDR7   0x0000C000U
#define GPIO_PUPDR_PUPDR7_0   0x00004000U
#define GPIO_PUPDR_PUPDR7_1   0x00008000U
#define GPIO_PUPDR_PUPDR8   0x00030000U
#define GPIO_PUPDR_PUPDR8_0   0x00010000U
#define GPIO_PUPDR_PUPDR8_1   0x00020000U
#define GPIO_PUPDR_PUPDR9   0x000C0000U
#define GPIO_PUPDR_PUPDR9_0   0x00040000U
#define GPIO_PUPDR_PUPDR9_1   0x00080000U
#define I2C_CR1_ADDRIE   0x00000008U

Address match interrupt enable

#define I2C_CR1_ALERTEN   0x00400000U

SMBus alert enable

#define I2C_CR1_ANFOFF   0x00001000U

Analog noise filter OFF

#define I2C_CR1_DFN   I2C_CR1_DNF

Digital noise filter

#define I2C_CR1_DNF   0x00000F00U

Digital noise filter

#define I2C_CR1_ERRIE   0x00000080U

Errors interrupt enable

#define I2C_CR1_GCEN   0x00080000U

General call enable

#define I2C_CR1_NACKIE   0x00000010U

NACK received interrupt enable

#define I2C_CR1_NOSTRETCH   0x00020000U

Clock stretching disable

#define I2C_CR1_PE   0x00000001U

Peripheral enable

#define I2C_CR1_PECEN   0x00800000U

PEC enable

#define I2C_CR1_RXDMAEN   0x00008000U

DMA reception requests enable

#define I2C_CR1_RXIE   0x00000004U

RX interrupt enable

#define I2C_CR1_SBC   0x00010000U

Slave byte control

#define I2C_CR1_SMBDEN   0x00200000U

SMBus device default address enable

#define I2C_CR1_SMBHEN   0x00100000U

SMBus host address enable

#define I2C_CR1_STOPIE   0x00000020U

STOP detection interrupt enable

#define I2C_CR1_TCIE   0x00000040U

Transfer complete interrupt enable

#define I2C_CR1_TXDMAEN   0x00004000U

DMA transmission requests enable

#define I2C_CR1_TXIE   0x00000002U

TX interrupt enable

#define I2C_CR2_ADD10   0x00000800U

10-bit addressing mode (master mode)

#define I2C_CR2_AUTOEND   0x02000000U

Automatic end mode (master mode)

#define I2C_CR2_HEAD10R   0x00001000U

10-bit address header only read direction (master mode)

#define I2C_CR2_NACK   0x00008000U

NACK generation (slave mode)

#define I2C_CR2_NBYTES   0x00FF0000U

Number of bytes

#define I2C_CR2_PECBYTE   0x04000000U

Packet error checking byte

#define I2C_CR2_RD_WRN   0x00000400U

Transfer direction (master mode)

#define I2C_CR2_RELOAD   0x01000000U

NBYTES reload mode

#define I2C_CR2_SADD   0x000003FFU

Slave address (master mode)

#define I2C_CR2_START   0x00002000U

START generation

#define I2C_CR2_STOP   0x00004000U

STOP generation (master mode)

#define I2C_ICR_ADDRCF   0x00000008U

Address matched clear flag

#define I2C_ICR_ALERTCF   0x00002000U

Alert clear flag

#define I2C_ICR_ARLOCF   0x00000200U

Arbitration lost clear flag

#define I2C_ICR_BERRCF   0x00000100U

Bus error clear flag

#define I2C_ICR_NACKCF   0x00000010U

NACK clear flag

#define I2C_ICR_OVRCF   0x00000400U

Overrun/Underrun clear flag

#define I2C_ICR_PECCF   0x00000800U

PAC error clear flag

#define I2C_ICR_STOPCF   0x00000020U

STOP detection clear flag

#define I2C_ICR_TIMOUTCF   0x00001000U

Timeout clear flag

#define I2C_ISR_ADDCODE   0x00FE0000U

Address match code (slave mode)

#define I2C_ISR_ADDR   0x00000008U

Address matched (slave mode)

#define I2C_ISR_ALERT   0x00002000U

SMBus alert

#define I2C_ISR_ARLO   0x00000200U

Arbitration lost

#define I2C_ISR_BERR   0x00000100U

Bus error

#define I2C_ISR_BUSY   0x00008000U

Bus busy

#define I2C_ISR_DIR   0x00010000U

Transfer direction (slave mode)

#define I2C_ISR_NACKF   0x00000010U

NACK received flag

#define I2C_ISR_OVR   0x00000400U

Overrun/Underrun

#define I2C_ISR_PECERR   0x00000800U

PEC error in reception

#define I2C_ISR_RXNE   0x00000004U

Receive data register not empty

#define I2C_ISR_STOPF   0x00000020U

STOP detection flag

#define I2C_ISR_TC   0x00000040U

Transfer complete (master mode)

#define I2C_ISR_TCR   0x00000080U

Transfer complete reload

#define I2C_ISR_TIMEOUT   0x00001000U

Timeout or Tlow detection flag

#define I2C_ISR_TXE   0x00000001U

Transmit data register empty

#define I2C_ISR_TXIS   0x00000002U

Transmit interrupt status

#define I2C_OAR1_OA1   0x000003FFU

Interface own address 1

#define I2C_OAR1_OA1EN   0x00008000U

Own address 1 enable

#define I2C_OAR1_OA1MODE   0x00000400U

Own address 1 10-bit mode

#define I2C_OAR2_OA2   0x000000FEU

Interface own address 2

#define I2C_OAR2_OA2EN   0x00008000U

Own address 2 enable

#define I2C_OAR2_OA2MASK01   0x00000100U

OA2[1] is masked, Only OA2[7:2] are compared

#define I2C_OAR2_OA2MASK02   0x00000200U

OA2[2:1] is masked, Only OA2[7:3] are compared

#define I2C_OAR2_OA2MASK03   0x00000300U

OA2[3:1] is masked, Only OA2[7:4] are compared

#define I2C_OAR2_OA2MASK04   0x00000400U

OA2[4:1] is masked, Only OA2[7:5] are compared

#define I2C_OAR2_OA2MASK05   0x00000500U

OA2[5:1] is masked, Only OA2[7:6] are compared

#define I2C_OAR2_OA2MASK06   0x00000600U

OA2[6:1] is masked, Only OA2[7] are compared

#define I2C_OAR2_OA2MASK07   0x00000700U

OA2[7:1] is masked, No comparison is done

#define I2C_OAR2_OA2MSK   0x00000700U

Own address 2 masks

#define I2C_OAR2_OA2NOMASK   0x00000000U

No mask

#define I2C_PECR_PEC   0x000000FFU

PEC register

#define I2C_RXDR_RXDATA   0x000000FFU

8-bit receive data

#define I2C_TIMEOUTR_TEXTEN   0x80000000U

Extended clock timeout enable

#define I2C_TIMEOUTR_TIDLE   0x00001000U

Idle clock timeout detection

#define I2C_TIMEOUTR_TIMEOUTA   0x00000FFFU

Bus timeout A

#define I2C_TIMEOUTR_TIMEOUTB   0x0FFF0000U

Bus timeout B

#define I2C_TIMEOUTR_TIMOUTEN   0x00008000U

Clock timeout enable

#define I2C_TIMINGR_PRESC   0xF0000000U

Timings prescaler

#define I2C_TIMINGR_SCLDEL   0x00F00000U

Data setup time

#define I2C_TIMINGR_SCLH   0x0000FF00U

SCL high period (master mode)

#define I2C_TIMINGR_SCLL   0x000000FFU

SCL low period (master mode)

#define I2C_TIMINGR_SDADEL   0x000F0000U

Data hold time

#define I2C_TXDR_TXDATA   0x000000FFU

8-bit transmit data

#define IWDG_KR_KEY   0xFFFFU

Key value (write only, read 0000h)

#define IWDG_PR_PR   0x07U

PR[2:0] (Prescaler divider)

#define IWDG_PR_PR_0   0x01U

Bit 0

#define IWDG_PR_PR_1   0x02U

Bit 1

#define IWDG_PR_PR_2   0x04U

Bit 2

#define IWDG_RLR_RL   0x0FFFU

Watchdog counter reload value

#define IWDG_SR_PVU   0x01U

Watchdog prescaler value update

#define IWDG_SR_RVU   0x02U

Watchdog counter reload value update

#define IWDG_SR_WVU   0x04U

Watchdog counter window value update

#define IWDG_WINR_WIN   0x0FFFU

Watchdog counter window value

#define LPTIM_ARR_ARR   0x0000FFFFU

Auto reload register

#define LPTIM_CFGR_CKFLT   0x00000018U

CKFLT[1:0] bits (Configurable digital filter for external clock)

#define LPTIM_CFGR_CKFLT_0   0x00000008U

Bit 0

#define LPTIM_CFGR_CKFLT_1   0x00000010U

Bit 1

#define LPTIM_CFGR_CKPOL   0x00000006U

CKPOL[1:0] bits (Clock polarity)

#define LPTIM_CFGR_CKPOL_0   0x00000002U

Bit 0

#define LPTIM_CFGR_CKPOL_1   0x00000004U

Bit 1

#define LPTIM_CFGR_CKSEL   0x00000001U

Clock selector

#define LPTIM_CFGR_COUNTMODE   0x00800000U

Counter mode enable

#define LPTIM_CFGR_ENC   0x01000000U

Encoder mode enable

#define LPTIM_CFGR_PRELOAD   0x00400000U

Reg update mode

#define LPTIM_CFGR_PRESC   0x00000E00U

PRESC[2:0] bits (Clock prescaler)

#define LPTIM_CFGR_PRESC_0   0x00000200U

Bit 0

#define LPTIM_CFGR_PRESC_1   0x00000400U

Bit 1

#define LPTIM_CFGR_PRESC_2   0x00000800U

Bit 2

#define LPTIM_CFGR_TIMOUT   0x00080000U

Timout enable

#define LPTIM_CFGR_TRGFLT   0x000000C0U

TRGFLT[1:0] bits (Configurable digital filter for trigger)

#define LPTIM_CFGR_TRGFLT_0   0x00000040U

Bit 0

#define LPTIM_CFGR_TRGFLT_1   0x00000080U

Bit 1

#define LPTIM_CFGR_TRIGEN   0x00060000U

TRIGEN[1:0] bits (Trigger enable and polarity)

#define LPTIM_CFGR_TRIGEN_0   0x00020000U

Bit 0

#define LPTIM_CFGR_TRIGEN_1   0x00040000U

Bit 1

#define LPTIM_CFGR_TRIGSEL   0x0000E000U

TRIGSEL[2:0]] bits (Trigger selector)

#define LPTIM_CFGR_TRIGSEL_0   0x00002000U

Bit 0

#define LPTIM_CFGR_TRIGSEL_1   0x00004000U

Bit 1

#define LPTIM_CFGR_TRIGSEL_2   0x00008000U

Bit 2

#define LPTIM_CFGR_WAVE   0x00100000U

Waveform shape

#define LPTIM_CFGR_WAVPOL   0x00200000U

Waveform shape polarity

#define LPTIM_CMP_CMP   0x0000FFFFU

Compare register

#define LPTIM_CNT_CNT   0x0000FFFFU

Counter register

#define LPTIM_CR_CNTSTRT   0x00000004U

Timer start in continuous mode

#define LPTIM_CR_ENABLE   0x00000001U

LPTIMer enable

#define LPTIM_CR_SNGSTRT   0x00000002U

Timer start in single mode

#define LPTIM_ICR_ARRMCF   0x00000002U

Autoreload match Clear Flag

#define LPTIM_ICR_ARROKCF   0x00000010U

Autoreload register update OK Clear Flag

#define LPTIM_ICR_CMPMCF   0x00000001U

Compare match Clear Flag

#define LPTIM_ICR_CMPOKCF   0x00000008U

Compare register update OK Clear Flag

#define LPTIM_ICR_DOWNCF   0x00000040U

Counter direction change up to down Clear Flag

#define LPTIM_ICR_EXTTRIGCF   0x00000004U

External trigger edge event Clear Flag

#define LPTIM_ICR_UPCF   0x00000020U

Counter direction change down to up Clear Flag

#define LPTIM_IER_ARRMIE   0x00000002U

Autoreload match Interrupt Enable

#define LPTIM_IER_ARROKIE   0x00000010U

Autoreload register update OK Interrupt Enable

#define LPTIM_IER_CMPMIE   0x00000001U

Compare match Interrupt Enable

#define LPTIM_IER_CMPOKIE   0x00000008U

Compare register update OK Interrupt Enable

#define LPTIM_IER_DOWNIE   0x00000040U

Counter direction change up to down Interrupt Enable

#define LPTIM_IER_EXTTRIGIE   0x00000004U

External trigger edge event Interrupt Enable

#define LPTIM_IER_UPIE   0x00000020U

Counter direction change down to up Interrupt Enable

#define LPTIM_ISR_ARRM   0x00000002U

Autoreload match

#define LPTIM_ISR_ARROK   0x00000010U

Autoreload register update OK

#define LPTIM_ISR_CMPM   0x00000001U

Compare match

#define LPTIM_ISR_CMPOK   0x00000008U

Compare register update OK

#define LPTIM_ISR_DOWN   0x00000040U

Counter direction change up to down

#define LPTIM_ISR_EXTTRIG   0x00000004U

External trigger edge event

#define LPTIM_ISR_UP   0x00000020U

Counter direction change down to up

#define LTDC_AWCR_AAH   0x000007FFU

Accumulated Active heigh

#define LTDC_AWCR_AAW   0x0FFF0000U

Accumulated Active Width

#define LTDC_BCCR_BCBLUE   0x000000FFU

Background Blue value

#define LTDC_BCCR_BCGREEN   0x0000FF00U

Background Green value

#define LTDC_BCCR_BCRED   0x00FF0000U

Background Red value

#define LTDC_BPCR_AHBP   0x0FFF0000U

Accumulated Horizontal Back Porch

#define LTDC_BPCR_AVBP   0x000007FFU

Accumulated Vertical Back Porch

#define LTDC_CDSR_HDES   0x00000002U

Horizontal Data Enable Status

#define LTDC_CDSR_HSYNCS   0x00000008U

Horizontal Synchronization Status

#define LTDC_CDSR_VDES   0x00000001U

Vertical Data Enable Status

#define LTDC_CDSR_VSYNCS   0x00000004U

Vertical Synchronization Status

#define LTDC_CPSR_CXPOS   0xFFFF0000U

Current X Position

#define LTDC_CPSR_CYPOS   0x0000FFFFU

Current Y Position

#define LTDC_GCR_DBW   0x00000070U

Dither Blue Width

#define LTDC_GCR_DEN   0x00010000U

Dither Enable

#define LTDC_GCR_DEPOL   0x20000000U

Data Enable Polarity

#define LTDC_GCR_DGW   0x00000700U

Dither Green Width

#define LTDC_GCR_DRW   0x00007000U

Dither Red Width

#define LTDC_GCR_DTEN   LTDC_GCR_DEN
#define LTDC_GCR_HSPOL   0x80000000U

Horizontal Synchronization Polarity

#define LTDC_GCR_LTDCEN   0x00000001U

LCD-TFT controller enable bit

#define LTDC_GCR_PCPOL   0x10000000U

Pixel Clock Polarity

#define LTDC_GCR_VSPOL   0x40000000U

Vertical Synchronization Polarity

#define LTDC_ICR_CFUIF   0x00000002U

Clears the FIFO Underrun Interrupt Flag

#define LTDC_ICR_CLIF   0x00000001U

Clears the Line Interrupt Flag

#define LTDC_ICR_CRRIF   0x00000008U

Clears Register Reload interrupt Flag

#define LTDC_ICR_CTERRIF   0x00000004U

Clears the Transfer Error Interrupt Flag

#define LTDC_IER_FUIE   0x00000002U

FIFO Underrun Interrupt Enable

#define LTDC_IER_LIE   0x00000001U

Line Interrupt Enable

#define LTDC_IER_RRIE   0x00000008U

Register Reload interrupt enable

#define LTDC_IER_TERRIE   0x00000004U

Transfer Error Interrupt Enable

#define LTDC_ISR_FUIF   0x00000002U

FIFO Underrun Interrupt Flag

#define LTDC_ISR_LIF   0x00000001U

Line Interrupt Flag

#define LTDC_ISR_RRIF   0x00000008U

Register Reload interrupt Flag

#define LTDC_ISR_TERRIF   0x00000004U

Transfer Error Interrupt Flag

#define LTDC_LIPCR_LIPOS   0x000007FFU

Line Interrupt Position

#define LTDC_LxBFCR_BF1   0x00000700U

Blending Factor 1

#define LTDC_LxBFCR_BF2   0x00000007U

Blending Factor 2

#define LTDC_LxCACR_CONSTA   0x000000FFU

Constant Alpha

#define LTDC_LxCFBAR_CFBADD   0xFFFFFFFFU

Color Frame Buffer Start Address

#define LTDC_LxCFBLNR_CFBLNBR   0x000007FFU

Frame Buffer Line Number

#define LTDC_LxCFBLR_CFBLL   0x00001FFFU

Color Frame Buffer Line Length

#define LTDC_LxCFBLR_CFBP   0x1FFF0000U

Color Frame Buffer Pitch in bytes

#define LTDC_LxCKCR_CKBLUE   0x000000FFU

Color Key Blue value

#define LTDC_LxCKCR_CKGREEN   0x0000FF00U

Color Key Green value

#define LTDC_LxCKCR_CKRED   0x00FF0000U

Color Key Red value

#define LTDC_LxCLUTWR_BLUE   0x000000FFU

Blue value

#define LTDC_LxCLUTWR_CLUTADD   0xFF000000U

CLUT address

#define LTDC_LxCLUTWR_GREEN   0x0000FF00U

Green value

#define LTDC_LxCLUTWR_RED   0x00FF0000U

Red value

#define LTDC_LxCR_CLUTEN   0x00000010U

Color Lockup Table Enable

#define LTDC_LxCR_COLKEN   0x00000002U

Color Keying Enable

#define LTDC_LxCR_LEN   0x00000001U

Layer Enable

#define LTDC_LxDCCR_DCALPHA   0xFF000000U

Default Color Alpha

#define LTDC_LxDCCR_DCBLUE   0x000000FFU

Default Color Blue

#define LTDC_LxDCCR_DCGREEN   0x0000FF00U

Default Color Green

#define LTDC_LxDCCR_DCRED   0x00FF0000U

Default Color Red

#define LTDC_LxPFCR_PF   0x00000007U

Pixel Format

#define LTDC_LxWHPCR_WHSPPOS   0xFFFF0000U

Window Horizontal Stop Position

#define LTDC_LxWHPCR_WHSTPOS   0x00000FFFU

Window Horizontal Start Position

#define LTDC_LxWVPCR_WVSPPOS   0xFFFF0000U

Window Vertical Stop Position

#define LTDC_LxWVPCR_WVSTPOS   0x00000FFFU

Window Vertical Start Position

#define LTDC_SRCR_IMR   0x00000001U

Immediate Reload

#define LTDC_SRCR_VBR   0x00000002U

Vertical Blanking Reload

#define LTDC_SSCR_HSW   0x0FFF0000U

Horizontal Synchronization Width

#define LTDC_SSCR_VSH   0x000007FFU

Vertical Synchronization Height

#define LTDC_TWCR_TOTALH   0x000007FFU

Total Heigh

#define LTDC_TWCR_TOTALW   0x0FFF0000U

Total Width

#define PWR_CR1_ADCDC1   0x00002000U

Refer to AN4073 on how to use this bit

#define PWR_CR1_CSBF   0x00000008U

Clear Standby Flag

#define PWR_CR1_DBP   0x00000100U

Disable Backup Domain write protection

#define PWR_CR1_FPDS   0x00000200U

Flash power down in Stop mode

#define PWR_CR1_LPDS   0x00000001U

Low-Power Deepsleep

#define PWR_CR1_LPUDS   0x00000400U

Low-power regulator in deepsleep under-drive mode

#define PWR_CR1_MRUDS   0x00000800U

Main regulator in deepsleep under-drive mode

#define PWR_CR1_ODEN   0x00010000U

Over Drive enable

#define PWR_CR1_ODSWEN   0x00020000U

Over Drive switch enabled

#define PWR_CR1_PDDS   0x00000002U

Power Down Deepsleep

#define PWR_CR1_PLS   0x000000E0U

PLS[2:0] bits (PVD Level Selection)

#define PWR_CR1_PLS_0   0x00000020U

Bit 0

#define PWR_CR1_PLS_1   0x00000040U

Bit 1

#define PWR_CR1_PLS_2   0x00000080U

Bit 2 PVD level configuration

#define PWR_CR1_PLS_LEV0   0x00000000U

PVD level 0

#define PWR_CR1_PLS_LEV1   0x00000020U

PVD level 1

#define PWR_CR1_PLS_LEV2   0x00000040U

PVD level 2

#define PWR_CR1_PLS_LEV3   0x00000060U

PVD level 3

#define PWR_CR1_PLS_LEV4   0x00000080U

PVD level 4

#define PWR_CR1_PLS_LEV5   0x000000A0U

PVD level 5

#define PWR_CR1_PLS_LEV6   0x000000C0U

PVD level 6

#define PWR_CR1_PLS_LEV7   0x000000E0U

PVD level 7

#define PWR_CR1_PVDE   0x00000010U

Power Voltage Detector Enable

#define PWR_CR1_UDEN   0x000C0000U

Under Drive enable in stop mode

#define PWR_CR1_UDEN_0   0x00040000U

Bit 0

#define PWR_CR1_UDEN_1   0x00080000U

Bit 1

#define PWR_CR1_VOS   0x0000C000U

VOS[1:0] bits (Regulator voltage scaling output selection)

#define PWR_CR1_VOS_0   0x00004000U

Bit 0

#define PWR_CR1_VOS_1   0x00008000U

Bit 1

#define PWR_CR2_CWUPF1   0x00000001U

Clear Wakeup Pin Flag for PA0

#define PWR_CR2_CWUPF2   0x00000002U

Clear Wakeup Pin Flag for PA2

#define PWR_CR2_CWUPF3   0x00000004U

Clear Wakeup Pin Flag for PC1

#define PWR_CR2_CWUPF4   0x00000008U

Clear Wakeup Pin Flag for PC13

#define PWR_CR2_CWUPF5   0x00000010U

Clear Wakeup Pin Flag for PI8

#define PWR_CR2_CWUPF6   0x00000020U

Clear Wakeup Pin Flag for PI11

#define PWR_CR2_WUPP1   0x00000100U

Wakeup Pin Polarity bit for PA0

#define PWR_CR2_WUPP2   0x00000200U

Wakeup Pin Polarity bit for PA2

#define PWR_CR2_WUPP3   0x00000400U

Wakeup Pin Polarity bit for PC1

#define PWR_CR2_WUPP4   0x00000800U

Wakeup Pin Polarity bit for PC13

#define PWR_CR2_WUPP5   0x00001000U

Wakeup Pin Polarity bit for PI8

#define PWR_CR2_WUPP6   0x00002000U

Wakeup Pin Polarity bit for PI11

#define PWR_CSR1_BRE   0x00000200U

Backup regulator enable

#define PWR_CSR1_BRR   0x00000008U

Backup regulator ready

#define PWR_CSR1_EIWUP   0x00000100U

Enable internal wakeup

#define PWR_CSR1_ODRDY   0x00010000U

Over Drive generator ready

#define PWR_CSR1_ODSWRDY   0x00020000U

Over Drive Switch ready

#define PWR_CSR1_PVDO   0x00000004U

PVD Output

#define PWR_CSR1_SBF   0x00000002U

Standby Flag

#define PWR_CSR1_UDRDY   0x000C0000U

Under Drive ready

#define PWR_CSR1_UDSWRDY   PWR_CSR1_UDRDY
#define PWR_CSR1_VOSRDY   0x00004000U

Regulator voltage scaling output selection ready

#define PWR_CSR1_WUIF   0x00000001U

Wake up internal Flag

#define PWR_CSR2_EWUP1   0x00000100U

Enable Wakeup Pin PA0

#define PWR_CSR2_EWUP2   0x00000200U

Enable Wakeup Pin PA2

#define PWR_CSR2_EWUP3   0x00000400U

Enable Wakeup Pin PC1

#define PWR_CSR2_EWUP4   0x00000800U

Enable Wakeup Pin PC13

#define PWR_CSR2_EWUP5   0x00001000U

Enable Wakeup Pin PI8

#define PWR_CSR2_EWUP6   0x00002000U

Enable Wakeup Pin PI11

#define PWR_CSR2_WUPF1   0x00000001U

Wakeup Pin Flag for PA0

#define PWR_CSR2_WUPF2   0x00000002U

Wakeup Pin Flag for PA2

#define PWR_CSR2_WUPF3   0x00000004U

Wakeup Pin Flag for PC1

#define PWR_CSR2_WUPF4   0x00000008U

Wakeup Pin Flag for PC13

#define PWR_CSR2_WUPF5   0x00000010U

Wakeup Pin Flag for PI8

#define PWR_CSR2_WUPF6   0x00000020U

Wakeup Pin Flag for PI11

#define QSPI1_V1_0
#define QUADSPI_ABR_ALTERNATE   0xFFFFFFFFU

ALTERNATE[31:0]: Alternate Bytes

#define QUADSPI_AR_ADDRESS   0xFFFFFFFFU

ADDRESS[31:0]: Address

#define QUADSPI_CCR_ABMODE   0x0000C000U

ABMODE[1:0]: Alternate Bytes Mode

#define QUADSPI_CCR_ABMODE_0   0x00004000U

Bit 0

#define QUADSPI_CCR_ABMODE_1   0x00008000U

Bit 1

#define QUADSPI_CCR_ABSIZE   0x00030000U

ABSIZE[1:0]: Instruction Mode

#define QUADSPI_CCR_ABSIZE_0   0x00010000U

Bit 0

#define QUADSPI_CCR_ABSIZE_1   0x00020000U

Bit 1

#define QUADSPI_CCR_ADMODE   0x00000C00U

ADMODE[1:0]: Address Mode

#define QUADSPI_CCR_ADMODE_0   0x00000400U

Bit 0

#define QUADSPI_CCR_ADMODE_1   0x00000800U

Bit 1

#define QUADSPI_CCR_ADSIZE   0x00003000U

ADSIZE[1:0]: Address Size

#define QUADSPI_CCR_ADSIZE_0   0x00001000U

Bit 0

#define QUADSPI_CCR_ADSIZE_1   0x00002000U

Bit 1

#define QUADSPI_CCR_DCYC   0x007C0000U

DCYC[4:0]: Dummy Cycles

#define QUADSPI_CCR_DCYC_0   0x00040000U

Bit 0

#define QUADSPI_CCR_DCYC_1   0x00080000U

Bit 1

#define QUADSPI_CCR_DCYC_2   0x00100000U

Bit 2

#define QUADSPI_CCR_DCYC_3   0x00200000U

Bit 3

#define QUADSPI_CCR_DCYC_4   0x00400000U

Bit 4

#define QUADSPI_CCR_DDRM   0x80000000U

DDRM: Double Data Rate Mode

#define QUADSPI_CCR_DHHC   0x40000000U

DHHC: Delay Half Hclk Cycle

#define QUADSPI_CCR_DMODE   0x03000000U

DMODE[1:0]: Data Mode

#define QUADSPI_CCR_DMODE_0   0x01000000U

Bit 0

#define QUADSPI_CCR_DMODE_1   0x02000000U

Bit 1

#define QUADSPI_CCR_FMODE   0x0C000000U

FMODE[1:0]: Functional Mode

#define QUADSPI_CCR_FMODE_0   0x04000000U

Bit 0

#define QUADSPI_CCR_FMODE_1   0x08000000U

Bit 1

#define QUADSPI_CCR_IMODE   0x00000300U

IMODE[1:0]: Instruction Mode

#define QUADSPI_CCR_IMODE_0   0x00000100U

Bit 0

#define QUADSPI_CCR_IMODE_1   0x00000200U

Bit 1

#define QUADSPI_CCR_INSTRUCTION   0x000000FFU

INSTRUCTION[7:0]: Instruction

#define QUADSPI_CCR_INSTRUCTION_0   0x00000001U

Bit 0

#define QUADSPI_CCR_INSTRUCTION_1   0x00000002U

Bit 1

#define QUADSPI_CCR_INSTRUCTION_2   0x00000004U

Bit 2

#define QUADSPI_CCR_INSTRUCTION_3   0x00000008U

Bit 3

#define QUADSPI_CCR_INSTRUCTION_4   0x00000010U

Bit 4

#define QUADSPI_CCR_INSTRUCTION_5   0x00000020U

Bit 5

#define QUADSPI_CCR_INSTRUCTION_6   0x00000040U

Bit 6

#define QUADSPI_CCR_INSTRUCTION_7   0x00000080U

Bit 7

#define QUADSPI_CCR_SIOO   0x10000000U

SIOO: Send Instruction Only Once Mode

#define QUADSPI_CR_ABORT   0x00000002U

Abort request

#define QUADSPI_CR_APMS   0x00400000U

Bit 1

#define QUADSPI_CR_DFM   0x00000040U

Dual Flash Mode

#define QUADSPI_CR_DMAEN   0x00000004U

DMA Enable

#define QUADSPI_CR_EN   0x00000001U

Enable

#define QUADSPI_CR_FSEL   0x00000080U

Flash Select

#define QUADSPI_CR_FTHRES   0x00001F00U

FTHRES[4:0] FIFO Level

#define QUADSPI_CR_FTHRES_0   0x00000100U

Bit 0

#define QUADSPI_CR_FTHRES_1   0x00000200U

Bit 1

#define QUADSPI_CR_FTHRES_2   0x00000400U

Bit 2

#define QUADSPI_CR_FTHRES_3   0x00000800U

Bit 3

#define QUADSPI_CR_FTHRES_4   0x00001000U

Bit 4

#define QUADSPI_CR_FTIE   0x00040000U

FIFO Threshold Interrupt Enable

#define QUADSPI_CR_PMM   0x00800000U

Polling Match Mode

#define QUADSPI_CR_PRESCALER   0xFF000000U

PRESCALER[7:0] Clock prescaler

#define QUADSPI_CR_PRESCALER_0   0x01000000U

Bit 0

#define QUADSPI_CR_PRESCALER_1   0x02000000U

Bit 1

#define QUADSPI_CR_PRESCALER_2   0x04000000U

Bit 2

#define QUADSPI_CR_PRESCALER_3   0x08000000U

Bit 3

#define QUADSPI_CR_PRESCALER_4   0x10000000U

Bit 4

#define QUADSPI_CR_PRESCALER_5   0x20000000U

Bit 5

#define QUADSPI_CR_PRESCALER_6   0x40000000U

Bit 6

#define QUADSPI_CR_PRESCALER_7   0x80000000U

Bit 7

#define QUADSPI_CR_SMIE   0x00080000U

Status Match Interrupt Enable

#define QUADSPI_CR_SSHIFT   0x00000010U

Sample Shift

#define QUADSPI_CR_TCEN   0x00000008U

Timeout Counter Enable

#define QUADSPI_CR_TCIE   0x00020000U

Transfer Complete Interrupt Enable

#define QUADSPI_CR_TEIE   0x00010000U

Transfer Error Interrupt Enable

#define QUADSPI_CR_TOIE   0x00100000U

TimeOut Interrupt Enable

#define QUADSPI_DCR_CKMODE   0x00000001U

Mode 0 / Mode 3

#define QUADSPI_DCR_CSHT   0x00000700U

CSHT[2:0]: ChipSelect High Time

#define QUADSPI_DCR_CSHT_0   0x00000100U

Bit 0

#define QUADSPI_DCR_CSHT_1   0x00000200U

Bit 1

#define QUADSPI_DCR_CSHT_2   0x00000400U

Bit 2

#define QUADSPI_DCR_FSIZE   0x001F0000U

FSIZE[4:0]: Flash Size

#define QUADSPI_DCR_FSIZE_0   0x00010000U

Bit 0

#define QUADSPI_DCR_FSIZE_1   0x00020000U

Bit 1

#define QUADSPI_DCR_FSIZE_2   0x00040000U

Bit 2

#define QUADSPI_DCR_FSIZE_3   0x00080000U

Bit 3

#define QUADSPI_DCR_FSIZE_4   0x00100000U

Bit 4

#define QUADSPI_DLR_DL   0xFFFFFFFFU

DL[31:0]: Data Length

#define QUADSPI_DR_DATA   0xFFFFFFFFU

DATA[31:0]: Data

#define QUADSPI_FCR_CSMF   0x00000008U

Clear Status Match Flag

#define QUADSPI_FCR_CTCF   0x00000002U

Clear Transfer Complete Flag

#define QUADSPI_FCR_CTEF   0x00000001U

Clear Transfer Error Flag

#define QUADSPI_FCR_CTOF   0x00000010U

Clear Timeout Flag

#define QUADSPI_LPTR_TIMEOUT   0x0000FFFFU

TIMEOUT[15:0]: Timeout period

#define QUADSPI_PIR_INTERVAL   0x0000FFFFU

INTERVAL[15:0]: Polling Interval

#define QUADSPI_PSMAR_MATCH   0xFFFFFFFFU

MATCH[31:0]: Status Match

#define QUADSPI_PSMKR_MASK   0xFFFFFFFFU

MASK[31:0]: Status Mask

#define QUADSPI_SR_BUSY   0x00000020U

Busy

#define QUADSPI_SR_FLEVEL   0x00001F00U

FIFO Threshlod Flag

#define QUADSPI_SR_FLEVEL_0   0x00000100U

Bit 0

#define QUADSPI_SR_FLEVEL_1   0x00000200U

Bit 1

#define QUADSPI_SR_FLEVEL_2   0x00000400U

Bit 2

#define QUADSPI_SR_FLEVEL_3   0x00000800U

Bit 3

#define QUADSPI_SR_FLEVEL_4   0x00001000U

Bit 4

#define QUADSPI_SR_FTF   0x00000004U

FIFO Threshlod Flag

#define QUADSPI_SR_SMF   0x00000008U

Status Match Flag

#define QUADSPI_SR_TCF   0x00000002U

Transfer Complete Flag

#define QUADSPI_SR_TEF   0x00000001U

Transfer Error Flag

#define QUADSPI_SR_TOF   0x00000010U

Timeout Flag

#define RCC_AHB1ENR_BKPSRAMEN   0x00040000U
#define RCC_AHB1ENR_CRCEN   0x00001000U
#define RCC_AHB1ENR_DMA1EN   0x00200000U
#define RCC_AHB1ENR_DMA2DEN   0x00800000U
#define RCC_AHB1ENR_DMA2EN   0x00400000U
#define RCC_AHB1ENR_DTCMRAMEN   0x00100000U
#define RCC_AHB1ENR_ETHMACEN   0x02000000U
#define RCC_AHB1ENR_ETHMACPTPEN   0x10000000U
#define RCC_AHB1ENR_ETHMACRXEN   0x08000000U
#define RCC_AHB1ENR_ETHMACTXEN   0x04000000U
#define RCC_AHB1ENR_GPIOAEN   0x00000001U
#define RCC_AHB1ENR_GPIOBEN   0x00000002U
#define RCC_AHB1ENR_GPIOCEN   0x00000004U
#define RCC_AHB1ENR_GPIODEN   0x00000008U
#define RCC_AHB1ENR_GPIOEEN   0x00000010U
#define RCC_AHB1ENR_GPIOFEN   0x00000020U
#define RCC_AHB1ENR_GPIOGEN   0x00000040U
#define RCC_AHB1ENR_GPIOHEN   0x00000080U
#define RCC_AHB1ENR_GPIOIEN   0x00000100U
#define RCC_AHB1ENR_GPIOJEN   0x00000200U
#define RCC_AHB1ENR_GPIOKEN   0x00000400U
#define RCC_AHB1ENR_OTGHSEN   0x20000000U
#define RCC_AHB1ENR_OTGHSULPIEN   0x40000000U
#define RCC_AHB1LPENR_AXILPEN   0x00002000U
#define RCC_AHB1LPENR_BKPSRAMLPEN   0x00040000U
#define RCC_AHB1LPENR_CRCLPEN   0x00001000U
#define RCC_AHB1LPENR_DMA1LPEN   0x00200000U
#define RCC_AHB1LPENR_DMA2DLPEN   0x00800000U
#define RCC_AHB1LPENR_DMA2LPEN   0x00400000U
#define RCC_AHB1LPENR_DTCMLPEN   0x00100000U
#define RCC_AHB1LPENR_ETHMACLPEN   0x02000000U
#define RCC_AHB1LPENR_ETHMACPTPLPEN   0x10000000U
#define RCC_AHB1LPENR_ETHMACRXLPEN   0x08000000U
#define RCC_AHB1LPENR_ETHMACTXLPEN   0x04000000U
#define RCC_AHB1LPENR_FLITFLPEN   0x00008000U
#define RCC_AHB1LPENR_GPIOALPEN   0x00000001U
#define RCC_AHB1LPENR_GPIOBLPEN   0x00000002U
#define RCC_AHB1LPENR_GPIOCLPEN   0x00000004U
#define RCC_AHB1LPENR_GPIODLPEN   0x00000008U
#define RCC_AHB1LPENR_GPIOELPEN   0x00000010U
#define RCC_AHB1LPENR_GPIOFLPEN   0x00000020U
#define RCC_AHB1LPENR_GPIOGLPEN   0x00000040U
#define RCC_AHB1LPENR_GPIOHLPEN   0x00000080U
#define RCC_AHB1LPENR_GPIOILPEN   0x00000100U
#define RCC_AHB1LPENR_GPIOJLPEN   0x00000200U
#define RCC_AHB1LPENR_GPIOKLPEN   0x00000400U
#define RCC_AHB1LPENR_OTGHSLPEN   0x20000000U
#define RCC_AHB1LPENR_OTGHSULPILPEN   0x40000000U
#define RCC_AHB1LPENR_SRAM1LPEN   0x00010000U
#define RCC_AHB1LPENR_SRAM2LPEN   0x00020000U
#define RCC_AHB1RSTR_CRCRST   0x00001000U
#define RCC_AHB1RSTR_DMA1RST   0x00200000U
#define RCC_AHB1RSTR_DMA2DRST   0x00800000U
#define RCC_AHB1RSTR_DMA2RST   0x00400000U
#define RCC_AHB1RSTR_ETHMACRST   0x02000000U
#define RCC_AHB1RSTR_GPIOARST   0x00000001U
#define RCC_AHB1RSTR_GPIOBRST   0x00000002U
#define RCC_AHB1RSTR_GPIOCRST   0x00000004U
#define RCC_AHB1RSTR_GPIODRST   0x00000008U
#define RCC_AHB1RSTR_GPIOERST   0x00000010U
#define RCC_AHB1RSTR_GPIOFRST   0x00000020U
#define RCC_AHB1RSTR_GPIOGRST   0x00000040U
#define RCC_AHB1RSTR_GPIOHRST   0x00000080U
#define RCC_AHB1RSTR_GPIOIRST   0x00000100U
#define RCC_AHB1RSTR_GPIOJRST   0x00000200U
#define RCC_AHB1RSTR_GPIOKRST   0x00000400U
#define RCC_AHB1RSTR_OTGHRST   0x20000000U
#define RCC_AHB2ENR_DCMIEN   0x00000001U
#define RCC_AHB2ENR_OTGFSEN   0x00000080U
#define RCC_AHB2ENR_RNGEN   0x00000040U
#define RCC_AHB2LPENR_DCMILPEN   0x00000001U
#define RCC_AHB2LPENR_OTGFSLPEN   0x00000080U
#define RCC_AHB2LPENR_RNGLPEN   0x00000040U
#define RCC_AHB2RSTR_DCMIRST   0x00000001U
#define RCC_AHB2RSTR_OTGFSRST   0x00000080U
#define RCC_AHB2RSTR_RNGRST   0x00000040U
#define RCC_AHB3ENR_FMCEN   0x00000001U
#define RCC_AHB3ENR_QSPIEN   0x00000002U
#define RCC_AHB3LPENR_FMCLPEN   0x00000001U
#define RCC_AHB3LPENR_QSPILPEN   0x00000002U
#define RCC_AHB3RSTR_FMCRST   0x00000001U
#define RCC_AHB3RSTR_QSPIRST   0x00000002U
#define RCC_APB1ENR_CAN1EN   0x02000000U
#define RCC_APB1ENR_CAN2EN   0x04000000U
#define RCC_APB1ENR_CECEN   0x08000000U
#define RCC_APB1ENR_DACEN   0x20000000U
#define RCC_APB1ENR_I2C1EN   0x00200000U
#define RCC_APB1ENR_I2C2EN   0x00400000U
#define RCC_APB1ENR_I2C3EN   0x00800000U
#define RCC_APB1ENR_I2C4EN   0x01000000U
#define RCC_APB1ENR_LPTIM1EN   0x00000200U
#define RCC_APB1ENR_PWREN   0x10000000U
#define RCC_APB1ENR_SPDIFRXEN   0x00010000U
#define RCC_APB1ENR_SPI2EN   0x00004000U
#define RCC_APB1ENR_SPI3EN   0x00008000U
#define RCC_APB1ENR_TIM12EN   0x00000040U
#define RCC_APB1ENR_TIM13EN   0x00000080U
#define RCC_APB1ENR_TIM14EN   0x00000100U
#define RCC_APB1ENR_TIM2EN   0x00000001U
#define RCC_APB1ENR_TIM3EN   0x00000002U
#define RCC_APB1ENR_TIM4EN   0x00000004U
#define RCC_APB1ENR_TIM5EN   0x00000008U
#define RCC_APB1ENR_TIM6EN   0x00000010U
#define RCC_APB1ENR_TIM7EN   0x00000020U
#define RCC_APB1ENR_UART4EN   0x00080000U
#define RCC_APB1ENR_UART5EN   0x00100000U
#define RCC_APB1ENR_UART7EN   0x40000000U
#define RCC_APB1ENR_UART8EN   0x80000000U
#define RCC_APB1ENR_USART2EN   0x00020000U
#define RCC_APB1ENR_USART3EN   0x00040000U
#define RCC_APB1ENR_WWDGEN   0x00000800U
#define RCC_APB1LPENR_CAN1LPEN   0x02000000U
#define RCC_APB1LPENR_CAN2LPEN   0x04000000U
#define RCC_APB1LPENR_CECLPEN   0x08000000U
#define RCC_APB1LPENR_DACLPEN   0x20000000U
#define RCC_APB1LPENR_I2C1LPEN   0x00200000U
#define RCC_APB1LPENR_I2C2LPEN   0x00400000U
#define RCC_APB1LPENR_I2C3LPEN   0x00800000U
#define RCC_APB1LPENR_I2C4LPEN   0x01000000U
#define RCC_APB1LPENR_LPTIM1LPEN   0x00000200U
#define RCC_APB1LPENR_PWRLPEN   0x10000000U
#define RCC_APB1LPENR_SPDIFRXLPEN   0x00010000U
#define RCC_APB1LPENR_SPI2LPEN   0x00004000U
#define RCC_APB1LPENR_SPI3LPEN   0x00008000U
#define RCC_APB1LPENR_TIM12LPEN   0x00000040U
#define RCC_APB1LPENR_TIM13LPEN   0x00000080U
#define RCC_APB1LPENR_TIM14LPEN   0x00000100U
#define RCC_APB1LPENR_TIM2LPEN   0x00000001U
#define RCC_APB1LPENR_TIM3LPEN   0x00000002U
#define RCC_APB1LPENR_TIM4LPEN   0x00000004U
#define RCC_APB1LPENR_TIM5LPEN   0x00000008U
#define RCC_APB1LPENR_TIM6LPEN   0x00000010U
#define RCC_APB1LPENR_TIM7LPEN   0x00000020U
#define RCC_APB1LPENR_UART4LPEN   0x00080000U
#define RCC_APB1LPENR_UART5LPEN   0x00100000U
#define RCC_APB1LPENR_UART7LPEN   0x40000000U
#define RCC_APB1LPENR_UART8LPEN   0x80000000U
#define RCC_APB1LPENR_USART2LPEN   0x00020000U
#define RCC_APB1LPENR_USART3LPEN   0x00040000U
#define RCC_APB1LPENR_WWDGLPEN   0x00000800U
#define RCC_APB1RSTR_CAN1RST   0x02000000U
#define RCC_APB1RSTR_CAN2RST   0x04000000U
#define RCC_APB1RSTR_CECRST   0x08000000U
#define RCC_APB1RSTR_DACRST   0x20000000U
#define RCC_APB1RSTR_I2C1RST   0x00200000U
#define RCC_APB1RSTR_I2C2RST   0x00400000U
#define RCC_APB1RSTR_I2C3RST   0x00800000U
#define RCC_APB1RSTR_I2C4RST   0x01000000U
#define RCC_APB1RSTR_LPTIM1RST   0x00000200U
#define RCC_APB1RSTR_PWRRST   0x10000000U
#define RCC_APB1RSTR_SPDIFRXRST   0x00010000U
#define RCC_APB1RSTR_SPI2RST   0x00004000U
#define RCC_APB1RSTR_SPI3RST   0x00008000U
#define RCC_APB1RSTR_TIM12RST   0x00000040U
#define RCC_APB1RSTR_TIM13RST   0x00000080U
#define RCC_APB1RSTR_TIM14RST   0x00000100U
#define RCC_APB1RSTR_TIM2RST   0x00000001U
#define RCC_APB1RSTR_TIM3RST   0x00000002U
#define RCC_APB1RSTR_TIM4RST   0x00000004U
#define RCC_APB1RSTR_TIM5RST   0x00000008U
#define RCC_APB1RSTR_TIM6RST   0x00000010U
#define RCC_APB1RSTR_TIM7RST   0x00000020U
#define RCC_APB1RSTR_UART4RST   0x00080000U
#define RCC_APB1RSTR_UART5RST   0x00100000U
#define RCC_APB1RSTR_UART7RST   0x40000000U
#define RCC_APB1RSTR_UART8RST   0x80000000U
#define RCC_APB1RSTR_USART2RST   0x00020000U
#define RCC_APB1RSTR_USART3RST   0x00040000U
#define RCC_APB1RSTR_WWDGRST   0x00000800U
#define RCC_APB2ENR_ADC1EN   0x00000100U
#define RCC_APB2ENR_ADC2EN   0x00000200U
#define RCC_APB2ENR_ADC3EN   0x00000400U
#define RCC_APB2ENR_LTDCEN   0x04000000U
#define RCC_APB2ENR_SAI1EN   0x00400000U
#define RCC_APB2ENR_SAI2EN   0x00800000U
#define RCC_APB2ENR_SDMMC1EN   0x00000800U
#define RCC_APB2ENR_SPI1EN   0x00001000U
#define RCC_APB2ENR_SPI4EN   0x00002000U
#define RCC_APB2ENR_SPI5EN   0x00100000U
#define RCC_APB2ENR_SPI6EN   0x00200000U
#define RCC_APB2ENR_SYSCFGEN   0x00004000U
#define RCC_APB2ENR_TIM10EN   0x00020000U
#define RCC_APB2ENR_TIM11EN   0x00040000U
#define RCC_APB2ENR_TIM1EN   0x00000001U
#define RCC_APB2ENR_TIM8EN   0x00000002U
#define RCC_APB2ENR_TIM9EN   0x00010000U
#define RCC_APB2ENR_USART1EN   0x00000010U
#define RCC_APB2ENR_USART6EN   0x00000020U
#define RCC_APB2LPENR_ADC1LPEN   0x00000100U
#define RCC_APB2LPENR_ADC2LPEN   0x00000200U
#define RCC_APB2LPENR_ADC3LPEN   0x00000400U
#define RCC_APB2LPENR_LTDCLPEN   0x04000000U
#define RCC_APB2LPENR_SAI1LPEN   0x00400000U
#define RCC_APB2LPENR_SAI2LPEN   0x00800000U
#define RCC_APB2LPENR_SDMMC1LPEN   0x00000800U
#define RCC_APB2LPENR_SPI1LPEN   0x00001000U
#define RCC_APB2LPENR_SPI4LPEN   0x00002000U
#define RCC_APB2LPENR_SPI5LPEN   0x00100000U
#define RCC_APB2LPENR_SPI6LPEN   0x00200000U
#define RCC_APB2LPENR_SYSCFGLPEN   0x00004000U
#define RCC_APB2LPENR_TIM10LPEN   0x00020000U
#define RCC_APB2LPENR_TIM11LPEN   0x00040000U
#define RCC_APB2LPENR_TIM1LPEN   0x00000001U
#define RCC_APB2LPENR_TIM8LPEN   0x00000002U
#define RCC_APB2LPENR_TIM9LPEN   0x00010000U
#define RCC_APB2LPENR_USART1LPEN   0x00000010U
#define RCC_APB2LPENR_USART6LPEN   0x00000020U
#define RCC_APB2RSTR_ADCRST   0x00000100U
#define RCC_APB2RSTR_LTDCRST   0x04000000U
#define RCC_APB2RSTR_SAI1RST   0x00400000U
#define RCC_APB2RSTR_SAI2RST   0x00800000U
#define RCC_APB2RSTR_SDMMC1RST   0x00000800U
#define RCC_APB2RSTR_SPI1RST   0x00001000U
#define RCC_APB2RSTR_SPI4RST   0x00002000U
#define RCC_APB2RSTR_SPI5RST   0x00100000U
#define RCC_APB2RSTR_SPI6RST   0x00200000U
#define RCC_APB2RSTR_SYSCFGRST   0x00004000U
#define RCC_APB2RSTR_TIM10RST   0x00020000U
#define RCC_APB2RSTR_TIM11RST   0x00040000U
#define RCC_APB2RSTR_TIM1RST   0x00000001U
#define RCC_APB2RSTR_TIM8RST   0x00000002U
#define RCC_APB2RSTR_TIM9RST   0x00010000U
#define RCC_APB2RSTR_USART1RST   0x00000010U
#define RCC_APB2RSTR_USART6RST   0x00000020U
#define RCC_BDCR_BDRST   0x00010000U
#define RCC_BDCR_LSEBYP   0x00000004U
#define RCC_BDCR_LSEDRV   0x00000018U
#define RCC_BDCR_LSEDRV_0   0x00000008U
#define RCC_BDCR_LSEDRV_1   0x00000010U
#define RCC_BDCR_LSEON   0x00000001U
#define RCC_BDCR_LSERDY   0x00000002U
#define RCC_BDCR_RTCEN   0x00008000U
#define RCC_BDCR_RTCSEL   0x00000300U
#define RCC_BDCR_RTCSEL_0   0x00000100U
#define RCC_BDCR_RTCSEL_1   0x00000200U
#define RCC_CFGR_HPRE   0x000000F0U

HPRE[3:0] bits (AHB prescaler)

#define RCC_CFGR_HPRE_0   0x00000010U

Bit 0

#define RCC_CFGR_HPRE_1   0x00000020U

Bit 1

#define RCC_CFGR_HPRE_2   0x00000040U

Bit 2

#define RCC_CFGR_HPRE_3   0x00000080U

Bit 3

#define RCC_CFGR_HPRE_DIV1   0x00000000U

SYSCLK not divided

#define RCC_CFGR_HPRE_DIV128   0x000000D0U

SYSCLK divided by 128

#define RCC_CFGR_HPRE_DIV16   0x000000B0U

SYSCLK divided by 16

#define RCC_CFGR_HPRE_DIV2   0x00000080U

SYSCLK divided by 2

#define RCC_CFGR_HPRE_DIV256   0x000000E0U

SYSCLK divided by 256

#define RCC_CFGR_HPRE_DIV4   0x00000090U

SYSCLK divided by 4

#define RCC_CFGR_HPRE_DIV512   0x000000F0U

SYSCLK divided by 512 PPRE1 configuration

#define RCC_CFGR_HPRE_DIV64   0x000000C0U

SYSCLK divided by 64

#define RCC_CFGR_HPRE_DIV8   0x000000A0U

SYSCLK divided by 8

#define RCC_CFGR_I2SSRC   0x00800000U
#define RCC_CFGR_MCO1   0x00600000U
#define RCC_CFGR_MCO1_0   0x00200000U
#define RCC_CFGR_MCO1_1   0x00400000U
#define RCC_CFGR_MCO1PRE   0x07000000U
#define RCC_CFGR_MCO1PRE_0   0x01000000U
#define RCC_CFGR_MCO1PRE_1   0x02000000U
#define RCC_CFGR_MCO1PRE_2   0x04000000U
#define RCC_CFGR_MCO2   0xC0000000U
#define RCC_CFGR_MCO2_0   0x40000000U
#define RCC_CFGR_MCO2_1   0x80000000U
#define RCC_CFGR_MCO2PRE   0x38000000U
#define RCC_CFGR_MCO2PRE_0   0x08000000U
#define RCC_CFGR_MCO2PRE_1   0x10000000U
#define RCC_CFGR_MCO2PRE_2   0x20000000U
#define RCC_CFGR_PPRE1   0x00001C00U

PRE1[2:0] bits (APB1 prescaler)

#define RCC_CFGR_PPRE1_0   0x00000400U

Bit 0

#define RCC_CFGR_PPRE1_1   0x00000800U

Bit 1

#define RCC_CFGR_PPRE1_2   0x00001000U

Bit 2

#define RCC_CFGR_PPRE1_DIV1   0x00000000U

HCLK not divided

#define RCC_CFGR_PPRE1_DIV16   0x00001C00U

HCLK divided by 16 PPRE2 configuration

#define RCC_CFGR_PPRE1_DIV2   0x00001000U

HCLK divided by 2

#define RCC_CFGR_PPRE1_DIV4   0x00001400U

HCLK divided by 4

#define RCC_CFGR_PPRE1_DIV8   0x00001800U

HCLK divided by 8

#define RCC_CFGR_PPRE2   0x0000E000U

PRE2[2:0] bits (APB2 prescaler)

#define RCC_CFGR_PPRE2_0   0x00002000U

Bit 0

#define RCC_CFGR_PPRE2_1   0x00004000U

Bit 1

#define RCC_CFGR_PPRE2_2   0x00008000U

Bit 2

#define RCC_CFGR_PPRE2_DIV1   0x00000000U

HCLK not divided

#define RCC_CFGR_PPRE2_DIV16   0x0000E000U

HCLK divided by 16 RTCPRE configuration

#define RCC_CFGR_PPRE2_DIV2   0x00008000U

HCLK divided by 2

#define RCC_CFGR_PPRE2_DIV4   0x0000A000U

HCLK divided by 4

#define RCC_CFGR_PPRE2_DIV8   0x0000C000U

HCLK divided by 8

#define RCC_CFGR_RTCPRE   0x001F0000U
#define RCC_CFGR_RTCPRE_0   0x00010000U
#define RCC_CFGR_RTCPRE_1   0x00020000U
#define RCC_CFGR_RTCPRE_2   0x00040000U
#define RCC_CFGR_RTCPRE_3   0x00080000U
#define RCC_CFGR_RTCPRE_4   0x00100000U

MCO1 configuration

#define RCC_CFGR_SW   0x00000003U

< SW configuration SW[1:0] bits (System clock Switch)

#define RCC_CFGR_SW_0   0x00000001U

Bit 0

#define RCC_CFGR_SW_1   0x00000002U

Bit 1

#define RCC_CFGR_SW_HSE   0x00000001U

HSE selected as system clock

#define RCC_CFGR_SW_HSI   0x00000000U

HSI selected as system clock

#define RCC_CFGR_SW_PLL   0x00000002U

PLL selected as system clock SWS configuration

#define RCC_CFGR_SWS   0x0000000CU

SWS[1:0] bits (System Clock Switch Status)

#define RCC_CFGR_SWS_0   0x00000004U

Bit 0

#define RCC_CFGR_SWS_1   0x00000008U

Bit 1

#define RCC_CFGR_SWS_HSE   0x00000004U

HSE oscillator used as system clock

#define RCC_CFGR_SWS_HSI   0x00000000U

HSI oscillator used as system clock

#define RCC_CFGR_SWS_PLL   0x00000008U

PLL used as system clock HPRE configuration

#define RCC_CIR_CSSC   0x00800000U
#define RCC_CIR_CSSF   0x00000080U
#define RCC_CIR_HSERDYC   0x00080000U
#define RCC_CIR_HSERDYF   0x00000008U
#define RCC_CIR_HSERDYIE   0x00000800U
#define RCC_CIR_HSIRDYC   0x00040000U
#define RCC_CIR_HSIRDYF   0x00000004U
#define RCC_CIR_HSIRDYIE   0x00000400U
#define RCC_CIR_LSERDYC   0x00020000U
#define RCC_CIR_LSERDYF   0x00000002U
#define RCC_CIR_LSERDYIE   0x00000200U
#define RCC_CIR_LSIRDYC   0x00010000U
#define RCC_CIR_LSIRDYF   0x00000001U
#define RCC_CIR_LSIRDYIE   0x00000100U
#define RCC_CIR_PLLI2SRDYC   0x00200000U
#define RCC_CIR_PLLI2SRDYF   0x00000020U
#define RCC_CIR_PLLI2SRDYIE   0x00002000U
#define RCC_CIR_PLLRDYC   0x00100000U
#define RCC_CIR_PLLRDYF   0x00000010U
#define RCC_CIR_PLLRDYIE   0x00001000U
#define RCC_CIR_PLLSAIRDYC   0x00400000U
#define RCC_CIR_PLLSAIRDYF   0x00000040U
#define RCC_CIR_PLLSAIRDYIE   0x00004000U
#define RCC_CR_CSSON   0x00080000U
#define RCC_CR_HSEBYP   0x00040000U
#define RCC_CR_HSEON   0x00010000U
#define RCC_CR_HSERDY   0x00020000U
#define RCC_CR_HSICAL   0x0000FF00U
#define RCC_CR_HSICAL_0   0x00000100U

Bit 0

#define RCC_CR_HSICAL_1   0x00000200U

Bit 1

#define RCC_CR_HSICAL_2   0x00000400U

Bit 2

#define RCC_CR_HSICAL_3   0x00000800U

Bit 3

#define RCC_CR_HSICAL_4   0x00001000U

Bit 4

#define RCC_CR_HSICAL_5   0x00002000U

Bit 5

#define RCC_CR_HSICAL_6   0x00004000U

Bit 6

#define RCC_CR_HSICAL_7   0x00008000U

Bit 7

#define RCC_CR_HSION   0x00000001U
#define RCC_CR_HSIRDY   0x00000002U
#define RCC_CR_HSITRIM   0x000000F8U
#define RCC_CR_HSITRIM_0   0x00000008U

Bit 0

#define RCC_CR_HSITRIM_1   0x00000010U

Bit 1

#define RCC_CR_HSITRIM_2   0x00000020U

Bit 2

#define RCC_CR_HSITRIM_3   0x00000040U

Bit 3

#define RCC_CR_HSITRIM_4   0x00000080U

Bit 4

#define RCC_CR_PLLI2SON   0x04000000U
#define RCC_CR_PLLI2SRDY   0x08000000U
#define RCC_CR_PLLON   0x01000000U
#define RCC_CR_PLLRDY   0x02000000U
#define RCC_CR_PLLSAION   0x10000000U
#define RCC_CR_PLLSAIRDY   0x20000000U
#define RCC_CSR_BORRSTF   0x02000000U
#define RCC_CSR_IWDGRSTF   0x20000000U
#define RCC_CSR_LPWRRSTF   0x80000000U
#define RCC_CSR_LSION   0x00000001U
#define RCC_CSR_LSIRDY   0x00000002U
#define RCC_CSR_PINRSTF   0x04000000U
#define RCC_CSR_PORRSTF   0x08000000U
#define RCC_CSR_RMVF   0x01000000U
#define RCC_CSR_SFTRSTF   0x10000000U
#define RCC_CSR_WWDGRSTF   0x40000000U
#define RCC_DCKCFGR1_PLLI2SDIVQ   0x0000001FU
#define RCC_DCKCFGR1_PLLI2SDIVQ_0   0x00000001U
#define RCC_DCKCFGR1_PLLI2SDIVQ_1   0x00000002U
#define RCC_DCKCFGR1_PLLI2SDIVQ_2   0x00000004U
#define RCC_DCKCFGR1_PLLI2SDIVQ_3   0x00000008U
#define RCC_DCKCFGR1_PLLI2SDIVQ_4   0x00000010U
#define RCC_DCKCFGR1_PLLSAIDIVQ   0x00001F00U
#define RCC_DCKCFGR1_PLLSAIDIVQ_0   0x00000100U
#define RCC_DCKCFGR1_PLLSAIDIVQ_1   0x00000200U
#define RCC_DCKCFGR1_PLLSAIDIVQ_2   0x00000400U
#define RCC_DCKCFGR1_PLLSAIDIVQ_3   0x00000800U
#define RCC_DCKCFGR1_PLLSAIDIVQ_4   0x00001000U
#define RCC_DCKCFGR1_PLLSAIDIVR   0x00030000U
#define RCC_DCKCFGR1_PLLSAIDIVR_0   0x00010000U
#define RCC_DCKCFGR1_PLLSAIDIVR_1   0x00020000U
#define RCC_DCKCFGR1_SAI1SEL   0x00300000U
#define RCC_DCKCFGR1_SAI1SEL_0   0x00100000U
#define RCC_DCKCFGR1_SAI1SEL_1   0x00200000U
#define RCC_DCKCFGR1_SAI2SEL   0x00C00000U
#define RCC_DCKCFGR1_SAI2SEL_0   0x00400000U
#define RCC_DCKCFGR1_SAI2SEL_1   0x00800000U
#define RCC_DCKCFGR1_TIMPRE   0x01000000U
#define RCC_DCKCFGR2_CECSEL   0x04000000U
#define RCC_DCKCFGR2_CK48MSEL   0x08000000U
#define RCC_DCKCFGR2_I2C1SEL   0x00030000U
#define RCC_DCKCFGR2_I2C1SEL_0   0x00010000U
#define RCC_DCKCFGR2_I2C1SEL_1   0x00020000U
#define RCC_DCKCFGR2_I2C2SEL   0x000C0000U
#define RCC_DCKCFGR2_I2C2SEL_0   0x00040000U
#define RCC_DCKCFGR2_I2C2SEL_1   0x00080000U
#define RCC_DCKCFGR2_I2C3SEL   0x00300000U
#define RCC_DCKCFGR2_I2C3SEL_0   0x00100000U
#define RCC_DCKCFGR2_I2C3SEL_1   0x00200000U
#define RCC_DCKCFGR2_I2C4SEL   0x00C00000U
#define RCC_DCKCFGR2_I2C4SEL_0   0x00400000U
#define RCC_DCKCFGR2_I2C4SEL_1   0x00800000U
#define RCC_DCKCFGR2_LPTIM1SEL   0x03000000U
#define RCC_DCKCFGR2_LPTIM1SEL_0   0x01000000U
#define RCC_DCKCFGR2_LPTIM1SEL_1   0x02000000U
#define RCC_DCKCFGR2_SDMMC1SEL   0x10000000U
#define RCC_DCKCFGR2_UART4SEL   0x000000C0U
#define RCC_DCKCFGR2_UART4SEL_0   0x00000040U
#define RCC_DCKCFGR2_UART4SEL_1   0x00000080U
#define RCC_DCKCFGR2_UART5SEL   0x00000300U
#define RCC_DCKCFGR2_UART5SEL_0   0x00000100U
#define RCC_DCKCFGR2_UART5SEL_1   0x00000200U
#define RCC_DCKCFGR2_UART7SEL   0x00003000U
#define RCC_DCKCFGR2_UART7SEL_0   0x00001000U
#define RCC_DCKCFGR2_UART7SEL_1   0x00002000U
#define RCC_DCKCFGR2_UART8SEL   0x0000C000U
#define RCC_DCKCFGR2_UART8SEL_0   0x00004000U
#define RCC_DCKCFGR2_UART8SEL_1   0x00008000U
#define RCC_DCKCFGR2_USART1SEL   0x00000003U
#define RCC_DCKCFGR2_USART1SEL_0   0x00000001U
#define RCC_DCKCFGR2_USART1SEL_1   0x00000002U
#define RCC_DCKCFGR2_USART2SEL   0x0000000CU
#define RCC_DCKCFGR2_USART2SEL_0   0x00000004U
#define RCC_DCKCFGR2_USART2SEL_1   0x00000008U
#define RCC_DCKCFGR2_USART3SEL   0x00000030U
#define RCC_DCKCFGR2_USART3SEL_0   0x00000010U
#define RCC_DCKCFGR2_USART3SEL_1   0x00000020U
#define RCC_DCKCFGR2_USART6SEL   0x00000C00U
#define RCC_DCKCFGR2_USART6SEL_0   0x00000400U
#define RCC_DCKCFGR2_USART6SEL_1   0x00000800U
#define RCC_PLLCFGR_PLLM   0x0000003FU
#define RCC_PLLCFGR_PLLM_0   0x00000001U
#define RCC_PLLCFGR_PLLM_1   0x00000002U
#define RCC_PLLCFGR_PLLM_2   0x00000004U
#define RCC_PLLCFGR_PLLM_3   0x00000008U
#define RCC_PLLCFGR_PLLM_4   0x00000010U
#define RCC_PLLCFGR_PLLM_5   0x00000020U
#define RCC_PLLCFGR_PLLN   0x00007FC0U
#define RCC_PLLCFGR_PLLN_0   0x00000040U
#define RCC_PLLCFGR_PLLN_1   0x00000080U
#define RCC_PLLCFGR_PLLN_2   0x00000100U
#define RCC_PLLCFGR_PLLN_3   0x00000200U
#define RCC_PLLCFGR_PLLN_4   0x00000400U
#define RCC_PLLCFGR_PLLN_5   0x00000800U
#define RCC_PLLCFGR_PLLN_6   0x00001000U
#define RCC_PLLCFGR_PLLN_7   0x00002000U
#define RCC_PLLCFGR_PLLN_8   0x00004000U
#define RCC_PLLCFGR_PLLP   0x00030000U
#define RCC_PLLCFGR_PLLP_0   0x00010000U
#define RCC_PLLCFGR_PLLP_1   0x00020000U
#define RCC_PLLCFGR_PLLQ   0x0F000000U
#define RCC_PLLCFGR_PLLQ_0   0x01000000U
#define RCC_PLLCFGR_PLLQ_1   0x02000000U
#define RCC_PLLCFGR_PLLQ_2   0x04000000U
#define RCC_PLLCFGR_PLLQ_3   0x08000000U
#define RCC_PLLCFGR_PLLSRC   0x00400000U
#define RCC_PLLCFGR_PLLSRC_HSE   0x00400000U
#define RCC_PLLCFGR_PLLSRC_HSI   0x00000000U
#define RCC_PLLI2SCFGR_PLLI2SN   0x00007FC0U
#define RCC_PLLI2SCFGR_PLLI2SN_0   0x00000040U
#define RCC_PLLI2SCFGR_PLLI2SN_1   0x00000080U
#define RCC_PLLI2SCFGR_PLLI2SN_2   0x00000100U
#define RCC_PLLI2SCFGR_PLLI2SN_3   0x00000200U
#define RCC_PLLI2SCFGR_PLLI2SN_4   0x00000400U
#define RCC_PLLI2SCFGR_PLLI2SN_5   0x00000800U
#define RCC_PLLI2SCFGR_PLLI2SN_6   0x00001000U
#define RCC_PLLI2SCFGR_PLLI2SN_7   0x00002000U
#define RCC_PLLI2SCFGR_PLLI2SN_8   0x00004000U
#define RCC_PLLI2SCFGR_PLLI2SP   0x00030000U
#define RCC_PLLI2SCFGR_PLLI2SP_0   0x00010000U
#define RCC_PLLI2SCFGR_PLLI2SP_1   0x00020000U
#define RCC_PLLI2SCFGR_PLLI2SQ   0x0F000000U
#define RCC_PLLI2SCFGR_PLLI2SQ_0   0x01000000U
#define RCC_PLLI2SCFGR_PLLI2SQ_1   0x02000000U
#define RCC_PLLI2SCFGR_PLLI2SQ_2   0x04000000U
#define RCC_PLLI2SCFGR_PLLI2SQ_3   0x08000000U
#define RCC_PLLI2SCFGR_PLLI2SR   0x70000000U
#define RCC_PLLI2SCFGR_PLLI2SR_0   0x10000000U
#define RCC_PLLI2SCFGR_PLLI2SR_1   0x20000000U
#define RCC_PLLI2SCFGR_PLLI2SR_2   0x40000000U
#define RCC_PLLSAICFGR_PLLSAIN   0x00007FC0U
#define RCC_PLLSAICFGR_PLLSAIN_0   0x00000040U
#define RCC_PLLSAICFGR_PLLSAIN_1   0x00000080U
#define RCC_PLLSAICFGR_PLLSAIN_2   0x00000100U
#define RCC_PLLSAICFGR_PLLSAIN_3   0x00000200U
#define RCC_PLLSAICFGR_PLLSAIN_4   0x00000400U
#define RCC_PLLSAICFGR_PLLSAIN_5   0x00000800U
#define RCC_PLLSAICFGR_PLLSAIN_6   0x00001000U
#define RCC_PLLSAICFGR_PLLSAIN_7   0x00002000U
#define RCC_PLLSAICFGR_PLLSAIN_8   0x00004000U
#define RCC_PLLSAICFGR_PLLSAIP   0x00030000U
#define RCC_PLLSAICFGR_PLLSAIP_0   0x00010000U
#define RCC_PLLSAICFGR_PLLSAIP_1   0x00020000U
#define RCC_PLLSAICFGR_PLLSAIQ   0x0F000000U
#define RCC_PLLSAICFGR_PLLSAIQ_0   0x01000000U
#define RCC_PLLSAICFGR_PLLSAIQ_1   0x02000000U
#define RCC_PLLSAICFGR_PLLSAIQ_2   0x04000000U
#define RCC_PLLSAICFGR_PLLSAIQ_3   0x08000000U
#define RCC_PLLSAICFGR_PLLSAIR   0x70000000U
#define RCC_PLLSAICFGR_PLLSAIR_0   0x10000000U
#define RCC_PLLSAICFGR_PLLSAIR_1   0x20000000U
#define RCC_PLLSAICFGR_PLLSAIR_2   0x40000000U
#define RCC_SSCGR_INCSTEP   0x0FFFE000U
#define RCC_SSCGR_MODPER   0x00001FFFU
#define RCC_SSCGR_SPREADSEL   0x40000000U
#define RCC_SSCGR_SSCGEN   0x80000000U
#define RNG_CR_IE   0x00000008U
#define RNG_CR_RNGEN   0x00000004U
#define RNG_SR_CECS   0x00000002U
#define RNG_SR_CEIS   0x00000020U
#define RNG_SR_DRDY   0x00000001U
#define RNG_SR_SECS   0x00000004U
#define RNG_SR_SEIS   0x00000040U
#define RTC_ALRMAR_DT   0x30000000U
#define RTC_ALRMAR_DT_0   0x10000000U
#define RTC_ALRMAR_DT_1   0x20000000U
#define RTC_ALRMAR_DU   0x0F000000U
#define RTC_ALRMAR_DU_0   0x01000000U
#define RTC_ALRMAR_DU_1   0x02000000U
#define RTC_ALRMAR_DU_2   0x04000000U
#define RTC_ALRMAR_DU_3   0x08000000U
#define RTC_ALRMAR_HT   0x00300000U
#define RTC_ALRMAR_HT_0   0x00100000U
#define RTC_ALRMAR_HT_1   0x00200000U
#define RTC_ALRMAR_HU   0x000F0000U
#define RTC_ALRMAR_HU_0   0x00010000U
#define RTC_ALRMAR_HU_1   0x00020000U
#define RTC_ALRMAR_HU_2   0x00040000U
#define RTC_ALRMAR_HU_3   0x00080000U
#define RTC_ALRMAR_MNT   0x00007000U
#define RTC_ALRMAR_MNT_0   0x00001000U
#define RTC_ALRMAR_MNT_1   0x00002000U
#define RTC_ALRMAR_MNT_2   0x00004000U
#define RTC_ALRMAR_MNU   0x00000F00U
#define RTC_ALRMAR_MNU_0   0x00000100U
#define RTC_ALRMAR_MNU_1   0x00000200U
#define RTC_ALRMAR_MNU_2   0x00000400U
#define RTC_ALRMAR_MNU_3   0x00000800U
#define RTC_ALRMAR_MSK1   0x00000080U
#define RTC_ALRMAR_MSK2   0x00008000U
#define RTC_ALRMAR_MSK3   0x00800000U
#define RTC_ALRMAR_MSK4   0x80000000U
#define RTC_ALRMAR_PM   0x00400000U
#define RTC_ALRMAR_ST   0x00000070U
#define RTC_ALRMAR_ST_0   0x00000010U
#define RTC_ALRMAR_ST_1   0x00000020U
#define RTC_ALRMAR_ST_2   0x00000040U
#define RTC_ALRMAR_SU   0x0000000FU
#define RTC_ALRMAR_SU_0   0x00000001U
#define RTC_ALRMAR_SU_1   0x00000002U
#define RTC_ALRMAR_SU_2   0x00000004U
#define RTC_ALRMAR_SU_3   0x00000008U
#define RTC_ALRMAR_WDSEL   0x40000000U
#define RTC_ALRMASSR_MASKSS   0x0F000000U
#define RTC_ALRMASSR_MASKSS_0   0x01000000U
#define RTC_ALRMASSR_MASKSS_1   0x02000000U
#define RTC_ALRMASSR_MASKSS_2   0x04000000U
#define RTC_ALRMASSR_MASKSS_3   0x08000000U
#define RTC_ALRMASSR_SS   0x00007FFFU
#define RTC_ALRMBR_DT   0x30000000U
#define RTC_ALRMBR_DT_0   0x10000000U
#define RTC_ALRMBR_DT_1   0x20000000U
#define RTC_ALRMBR_DU   0x0F000000U
#define RTC_ALRMBR_DU_0   0x01000000U
#define RTC_ALRMBR_DU_1   0x02000000U
#define RTC_ALRMBR_DU_2   0x04000000U
#define RTC_ALRMBR_DU_3   0x08000000U
#define RTC_ALRMBR_HT   0x00300000U
#define RTC_ALRMBR_HT_0   0x00100000U
#define RTC_ALRMBR_HT_1   0x00200000U
#define RTC_ALRMBR_HU   0x000F0000U
#define RTC_ALRMBR_HU_0   0x00010000U
#define RTC_ALRMBR_HU_1   0x00020000U
#define RTC_ALRMBR_HU_2   0x00040000U
#define RTC_ALRMBR_HU_3   0x00080000U
#define RTC_ALRMBR_MNT   0x00007000U
#define RTC_ALRMBR_MNT_0   0x00001000U
#define RTC_ALRMBR_MNT_1   0x00002000U
#define RTC_ALRMBR_MNT_2   0x00004000U
#define RTC_ALRMBR_MNU   0x00000F00U
#define RTC_ALRMBR_MNU_0   0x00000100U
#define RTC_ALRMBR_MNU_1   0x00000200U
#define RTC_ALRMBR_MNU_2   0x00000400U
#define RTC_ALRMBR_MNU_3   0x00000800U
#define RTC_ALRMBR_MSK1   0x00000080U
#define RTC_ALRMBR_MSK2   0x00008000U
#define RTC_ALRMBR_MSK3   0x00800000U
#define RTC_ALRMBR_MSK4   0x80000000U
#define RTC_ALRMBR_PM   0x00400000U
#define RTC_ALRMBR_ST   0x00000070U
#define RTC_ALRMBR_ST_0   0x00000010U
#define RTC_ALRMBR_ST_1   0x00000020U
#define RTC_ALRMBR_ST_2   0x00000040U
#define RTC_ALRMBR_SU   0x0000000FU
#define RTC_ALRMBR_SU_0   0x00000001U
#define RTC_ALRMBR_SU_1   0x00000002U
#define RTC_ALRMBR_SU_2   0x00000004U
#define RTC_ALRMBR_SU_3   0x00000008U
#define RTC_ALRMBR_WDSEL   0x40000000U
#define RTC_ALRMBSSR_MASKSS   0x0F000000U
#define RTC_ALRMBSSR_MASKSS_0   0x01000000U
#define RTC_ALRMBSSR_MASKSS_1   0x02000000U
#define RTC_ALRMBSSR_MASKSS_2   0x04000000U
#define RTC_ALRMBSSR_MASKSS_3   0x08000000U
#define RTC_ALRMBSSR_SS   0x00007FFFU
#define RTC_BKP0R   0xFFFFFFFFU
#define RTC_BKP10R   0xFFFFFFFFU
#define RTC_BKP11R   0xFFFFFFFFU
#define RTC_BKP12R   0xFFFFFFFFU
#define RTC_BKP13R   0xFFFFFFFFU
#define RTC_BKP14R   0xFFFFFFFFU
#define RTC_BKP15R   0xFFFFFFFFU
#define RTC_BKP16R   0xFFFFFFFFU
#define RTC_BKP17R   0xFFFFFFFFU
#define RTC_BKP18R   0xFFFFFFFFU
#define RTC_BKP19R   0xFFFFFFFFU
#define RTC_BKP1R   0xFFFFFFFFU
#define RTC_BKP20R   0xFFFFFFFFU
#define RTC_BKP21R   0xFFFFFFFFU
#define RTC_BKP22R   0xFFFFFFFFU
#define RTC_BKP23R   0xFFFFFFFFU
#define RTC_BKP24R   0xFFFFFFFFU
#define RTC_BKP25R   0xFFFFFFFFU
#define RTC_BKP26R   0xFFFFFFFFU
#define RTC_BKP27R   0xFFFFFFFFU
#define RTC_BKP28R   0xFFFFFFFFU
#define RTC_BKP29R   0xFFFFFFFFU
#define RTC_BKP2R   0xFFFFFFFFU
#define RTC_BKP30R   0xFFFFFFFFU
#define RTC_BKP31R   0xFFFFFFFFU
#define RTC_BKP3R   0xFFFFFFFFU
#define RTC_BKP4R   0xFFFFFFFFU
#define RTC_BKP5R   0xFFFFFFFFU
#define RTC_BKP6R   0xFFFFFFFFU
#define RTC_BKP7R   0xFFFFFFFFU
#define RTC_BKP8R   0xFFFFFFFFU
#define RTC_BKP9R   0xFFFFFFFFU
#define RTC_BKP_NUMBER   0x00000020U
#define RTC_CALR_CALM   0x000001FFU
#define RTC_CALR_CALM_0   0x00000001U
#define RTC_CALR_CALM_1   0x00000002U
#define RTC_CALR_CALM_2   0x00000004U
#define RTC_CALR_CALM_3   0x00000008U
#define RTC_CALR_CALM_4   0x00000010U
#define RTC_CALR_CALM_5   0x00000020U
#define RTC_CALR_CALM_6   0x00000040U
#define RTC_CALR_CALM_7   0x00000080U
#define RTC_CALR_CALM_8   0x00000100U
#define RTC_CALR_CALP   0x00008000U
#define RTC_CALR_CALW16   0x00002000U
#define RTC_CALR_CALW8   0x00004000U
#define RTC_CR_ADD1H   0x00010000U
#define RTC_CR_ALRAE   0x00000100U
#define RTC_CR_ALRAIE   0x00001000U
#define RTC_CR_ALRBE   0x00000200U
#define RTC_CR_ALRBIE   0x00002000U
#define RTC_CR_BCK   RTC_CR_BKP
#define RTC_CR_BKP   0x00040000U
#define RTC_CR_BYPSHAD   0x00000020U
#define RTC_CR_COE   0x00800000U
#define RTC_CR_COSEL   0x00080000U
#define RTC_CR_FMT   0x00000040U
#define RTC_CR_ITSE   0x01000000U
#define RTC_CR_OSEL   0x00600000U
#define RTC_CR_OSEL_0   0x00200000U
#define RTC_CR_OSEL_1   0x00400000U
#define RTC_CR_POL   0x00100000U
#define RTC_CR_REFCKON   0x00000010U
#define RTC_CR_SUB1H   0x00020000U
#define RTC_CR_TSE   0x00000800U
#define RTC_CR_TSEDGE   0x00000008U
#define RTC_CR_TSIE   0x00008000U
#define RTC_CR_WUCKSEL   0x00000007U
#define RTC_CR_WUCKSEL_0   0x00000001U
#define RTC_CR_WUCKSEL_1   0x00000002U
#define RTC_CR_WUCKSEL_2   0x00000004U
#define RTC_CR_WUTE   0x00000400U
#define RTC_CR_WUTIE   0x00004000U
#define RTC_DR_DT   0x00000030U
#define RTC_DR_DT_0   0x00000010U
#define RTC_DR_DT_1   0x00000020U
#define RTC_DR_DU   0x0000000FU
#define RTC_DR_DU_0   0x00000001U
#define RTC_DR_DU_1   0x00000002U
#define RTC_DR_DU_2   0x00000004U
#define RTC_DR_DU_3   0x00000008U
#define RTC_DR_MT   0x00001000U
#define RTC_DR_MU   0x00000F00U
#define RTC_DR_MU_0   0x00000100U
#define RTC_DR_MU_1   0x00000200U
#define RTC_DR_MU_2   0x00000400U
#define RTC_DR_MU_3   0x00000800U
#define RTC_DR_WDU   0x0000E000U
#define RTC_DR_WDU_0   0x00002000U
#define RTC_DR_WDU_1   0x00004000U
#define RTC_DR_WDU_2   0x00008000U
#define RTC_DR_YT   0x00F00000U
#define RTC_DR_YT_0   0x00100000U
#define RTC_DR_YT_1   0x00200000U
#define RTC_DR_YT_2   0x00400000U
#define RTC_DR_YT_3   0x00800000U
#define RTC_DR_YU   0x000F0000U
#define RTC_DR_YU_0   0x00010000U
#define RTC_DR_YU_1   0x00020000U
#define RTC_DR_YU_2   0x00040000U
#define RTC_DR_YU_3   0x00080000U
#define RTC_ISR_ALRAF   0x00000100U
#define RTC_ISR_ALRAWF   0x00000001U
#define RTC_ISR_ALRBF   0x00000200U
#define RTC_ISR_ALRBWF   0x00000002U
#define RTC_ISR_INIT   0x00000080U
#define RTC_ISR_INITF   0x00000040U
#define RTC_ISR_INITS   0x00000010U
#define RTC_ISR_ITSF   0x00020000U
#define RTC_ISR_RECALPF   0x00010000U
#define RTC_ISR_RSF   0x00000020U
#define RTC_ISR_SHPF   0x00000008U
#define RTC_ISR_TAMP1F   0x00002000U
#define RTC_ISR_TAMP2F   0x00004000U
#define RTC_ISR_TAMP3F   0x00008000U
#define RTC_ISR_TSF   0x00000800U
#define RTC_ISR_TSOVF   0x00001000U
#define RTC_ISR_WUTF   0x00000400U
#define RTC_ISR_WUTWF   0x00000004U
#define RTC_OR_ALARMTYPE   0x00000008U
#define RTC_OR_TSINSEL   0x00000006U
#define RTC_OR_TSINSEL_0   0x00000002U
#define RTC_OR_TSINSEL_1   0x00000004U
#define RTC_PRER_PREDIV_A   0x007F0000U
#define RTC_PRER_PREDIV_S   0x00007FFFU
#define RTC_SHIFTR_ADD1S   0x80000000U
#define RTC_SHIFTR_SUBFS   0x00007FFFU
#define RTC_SSR_SS   0x0000FFFFU
#define RTC_TAMPCR_TAMP1_TRG   RTC_TAMPCR_TAMP1TRG
#define RTC_TAMPCR_TAMP1E   0x00000001U
#define RTC_TAMPCR_TAMP1IE   0x00010000U
#define RTC_TAMPCR_TAMP1MF   0x00040000U
#define RTC_TAMPCR_TAMP1NOERASE   0x00020000U
#define RTC_TAMPCR_TAMP1TRG   0x00000002U
#define RTC_TAMPCR_TAMP2_TRG   RTC_TAMPCR_TAMP2TRG
#define RTC_TAMPCR_TAMP2E   0x00000008U
#define RTC_TAMPCR_TAMP2IE   0x00080000U
#define RTC_TAMPCR_TAMP2MF   0x00200000U
#define RTC_TAMPCR_TAMP2NOERASE   0x00100000U
#define RTC_TAMPCR_TAMP2TRG   0x00000010U
#define RTC_TAMPCR_TAMP3_TRG   RTC_TAMPCR_TAMP3TRG
#define RTC_TAMPCR_TAMP3E   0x00000020U
#define RTC_TAMPCR_TAMP3IE   0x00400000U
#define RTC_TAMPCR_TAMP3MF   0x01000000U
#define RTC_TAMPCR_TAMP3NOERASE   0x00800000U
#define RTC_TAMPCR_TAMP3TRG   0x00000040U
#define RTC_TAMPCR_TAMPFLT   0x00001800U
#define RTC_TAMPCR_TAMPFLT_0   0x00000800U
#define RTC_TAMPCR_TAMPFLT_1   0x00001000U
#define RTC_TAMPCR_TAMPFREQ   0x00000700U
#define RTC_TAMPCR_TAMPFREQ_0   0x00000100U
#define RTC_TAMPCR_TAMPFREQ_1   0x00000200U
#define RTC_TAMPCR_TAMPFREQ_2   0x00000400U
#define RTC_TAMPCR_TAMPIE   0x00000004U
#define RTC_TAMPCR_TAMPPRCH   0x00006000U
#define RTC_TAMPCR_TAMPPRCH_0   0x00002000U
#define RTC_TAMPCR_TAMPPRCH_1   0x00004000U
#define RTC_TAMPCR_TAMPPUDIS   0x00008000U
#define RTC_TAMPCR_TAMPTS   0x00000080U
#define RTC_TR_HT   0x00300000U
#define RTC_TR_HT_0   0x00100000U
#define RTC_TR_HT_1   0x00200000U
#define RTC_TR_HU   0x000F0000U
#define RTC_TR_HU_0   0x00010000U
#define RTC_TR_HU_1   0x00020000U
#define RTC_TR_HU_2   0x00040000U
#define RTC_TR_HU_3   0x00080000U
#define RTC_TR_MNT   0x00007000U
#define RTC_TR_MNT_0   0x00001000U
#define RTC_TR_MNT_1   0x00002000U
#define RTC_TR_MNT_2   0x00004000U
#define RTC_TR_MNU   0x00000F00U
#define RTC_TR_MNU_0   0x00000100U
#define RTC_TR_MNU_1   0x00000200U
#define RTC_TR_MNU_2   0x00000400U
#define RTC_TR_MNU_3   0x00000800U
#define RTC_TR_PM   0x00400000U
#define RTC_TR_ST   0x00000070U
#define RTC_TR_ST_0   0x00000010U
#define RTC_TR_ST_1   0x00000020U
#define RTC_TR_ST_2   0x00000040U
#define RTC_TR_SU   0x0000000FU
#define RTC_TR_SU_0   0x00000001U
#define RTC_TR_SU_1   0x00000002U
#define RTC_TR_SU_2   0x00000004U
#define RTC_TR_SU_3   0x00000008U
#define RTC_TSDR_DT   0x00000030U
#define RTC_TSDR_DT_0   0x00000010U
#define RTC_TSDR_DT_1   0x00000020U
#define RTC_TSDR_DU   0x0000000FU
#define RTC_TSDR_DU_0   0x00000001U
#define RTC_TSDR_DU_1   0x00000002U
#define RTC_TSDR_DU_2   0x00000004U
#define RTC_TSDR_DU_3   0x00000008U
#define RTC_TSDR_MT   0x00001000U
#define RTC_TSDR_MU   0x00000F00U
#define RTC_TSDR_MU_0   0x00000100U
#define RTC_TSDR_MU_1   0x00000200U
#define RTC_TSDR_MU_2   0x00000400U
#define RTC_TSDR_MU_3   0x00000800U
#define RTC_TSDR_WDU   0x0000E000U
#define RTC_TSDR_WDU_0   0x00002000U
#define RTC_TSDR_WDU_1   0x00004000U
#define RTC_TSDR_WDU_2   0x00008000U
#define RTC_TSSSR_SS   0x0000FFFFU
#define RTC_TSTR_HT   0x00300000U
#define RTC_TSTR_HT_0   0x00100000U
#define RTC_TSTR_HT_1   0x00200000U
#define RTC_TSTR_HU   0x000F0000U
#define RTC_TSTR_HU_0   0x00010000U
#define RTC_TSTR_HU_1   0x00020000U
#define RTC_TSTR_HU_2   0x00040000U
#define RTC_TSTR_HU_3   0x00080000U
#define RTC_TSTR_MNT   0x00007000U
#define RTC_TSTR_MNT_0   0x00001000U
#define RTC_TSTR_MNT_1   0x00002000U
#define RTC_TSTR_MNT_2   0x00004000U
#define RTC_TSTR_MNU   0x00000F00U
#define RTC_TSTR_MNU_0   0x00000100U
#define RTC_TSTR_MNU_1   0x00000200U
#define RTC_TSTR_MNU_2   0x00000400U
#define RTC_TSTR_MNU_3   0x00000800U
#define RTC_TSTR_PM   0x00400000U
#define RTC_TSTR_ST   0x00000070U
#define RTC_TSTR_ST_0   0x00000010U
#define RTC_TSTR_ST_1   0x00000020U
#define RTC_TSTR_ST_2   0x00000040U
#define RTC_TSTR_SU   0x0000000FU
#define RTC_TSTR_SU_0   0x00000001U
#define RTC_TSTR_SU_1   0x00000002U
#define RTC_TSTR_SU_2   0x00000004U
#define RTC_TSTR_SU_3   0x00000008U
#define RTC_WPR_KEY   0x000000FFU
#define RTC_WUTR_WUT   0x0000FFFFU
#define SAI_GCR_SYNCIN   0x00000003U

SYNCIN[1:0] bits (Synchronization Inputs)

#define SAI_GCR_SYNCIN_0   0x00000001U

Bit 0

#define SAI_GCR_SYNCIN_1   0x00000002U

Bit 1

#define SAI_GCR_SYNCOUT   0x00000030U

SYNCOUT[1:0] bits (Synchronization Outputs)

#define SAI_GCR_SYNCOUT_0   0x00000010U

Bit 0

#define SAI_GCR_SYNCOUT_1   0x00000020U

Bit 1

#define SAI_xCLRFR_CAFSDET   0x00000020U

Clear Anticipated frame synchronization detection

#define SAI_xCLRFR_CCNRDY   0x00000010U

Clear Codec not ready

#define SAI_xCLRFR_CFREQ   0x00000008U

Clear FIFO request

#define SAI_xCLRFR_CLFSDET   0x00000040U

Clear Late frame synchronization detection

#define SAI_xCLRFR_CMUTEDET   0x00000002U

Clear Mute detection

#define SAI_xCLRFR_COVRUDR   0x00000001U

Clear Overrun underrun

#define SAI_xCLRFR_CWCKCFG   0x00000004U

Clear Wrong Clock Configuration

#define SAI_xCR1_CKSTR   0x00000200U

ClocK STRobing edge

#define SAI_xCR1_DMAEN   0x00020000U

DMA enable

#define SAI_xCR1_DS   0x000000E0U

DS[1:0] bits (Data Size)

#define SAI_xCR1_DS_0   0x00000020U

Bit 0

#define SAI_xCR1_DS_1   0x00000040U

Bit 1

#define SAI_xCR1_DS_2   0x00000080U

Bit 2

#define SAI_xCR1_LSBFIRST   0x00000100U

LSB First Configuration

#define SAI_xCR1_MCKDIV   0x00F00000U

MCKDIV[3:0] (Master ClocK Divider)

#define SAI_xCR1_MCKDIV_0   0x00100000U

Bit 0

#define SAI_xCR1_MCKDIV_1   0x00200000U

Bit 1

#define SAI_xCR1_MCKDIV_2   0x00400000U

Bit 2

#define SAI_xCR1_MCKDIV_3   0x00800000U

Bit 3

#define SAI_xCR1_MODE   0x00000003U

MODE[1:0] bits (Audio Block Mode)

#define SAI_xCR1_MODE_0   0x00000001U

Bit 0

#define SAI_xCR1_MODE_1   0x00000002U

Bit 1

#define SAI_xCR1_MONO   0x00001000U

Mono mode

#define SAI_xCR1_NODIV   0x00080000U

No Divider Configuration

#define SAI_xCR1_OUTDRIV   0x00002000U

Output Drive

#define SAI_xCR1_PRTCFG   0x0000000CU

PRTCFG[1:0] bits (Protocol Configuration)

#define SAI_xCR1_PRTCFG_0   0x00000004U

Bit 0

#define SAI_xCR1_PRTCFG_1   0x00000008U

Bit 1

#define SAI_xCR1_SAIEN   0x00010000U

Audio Block enable

#define SAI_xCR1_SYNCEN   0x00000C00U

SYNCEN[1:0](SYNChronization ENable)

#define SAI_xCR1_SYNCEN_0   0x00000400U

Bit 0

#define SAI_xCR1_SYNCEN_1   0x00000800U

Bit 1

#define SAI_xCR2_COMP   0x0000C000U

COMP[1:0] (Companding mode)

#define SAI_xCR2_COMP_0   0x00004000U

Bit 0

#define SAI_xCR2_COMP_1   0x00008000U

Bit 1

#define SAI_xCR2_CPL   0x00002000U

Complement Bit

#define SAI_xCR2_FFLUSH   0x00000008U

Fifo FLUSH

#define SAI_xCR2_FTH   0x00000007U

FTH[2:0](Fifo THreshold)

#define SAI_xCR2_FTH_0   0x00000001U

Bit 0

#define SAI_xCR2_FTH_1   0x00000002U

Bit 1

#define SAI_xCR2_FTH_2   0x00000004U

Bit 2

#define SAI_xCR2_MUTE   0x00000020U

Mute mode

#define SAI_xCR2_MUTECNT   0x00001F80U

MUTECNT[5:0] (MUTE counter)

#define SAI_xCR2_MUTECNT_0   0x00000080U

Bit 0

#define SAI_xCR2_MUTECNT_1   0x00000100U

Bit 1

#define SAI_xCR2_MUTECNT_2   0x00000200U

Bit 2

#define SAI_xCR2_MUTECNT_3   0x00000400U

Bit 3

#define SAI_xCR2_MUTECNT_4   0x00000800U

Bit 4

#define SAI_xCR2_MUTECNT_5   0x00001000U

Bit 5

#define SAI_xCR2_MUTEVAL   0x00000040U

Muate value

#define SAI_xCR2_TRIS   0x00000010U

TRIState Management on data line

#define SAI_xDR_DATA   0xFFFFFFFFU
#define SAI_xFRCR_FRL   0x000000FFU

FRL[1:0](Frame length)

#define SAI_xFRCR_FRL_0   0x00000001U

Bit 0

#define SAI_xFRCR_FRL_1   0x00000002U

Bit 1

#define SAI_xFRCR_FRL_2   0x00000004U

Bit 2

#define SAI_xFRCR_FRL_3   0x00000008U

Bit 3

#define SAI_xFRCR_FRL_4   0x00000010U

Bit 4

#define SAI_xFRCR_FRL_5   0x00000020U

Bit 5

#define SAI_xFRCR_FRL_6   0x00000040U

Bit 6

#define SAI_xFRCR_FRL_7   0x00000080U

Bit 7

#define SAI_xFRCR_FSALL   0x00007F00U

FRL[1:0] (Frame synchronization active level length)

#define SAI_xFRCR_FSALL_0   0x00000100U

Bit 0

#define SAI_xFRCR_FSALL_1   0x00000200U

Bit 1

#define SAI_xFRCR_FSALL_2   0x00000400U

Bit 2

#define SAI_xFRCR_FSALL_3   0x00000800U

Bit 3

#define SAI_xFRCR_FSALL_4   0x00001000U

Bit 4

#define SAI_xFRCR_FSALL_5   0x00002000U

Bit 5

#define SAI_xFRCR_FSALL_6   0x00004000U

Bit 6

#define SAI_xFRCR_FSDEF   0x00010000U

Frame Synchronization Definition

#define SAI_xFRCR_FSOFF   0x00040000U

Frame Synchronization OFFset

#define SAI_xFRCR_FSPO   SAI_xFRCR_FSPOL
#define SAI_xFRCR_FSPOL   0x00020000U

Frame Synchronization POLarity

#define SAI_xIMR_AFSDETIE   0x00000020U

Anticipated frame synchronization detection interrupt enable

#define SAI_xIMR_CNRDYIE   0x00000010U

Codec not ready interrupt enable

#define SAI_xIMR_FREQIE   0x00000008U

FIFO request interrupt enable

#define SAI_xIMR_LFSDETIE   0x00000040U

Late frame synchronization detection interrupt enable

#define SAI_xIMR_MUTEDETIE   0x00000002U

Mute detection interrupt enable

#define SAI_xIMR_OVRUDRIE   0x00000001U

Overrun underrun interrupt enable

#define SAI_xIMR_WCKCFGIE   0x00000004U

Wrong Clock Configuration interrupt enable

#define SAI_xSLOTR_FBOFF   0x0000001FU

FRL[4:0](First Bit Offset)

#define SAI_xSLOTR_FBOFF_0   0x00000001U

Bit 0

#define SAI_xSLOTR_FBOFF_1   0x00000002U

Bit 1

#define SAI_xSLOTR_FBOFF_2   0x00000004U

Bit 2

#define SAI_xSLOTR_FBOFF_3   0x00000008U

Bit 3

#define SAI_xSLOTR_FBOFF_4   0x00000010U

Bit 4

#define SAI_xSLOTR_NBSLOT   0x00000F00U

NBSLOT[3:0] (Number of Slot in audio Frame)

#define SAI_xSLOTR_NBSLOT_0   0x00000100U

Bit 0

#define SAI_xSLOTR_NBSLOT_1   0x00000200U

Bit 1

#define SAI_xSLOTR_NBSLOT_2   0x00000400U

Bit 2

#define SAI_xSLOTR_NBSLOT_3   0x00000800U

Bit 3

#define SAI_xSLOTR_SLOTEN   0xFFFF0000U

SLOTEN[15:0] (Slot Enable)

#define SAI_xSLOTR_SLOTSZ   0x000000C0U

SLOTSZ[1:0] (Slot size)

#define SAI_xSLOTR_SLOTSZ_0   0x00000040U

Bit 0

#define SAI_xSLOTR_SLOTSZ_1   0x00000080U

Bit 1

#define SAI_xSR_AFSDET   0x00000020U

Anticipated frame synchronization detection

#define SAI_xSR_CNRDY   0x00000010U

Codec not ready

#define SAI_xSR_FLVL   0x00070000U

FLVL[2:0] (FIFO Level Threshold)

#define SAI_xSR_FLVL_0   0x00010000U

Bit 0

#define SAI_xSR_FLVL_1   0x00020000U

Bit 1

#define SAI_xSR_FLVL_2   0x00040000U

Bit 2

#define SAI_xSR_FREQ   0x00000008U

FIFO request

#define SAI_xSR_LFSDET   0x00000040U

Late frame synchronization detection

#define SAI_xSR_MUTEDET   0x00000002U

Mute detection

#define SAI_xSR_OVRUDR   0x00000001U

Overrun underrun

#define SAI_xSR_WCKCFG   0x00000004U

Wrong Clock Configuration

#define SDMMC_ARG_CMDARG   0xFFFFFFFFU

Command argument

#define SDMMC_CLKCR_BYPASS   0x0400U

Clock divider bypass enable bit

#define SDMMC_CLKCR_CLKDIV   0x00FFU

Clock divide factor

#define SDMMC_CLKCR_CLKEN   0x0100U

Clock enable bit

#define SDMMC_CLKCR_HWFC_EN   0x4000U

HW Flow Control enable

#define SDMMC_CLKCR_NEGEDGE   0x2000U

SDMMC_CK dephasing selection bit

#define SDMMC_CLKCR_PWRSAV   0x0200U

Power saving configuration bit

#define SDMMC_CLKCR_WIDBUS   0x1800U

WIDBUS[1:0] bits (Wide bus mode enable bit)

#define SDMMC_CLKCR_WIDBUS_0   0x0800U

Bit 0

#define SDMMC_CLKCR_WIDBUS_1   0x1000U

Bit 1

#define SDMMC_CMD_CMDINDEX   0x003FU

Command Index

#define SDMMC_CMD_CPSMEN   0x0400U

Command path state machine (CPSM) Enable bit

#define SDMMC_CMD_SDIOSUSPEND   0x0800U

SD I/O suspend command

#define SDMMC_CMD_WAITINT   0x0100U

CPSM Waits for Interrupt Request

#define SDMMC_CMD_WAITPEND   0x0200U

CPSM Waits for ends of data transfer (CmdPend internal signal)

#define SDMMC_CMD_WAITRESP   0x00C0U

WAITRESP[1:0] bits (Wait for response bits)

#define SDMMC_CMD_WAITRESP_0   0x0040U

Bit 0

#define SDMMC_CMD_WAITRESP_1   0x0080U

Bit 1

#define SDMMC_DCOUNT_DATACOUNT   0x01FFFFFFU

Data count value

#define SDMMC_DCTRL_DBLOCKSIZE   0x00F0U

DBLOCKSIZE[3:0] bits (Data block size)

#define SDMMC_DCTRL_DBLOCKSIZE_0   0x0010U

Bit 0

#define SDMMC_DCTRL_DBLOCKSIZE_1   0x0020U

Bit 1

#define SDMMC_DCTRL_DBLOCKSIZE_2   0x0040U

Bit 2

#define SDMMC_DCTRL_DBLOCKSIZE_3   0x0080U

Bit 3

#define SDMMC_DCTRL_DMAEN   0x0008U

DMA enabled bit

#define SDMMC_DCTRL_DTDIR   0x0002U

Data transfer direction selection

#define SDMMC_DCTRL_DTEN   0x0001U

Data transfer enabled bit

#define SDMMC_DCTRL_DTMODE   0x0004U

Data transfer mode selection

#define SDMMC_DCTRL_RWMOD   0x0400U

Read wait mode

#define SDMMC_DCTRL_RWSTART   0x0100U

Read wait start

#define SDMMC_DCTRL_RWSTOP   0x0200U

Read wait stop

#define SDMMC_DCTRL_SDIOEN   0x0800U

SD I/O enable functions

#define SDMMC_DLEN_DATALENGTH   0x01FFFFFFU

Data length value

#define SDMMC_DTIMER_DATATIME   0xFFFFFFFFU

Data timeout period.

#define SDMMC_FIFO_FIFODATA   0xFFFFFFFFU

Receive and transmit FIFO data

#define SDMMC_FIFOCNT_FIFOCOUNT   0x00FFFFFFU

Remaining number of words to be written to or read from the FIFO

#define SDMMC_ICR_CCRCFAILC   0x00000001U

CCRCFAIL flag clear bit

#define SDMMC_ICR_CMDRENDC   0x00000040U

CMDREND flag clear bit

#define SDMMC_ICR_CMDSENTC   0x00000080U

CMDSENT flag clear bit

#define SDMMC_ICR_CTIMEOUTC   0x00000004U

CTIMEOUT flag clear bit

#define SDMMC_ICR_DATAENDC   0x00000100U

DATAEND flag clear bit

#define SDMMC_ICR_DBCKENDC   0x00000400U

DBCKEND flag clear bit

#define SDMMC_ICR_DCRCFAILC   0x00000002U

DCRCFAIL flag clear bit

#define SDMMC_ICR_DTIMEOUTC   0x00000008U

DTIMEOUT flag clear bit

#define SDMMC_ICR_RXOVERRC   0x00000020U

RXOVERR flag clear bit

#define SDMMC_ICR_SDIOITC   0x00400000U

SDMMCIT flag clear bit

#define SDMMC_ICR_TXUNDERRC   0x00000010U

TXUNDERR flag clear bit

#define SDMMC_MASK_CCRCFAILIE   0x00000001U

Command CRC Fail Interrupt Enable

#define SDMMC_MASK_CMDACTIE   0x00000800U

CCommand Acting Interrupt Enable

#define SDMMC_MASK_CMDRENDIE   0x00000040U

Command Response Received Interrupt Enable

#define SDMMC_MASK_CMDSENTIE   0x00000080U

Command Sent Interrupt Enable

#define SDMMC_MASK_CTIMEOUTIE   0x00000004U

Command TimeOut Interrupt Enable

#define SDMMC_MASK_DATAENDIE   0x00000100U

Data End Interrupt Enable

#define SDMMC_MASK_DBCKENDIE   0x00000400U

Data Block End Interrupt Enable

#define SDMMC_MASK_DCRCFAILIE   0x00000002U

Data CRC Fail Interrupt Enable

#define SDMMC_MASK_DTIMEOUTIE   0x00000008U

Data TimeOut Interrupt Enable

#define SDMMC_MASK_RXACTIE   0x00002000U

Data receive acting interrupt enabled

#define SDMMC_MASK_RXDAVLIE   0x00200000U

Data available in Rx FIFO interrupt Enable

#define SDMMC_MASK_RXFIFOEIE   0x00080000U

Rx FIFO Empty interrupt Enable

#define SDMMC_MASK_RXFIFOFIE   0x00020000U

Rx FIFO Full interrupt Enable

#define SDMMC_MASK_RXFIFOHFIE   0x00008000U

Rx FIFO Half Full interrupt Enable

#define SDMMC_MASK_RXOVERRIE   0x00000020U

Rx FIFO OverRun Error Interrupt Enable

#define SDMMC_MASK_SDIOITIE   0x00400000U

SDMMC Mode Interrupt Received interrupt Enable

#define SDMMC_MASK_TXACTIE   0x00001000U

Data Transmit Acting Interrupt Enable

#define SDMMC_MASK_TXDAVLIE   0x00100000U

Data available in Tx FIFO interrupt Enable

#define SDMMC_MASK_TXFIFOEIE   0x00040000U

Tx FIFO Empty interrupt Enable

#define SDMMC_MASK_TXFIFOFIE   0x00010000U

Tx FIFO Full interrupt Enable

#define SDMMC_MASK_TXFIFOHEIE   0x00004000U

Tx FIFO Half Empty interrupt Enable

#define SDMMC_MASK_TXUNDERRIE   0x00000010U

Tx FIFO UnderRun Error Interrupt Enable

#define SDMMC_POWER_PWRCTRL   0x03U

PWRCTRL[1:0] bits (Power supply control bits)

#define SDMMC_POWER_PWRCTRL_0   0x01U

Bit 0

#define SDMMC_POWER_PWRCTRL_1   0x02U

Bit 1

#define SDMMC_RESP0_CARDSTATUS0   0xFFFFFFFFU

Card Status

#define SDMMC_RESP1_CARDSTATUS1   0xFFFFFFFFU

Card Status

#define SDMMC_RESP2_CARDSTATUS2   0xFFFFFFFFU

Card Status

#define SDMMC_RESP3_CARDSTATUS3   0xFFFFFFFFU

Card Status

#define SDMMC_RESP4_CARDSTATUS4   0xFFFFFFFFU

Card Status

#define SDMMC_RESPCMD_RESPCMD   0x3FU

Response command index

#define SDMMC_STA_CCRCFAIL   0x00000001U

Command response received (CRC check failed)

#define SDMMC_STA_CMDACT   0x00000800U

Command transfer in progress

#define SDMMC_STA_CMDREND   0x00000040U

Command response received (CRC check passed)

#define SDMMC_STA_CMDSENT   0x00000080U

Command sent (no response required)

#define SDMMC_STA_CTIMEOUT   0x00000004U

Command response timeout

#define SDMMC_STA_DATAEND   0x00000100U

Data end (data counter, SDIDCOUNT, is zero)

#define SDMMC_STA_DBCKEND   0x00000400U

Data block sent/received (CRC check passed)

#define SDMMC_STA_DCRCFAIL   0x00000002U

Data block sent/received (CRC check failed)

#define SDMMC_STA_DTIMEOUT   0x00000008U

Data timeout

#define SDMMC_STA_RXACT   0x00002000U

Data receive in progress

#define SDMMC_STA_RXDAVL   0x00200000U

Data available in receive FIFO

#define SDMMC_STA_RXFIFOE   0x00080000U

Receive FIFO empty

#define SDMMC_STA_RXFIFOF   0x00020000U

Receive FIFO full

#define SDMMC_STA_RXFIFOHF   0x00008000U

Receive FIFO Half Full: there are at least 8 words in the FIFO

#define SDMMC_STA_RXOVERR   0x00000020U

Received FIFO overrun error

#define SDMMC_STA_SDIOIT   0x00400000U

SDMMC interrupt received

#define SDMMC_STA_TXACT   0x00001000U

Data transmit in progress

#define SDMMC_STA_TXDAVL   0x00100000U

Data available in transmit FIFO

#define SDMMC_STA_TXFIFOE   0x00040000U

Transmit FIFO empty

#define SDMMC_STA_TXFIFOF   0x00010000U

Transmit FIFO full

#define SDMMC_STA_TXFIFOHE   0x00004000U

Transmit FIFO Half Empty: at least 8 words can be written into the FIFO

#define SDMMC_STA_TXUNDERR   0x00000010U

Transmit FIFO underrun error

#define SPDIFRX_CR_CBDMAEN   0x00000400U

Control Buffer DMA ENable for control flow

#define SPDIFRX_CR_CHSEL   0x00000800U

Channel Selection

#define SPDIFRX_CR_CUMSK   0x00000100U

Mask of channel status and user bits

#define SPDIFRX_CR_DRFMT   0x00000030U

RX Data format

#define SPDIFRX_CR_INSEL   0x00070000U

SPDIF input selection

#define SPDIFRX_CR_NBTR   0x00003000U

Maximum allowed re-tries during synchronization phase

#define SPDIFRX_CR_PMSK   0x00000040U

Mask Parity error bit

#define SPDIFRX_CR_PTMSK   0x00000200U

Mask of Preamble Type bits

#define SPDIFRX_CR_RXDMAEN   0x00000004U

Receiver DMA Enable for data flow

#define SPDIFRX_CR_RXSTEO   0x00000008U

Stereo Mode

#define SPDIFRX_CR_SPDIFEN   0x00000003U

Peripheral Block Enable

#define SPDIFRX_CR_VMSK   0x00000080U

Mask of Validity bit

#define SPDIFRX_CR_WFA   0x00004000U

Wait For Activity

#define SPDIFRX_CSR_CS   0x00FF0000U

Channel A status information

#define SPDIFRX_CSR_SOB   0x01000000U

Start Of Block

#define SPDIFRX_CSR_USR   0x0000FFFFU

User data information

#define SPDIFRX_DIR_THI   0x000013FFU

Threshold LOW

#define SPDIFRX_DIR_TLO   0x1FFF0000U

Threshold HIGH

#define SPDIFRX_DR0_C   0x08000000U

Channel Status bit

#define SPDIFRX_DR0_DR   0x00FFFFFFU

Data value

#define SPDIFRX_DR0_PE   0x01000000U

Parity Error bit

#define SPDIFRX_DR0_PT   0x30000000U

Preamble Type

#define SPDIFRX_DR0_U   0x04000000U

User bit

#define SPDIFRX_DR0_V   0x02000000U

Validity bit

#define SPDIFRX_DR1_C   0x00000008U

Channel Status bit

#define SPDIFRX_DR1_DR   0xFFFFFF00U

Data value

#define SPDIFRX_DR1_DRNL1   0xFFFF0000U

Data value Channel B

#define SPDIFRX_DR1_DRNL2   0x0000FFFFU

Data value Channel A

#define SPDIFRX_DR1_PE   0x00000001U

Parity Error bit

#define SPDIFRX_DR1_PT   0x00000030U

Preamble Type

#define SPDIFRX_DR1_U   0x00000004U

User bit

#define SPDIFRX_DR1_V   0x00000002U

Validity bit

#define SPDIFRX_IFCR_OVRCF   0x00000008U

Clears the Overrun error flag

#define SPDIFRX_IFCR_PERRCF   0x00000004U

Clears the Parity error flag

#define SPDIFRX_IFCR_SBDCF   0x00000010U

Clears the Synchronization Block Detected flag

#define SPDIFRX_IFCR_SYNCDCF   0x00000020U

Clears the Synchronization Done flag

#define SPDIFRX_IMR_CSRNEIE   0x00000002U

Control Buffer Ready Interrupt Enable

#define SPDIFRX_IMR_IFEIE   0x00000040U

Serial Interface Error Interrupt Enable

#define SPDIFRX_IMR_OVRIE   0x00000008U

Overrun error Interrupt Enable

#define SPDIFRX_IMR_PERRIE   0x00000004U

Parity error interrupt enable

#define SPDIFRX_IMR_RXNEIE   0x00000001U

RXNE interrupt enable

#define SPDIFRX_IMR_SBLKIE   0x00000010U

Synchronization Block Detected Interrupt Enable

#define SPDIFRX_IMR_SYNCDIE   0x00000020U

Synchronization Done

#define SPDIFRX_SR_CSRNE   0x00000002U

The Control Buffer register is not empty

#define SPDIFRX_SR_FERR   0x00000040U

Framing error

#define SPDIFRX_SR_OVR   0x00000008U

Overrun error

#define SPDIFRX_SR_PERR   0x00000004U

Parity error

#define SPDIFRX_SR_RXNE   0x00000001U

Read data register not empty

#define SPDIFRX_SR_SBD   0x00000010U

Synchronization Block Detected

#define SPDIFRX_SR_SERR   0x00000080U

Synchronization error

#define SPDIFRX_SR_SYNCD   0x00000020U

Synchronization Done

#define SPDIFRX_SR_TERR   0x00000100U

Time-out error

#define SPDIFRX_SR_WIDTH5   0x7FFF0000U

Duration of 5 symbols counted with spdif_clk

#define SPI_CR1_BIDIMODE   0x00008000U

Bidirectional data mode enable

#define SPI_CR1_BIDIOE   0x00004000U

Output enable in bidirectional mode

#define SPI_CR1_BR   0x00000038U

BR[2:0] bits (Baud Rate Control)

#define SPI_CR1_BR_0   0x00000008U

Bit 0

#define SPI_CR1_BR_1   0x00000010U

Bit 1

#define SPI_CR1_BR_2   0x00000020U

Bit 2

#define SPI_CR1_CPHA   0x00000001U

Clock Phase

#define SPI_CR1_CPOL   0x00000002U

Clock Polarity

#define SPI_CR1_CRCEN   0x00002000U

Hardware CRC calculation enable

#define SPI_CR1_CRCL   0x00000800U

CRC Length

#define SPI_CR1_CRCNEXT   0x00001000U

Transmit CRC next

#define SPI_CR1_LSBFIRST   0x00000080U

Frame Format

#define SPI_CR1_MSTR   0x00000004U

Master Selection

#define SPI_CR1_RXONLY   0x00000400U

Receive only

#define SPI_CR1_SPE   0x00000040U

SPI Enable

#define SPI_CR1_SSI   0x00000100U

Internal slave select

#define SPI_CR1_SSM   0x00000200U

Software slave management

#define SPI_CR2_DS   0x00000F00U

DS[3:0] Data Size

#define SPI_CR2_DS_0   0x00000100U

Bit 0

#define SPI_CR2_DS_1   0x00000200U

Bit 1

#define SPI_CR2_DS_2   0x00000400U

Bit 2

#define SPI_CR2_DS_3   0x00000800U

Bit 3

#define SPI_CR2_ERRIE   0x00000020U

Error Interrupt Enable

#define SPI_CR2_FRF   0x00000010U

Frame Format Enable

#define SPI_CR2_FRXTH   0x00001000U

FIFO reception Threshold

#define SPI_CR2_LDMARX   0x00002000U

Last DMA transfer for reception

#define SPI_CR2_LDMATX   0x00004000U

Last DMA transfer for transmission

#define SPI_CR2_NSSP   0x00000008U

NSS pulse management Enable

#define SPI_CR2_RXDMAEN   0x00000001U

Rx Buffer DMA Enable

#define SPI_CR2_RXNEIE   0x00000040U

RX buffer Not Empty Interrupt Enable

#define SPI_CR2_SSOE   0x00000004U

SS Output Enable

#define SPI_CR2_TXDMAEN   0x00000002U

Tx Buffer DMA Enable

#define SPI_CR2_TXEIE   0x00000080U

Tx buffer Empty Interrupt Enable

#define SPI_CRCPR_CRCPOLY   0xFFFFU

CRC polynomial register

#define SPI_DR_DR   0xFFFFU

Data Register

#define SPI_I2SCFGR_ASTRTEN   0x00001000U

Asynchronous start enable

#define SPI_I2SCFGR_CHLEN   0x00000001U

Channel length (number of bits per audio channel)

#define SPI_I2SCFGR_CKPOL   0x00000008U

steady state clock polarity

#define SPI_I2SCFGR_DATLEN   0x00000006U

DATLEN[1:0] bits (Data length to be transferred)

#define SPI_I2SCFGR_DATLEN_0   0x00000002U

Bit 0

#define SPI_I2SCFGR_DATLEN_1   0x00000004U

Bit 1

#define SPI_I2SCFGR_I2SCFG   0x00000300U

I2SCFG[1:0] bits (I2S configuration mode)

#define SPI_I2SCFGR_I2SCFG_0   0x00000100U

Bit 0

#define SPI_I2SCFGR_I2SCFG_1   0x00000200U

Bit 1

#define SPI_I2SCFGR_I2SE   0x00000400U

I2S Enable

#define SPI_I2SCFGR_I2SMOD   0x00000800U

I2S mode selection

#define SPI_I2SCFGR_I2SSTD   0x00000030U

I2SSTD[1:0] bits (I2S standard selection)

#define SPI_I2SCFGR_I2SSTD_0   0x00000010U

Bit 0

#define SPI_I2SCFGR_I2SSTD_1   0x00000020U

Bit 1

#define SPI_I2SCFGR_PCMSYNC   0x00000080U

PCM frame synchronization

#define SPI_I2SPR_I2SDIV   0x00FFU

I2S Linear prescaler

#define SPI_I2SPR_MCKOE   0x0200U

Master Clock Output Enable

#define SPI_I2SPR_ODD   0x0100U

Odd factor for the prescaler

#define SPI_RXCRCR_RXCRC   0xFFFFU

Rx CRC Register

#define SPI_SR_BSY   0x00000080U

Busy flag

#define SPI_SR_CHSIDE   0x00000004U

Channel side

#define SPI_SR_CRCERR   0x00000010U

CRC Error flag

#define SPI_SR_FRE   0x00000100U

TI frame format error

#define SPI_SR_FRLVL   0x00000600U

FIFO Reception Level

#define SPI_SR_FRLVL_0   0x00000200U

Bit 0

#define SPI_SR_FRLVL_1   0x00000400U

Bit 1

#define SPI_SR_FTLVL   0x00001800U

FIFO Transmission Level

#define SPI_SR_FTLVL_0   0x00000800U

Bit 0

#define SPI_SR_FTLVL_1   0x00001000U

Bit 1

#define SPI_SR_MODF   0x00000020U

Mode fault

#define SPI_SR_OVR   0x00000040U

Overrun flag

#define SPI_SR_RXNE   0x00000001U

Receive buffer Not Empty

#define SPI_SR_TXE   0x00000002U

Transmit buffer Empty

#define SPI_SR_UDR   0x00000008U

Underrun flag

#define SPI_TXCRCR_TXCRC   0xFFFFU

Tx CRC Register

#define SYSCFG_CMPCR_CMP_PD   0x00000001U

Compensation cell power-down

#define SYSCFG_CMPCR_READY   0x00000100U

Compensation cell ready flag

#define SYSCFG_EXTICR1_EXTI0   0x000FU

EXTI 0 configuration

#define SYSCFG_EXTICR1_EXTI0_PA   0x0000U

EXTI0 configuration.

PA[0] pin

#define SYSCFG_EXTICR1_EXTI0_PB   0x0001U

PB[0] pin

#define SYSCFG_EXTICR1_EXTI0_PC   0x0002U

PC[0] pin

#define SYSCFG_EXTICR1_EXTI0_PD   0x0003U

PD[0] pin

#define SYSCFG_EXTICR1_EXTI0_PE   0x0004U

PE[0] pin

#define SYSCFG_EXTICR1_EXTI0_PF   0x0005U

PF[0] pin

#define SYSCFG_EXTICR1_EXTI0_PG   0x0006U

PG[0] pin

#define SYSCFG_EXTICR1_EXTI0_PH   0x0007U

PH[0] pin

#define SYSCFG_EXTICR1_EXTI0_PI   0x0008U

PI[0] pin

#define SYSCFG_EXTICR1_EXTI0_PJ   0x0009U

PJ[0] pin

#define SYSCFG_EXTICR1_EXTI0_PK   0x000AU

PK[0] pin

#define SYSCFG_EXTICR1_EXTI1   0x00F0U

EXTI 1 configuration

#define SYSCFG_EXTICR1_EXTI1_PA   0x0000U

EXTI1 configuration.

PA[1] pin

#define SYSCFG_EXTICR1_EXTI1_PB   0x0010U

PB[1] pin

#define SYSCFG_EXTICR1_EXTI1_PC   0x0020U

PC[1] pin

#define SYSCFG_EXTICR1_EXTI1_PD   0x0030U

PD[1] pin

#define SYSCFG_EXTICR1_EXTI1_PE   0x0040U

PE[1] pin

#define SYSCFG_EXTICR1_EXTI1_PF   0x0050U

PF[1] pin

#define SYSCFG_EXTICR1_EXTI1_PG   0x0060U

PG[1] pin

#define SYSCFG_EXTICR1_EXTI1_PH   0x0070U

PH[1] pin

#define SYSCFG_EXTICR1_EXTI1_PI   0x0080U

PI[1] pin

#define SYSCFG_EXTICR1_EXTI1_PJ   0x0090U

PJ[1] pin

#define SYSCFG_EXTICR1_EXTI1_PK   0x00A0U

PK[1] pin

#define SYSCFG_EXTICR1_EXTI2   0x0F00U

EXTI 2 configuration

#define SYSCFG_EXTICR1_EXTI2_PA   0x0000U

EXTI2 configuration.

PA[2] pin

#define SYSCFG_EXTICR1_EXTI2_PB   0x0100U

PB[2] pin

#define SYSCFG_EXTICR1_EXTI2_PC   0x0200U

PC[2] pin

#define SYSCFG_EXTICR1_EXTI2_PD   0x0300U

PD[2] pin

#define SYSCFG_EXTICR1_EXTI2_PE   0x0400U

PE[2] pin

#define SYSCFG_EXTICR1_EXTI2_PF   0x0500U

PF[2] pin

#define SYSCFG_EXTICR1_EXTI2_PG   0x0600U

PG[2] pin

#define SYSCFG_EXTICR1_EXTI2_PH   0x0700U

PH[2] pin

#define SYSCFG_EXTICR1_EXTI2_PI   0x0800U

PI[2] pin

#define SYSCFG_EXTICR1_EXTI2_PJ   0x0900U

PJ[2] pin

#define SYSCFG_EXTICR1_EXTI2_PK   0x0A00U

PK[2] pin

#define SYSCFG_EXTICR1_EXTI3   0xF000U

EXTI 3 configuration

#define SYSCFG_EXTICR1_EXTI3_PA   0x0000U

EXTI3 configuration.

PA[3] pin

#define SYSCFG_EXTICR1_EXTI3_PB   0x1000U

PB[3] pin

#define SYSCFG_EXTICR1_EXTI3_PC   0x2000U

PC[3] pin

#define SYSCFG_EXTICR1_EXTI3_PD   0x3000U

PD[3] pin

#define SYSCFG_EXTICR1_EXTI3_PE   0x4000U

PE[3] pin

#define SYSCFG_EXTICR1_EXTI3_PF   0x5000U

PF[3] pin

#define SYSCFG_EXTICR1_EXTI3_PG   0x6000U

PG[3] pin

#define SYSCFG_EXTICR1_EXTI3_PH   0x7000U

PH[3] pin

#define SYSCFG_EXTICR1_EXTI3_PI   0x8000U

PI[3] pin

#define SYSCFG_EXTICR1_EXTI3_PJ   0x9000U

PJ[3] pin

#define SYSCFG_EXTICR1_EXTI3_PK   0xA000U

PK[3] pin

#define SYSCFG_EXTICR2_EXTI4   0x000FU

EXTI 4 configuration

#define SYSCFG_EXTICR2_EXTI4_PA   0x0000U

EXTI4 configuration.

PA[4] pin

#define SYSCFG_EXTICR2_EXTI4_PB   0x0001U

PB[4] pin

#define SYSCFG_EXTICR2_EXTI4_PC   0x0002U

PC[4] pin

#define SYSCFG_EXTICR2_EXTI4_PD   0x0003U

PD[4] pin

#define SYSCFG_EXTICR2_EXTI4_PE   0x0004U

PE[4] pin

#define SYSCFG_EXTICR2_EXTI4_PF   0x0005U

PF[4] pin

#define SYSCFG_EXTICR2_EXTI4_PG   0x0006U

PG[4] pin

#define SYSCFG_EXTICR2_EXTI4_PH   0x0007U

PH[4] pin

#define SYSCFG_EXTICR2_EXTI4_PI   0x0008U

PI[4] pin

#define SYSCFG_EXTICR2_EXTI4_PJ   0x0009U

PJ[4] pin

#define SYSCFG_EXTICR2_EXTI4_PK   0x000AU

PK[4] pin

#define SYSCFG_EXTICR2_EXTI5   0x00F0U

EXTI 5 configuration

#define SYSCFG_EXTICR2_EXTI5_PA   0x0000U

EXTI5 configuration.

PA[5] pin

#define SYSCFG_EXTICR2_EXTI5_PB   0x0010U

PB[5] pin

#define SYSCFG_EXTICR2_EXTI5_PC   0x0020U

PC[5] pin

#define SYSCFG_EXTICR2_EXTI5_PD   0x0030U

PD[5] pin

#define SYSCFG_EXTICR2_EXTI5_PE   0x0040U

PE[5] pin

#define SYSCFG_EXTICR2_EXTI5_PF   0x0050U

PF[5] pin

#define SYSCFG_EXTICR2_EXTI5_PG   0x0060U

PG[5] pin

#define SYSCFG_EXTICR2_EXTI5_PH   0x0070U

PH[5] pin

#define SYSCFG_EXTICR2_EXTI5_PI   0x0080U

PI[5] pin

#define SYSCFG_EXTICR2_EXTI5_PJ   0x0090U

PJ[5] pin

#define SYSCFG_EXTICR2_EXTI5_PK   0x00A0U

PK[5] pin

#define SYSCFG_EXTICR2_EXTI6   0x0F00U

EXTI 6 configuration

#define SYSCFG_EXTICR2_EXTI6_PA   0x0000U

EXTI6 configuration.

PA[6] pin

#define SYSCFG_EXTICR2_EXTI6_PB   0x0100U

PB[6] pin

#define SYSCFG_EXTICR2_EXTI6_PC   0x0200U

PC[6] pin

#define SYSCFG_EXTICR2_EXTI6_PD   0x0300U

PD[6] pin

#define SYSCFG_EXTICR2_EXTI6_PE   0x0400U

PE[6] pin

#define SYSCFG_EXTICR2_EXTI6_PF   0x0500U

PF[6] pin

#define SYSCFG_EXTICR2_EXTI6_PG   0x0600U

PG[6] pin

#define SYSCFG_EXTICR2_EXTI6_PH   0x0700U

PH[6] pin

#define SYSCFG_EXTICR2_EXTI6_PI   0x0800U

PI[6] pin

#define SYSCFG_EXTICR2_EXTI6_PJ   0x0900U

PJ[6] pin

#define SYSCFG_EXTICR2_EXTI6_PK   0x0A00U

PK[6] pin

#define SYSCFG_EXTICR2_EXTI7   0xF000U

EXTI 7 configuration

#define SYSCFG_EXTICR2_EXTI7_PA   0x0000U

EXTI7 configuration.

PA[7] pin

#define SYSCFG_EXTICR2_EXTI7_PB   0x1000U

PB[7] pin

#define SYSCFG_EXTICR2_EXTI7_PC   0x2000U

PC[7] pin

#define SYSCFG_EXTICR2_EXTI7_PD   0x3000U

PD[7] pin

#define SYSCFG_EXTICR2_EXTI7_PE   0x4000U

PE[7] pin

#define SYSCFG_EXTICR2_EXTI7_PF   0x5000U

PF[7] pin

#define SYSCFG_EXTICR2_EXTI7_PG   0x6000U

PG[7] pin

#define SYSCFG_EXTICR2_EXTI7_PH   0x7000U

PH[7] pin

#define SYSCFG_EXTICR2_EXTI7_PI   0x8000U

PI[7] pin

#define SYSCFG_EXTICR2_EXTI7_PJ   0x9000U

PJ[7] pin

#define SYSCFG_EXTICR2_EXTI7_PK   0xA000U

PK[7] pin

#define SYSCFG_EXTICR3_EXTI10   0x0F00U

EXTI 10 configuration

#define SYSCFG_EXTICR3_EXTI10_PA   0x0000U

EXTI10 configuration.

PA[10] pin

#define SYSCFG_EXTICR3_EXTI10_PB   0x0100U

PB[10] pin

#define SYSCFG_EXTICR3_EXTI10_PC   0x0200U

PC[10] pin

#define SYSCFG_EXTICR3_EXTI10_PD   0x0300U

PD[10] pin

#define SYSCFG_EXTICR3_EXTI10_PE   0x0400U

PE[10] pin

#define SYSCFG_EXTICR3_EXTI10_PF   0x0500U

PF[10] pin

#define SYSCFG_EXTICR3_EXTI10_PG   0x0600U

PG[10] pin

#define SYSCFG_EXTICR3_EXTI10_PH   0x0700U

PH[10] pin

#define SYSCFG_EXTICR3_EXTI10_PI   0x0800U

PI[10] pin

#define SYSCFG_EXTICR3_EXTI10_PJ   0x0900U

PJ[10] pin

#define SYSCFG_EXTICR3_EXTI11   0xF000U

EXTI 11 configuration

#define SYSCFG_EXTICR3_EXTI11_PA   0x0000U

EXTI11 configuration.

PA[11] pin

#define SYSCFG_EXTICR3_EXTI11_PB   0x1000U

PB[11] pin

#define SYSCFG_EXTICR3_EXTI11_PC   0x2000U

PC[11] pin

#define SYSCFG_EXTICR3_EXTI11_PD   0x3000U

PD[11] pin

#define SYSCFG_EXTICR3_EXTI11_PE   0x4000U

PE[11] pin

#define SYSCFG_EXTICR3_EXTI11_PF   0x5000U

PF[11] pin

#define SYSCFG_EXTICR3_EXTI11_PG   0x6000U

PG[11] pin

#define SYSCFG_EXTICR3_EXTI11_PH   0x7000U

PH[11] pin

#define SYSCFG_EXTICR3_EXTI11_PI   0x8000U

PI[11] pin

#define SYSCFG_EXTICR3_EXTI11_PJ   0x9000U

PJ[11] pin

#define SYSCFG_EXTICR3_EXTI8   0x000FU

EXTI 8 configuration

#define SYSCFG_EXTICR3_EXTI8_PA   0x0000U

EXTI8 configuration.

PA[8] pin

#define SYSCFG_EXTICR3_EXTI8_PB   0x0001U

PB[8] pin

#define SYSCFG_EXTICR3_EXTI8_PC   0x0002U

PC[8] pin

#define SYSCFG_EXTICR3_EXTI8_PD   0x0003U

PD[8] pin

#define SYSCFG_EXTICR3_EXTI8_PE   0x0004U

PE[8] pin

#define SYSCFG_EXTICR3_EXTI8_PF   0x0005U

PF[8] pin

#define SYSCFG_EXTICR3_EXTI8_PG   0x0006U

PG[8] pin

#define SYSCFG_EXTICR3_EXTI8_PH   0x0007U

PH[8] pin

#define SYSCFG_EXTICR3_EXTI8_PI   0x0008U

PI[8] pin

#define SYSCFG_EXTICR3_EXTI8_PJ   0x0009U

PJ[8] pin

#define SYSCFG_EXTICR3_EXTI9   0x00F0U

EXTI 9 configuration

#define SYSCFG_EXTICR3_EXTI9_PA   0x0000U

EXTI9 configuration.

PA[9] pin

#define SYSCFG_EXTICR3_EXTI9_PB   0x0010U

PB[9] pin

#define SYSCFG_EXTICR3_EXTI9_PC   0x0020U

PC[9] pin

#define SYSCFG_EXTICR3_EXTI9_PD   0x0030U

PD[9] pin

#define SYSCFG_EXTICR3_EXTI9_PE   0x0040U

PE[9] pin

#define SYSCFG_EXTICR3_EXTI9_PF   0x0050U

PF[9] pin

#define SYSCFG_EXTICR3_EXTI9_PG   0x0060U

PG[9] pin

#define SYSCFG_EXTICR3_EXTI9_PH   0x0070U

PH[9] pin

#define SYSCFG_EXTICR3_EXTI9_PI   0x0080U

PI[9] pin

#define SYSCFG_EXTICR3_EXTI9_PJ   0x0090U

PJ[9] pin

#define SYSCFG_EXTICR4_EXTI12   0x000FU

EXTI 12 configuration

#define SYSCFG_EXTICR4_EXTI12_PA   0x0000U

EXTI12 configuration.

PA[12] pin

#define SYSCFG_EXTICR4_EXTI12_PB   0x0001U

PB[12] pin

#define SYSCFG_EXTICR4_EXTI12_PC   0x0002U

PC[12] pin

#define SYSCFG_EXTICR4_EXTI12_PD   0x0003U

PD[12] pin

#define SYSCFG_EXTICR4_EXTI12_PE   0x0004U

PE[12] pin

#define SYSCFG_EXTICR4_EXTI12_PF   0x0005U

PF[12] pin

#define SYSCFG_EXTICR4_EXTI12_PG   0x0006U

PG[12] pin

#define SYSCFG_EXTICR4_EXTI12_PH   0x0007U

PH[12] pin

#define SYSCFG_EXTICR4_EXTI12_PI   0x0008U

PI[12] pin

#define SYSCFG_EXTICR4_EXTI12_PJ   0x0009U

PJ[12] pin

#define SYSCFG_EXTICR4_EXTI13   0x00F0U

EXTI 13 configuration

#define SYSCFG_EXTICR4_EXTI13_PA   0x0000U

EXTI13 configuration.

PA[13] pin

#define SYSCFG_EXTICR4_EXTI13_PB   0x0010U

PB[13] pin

#define SYSCFG_EXTICR4_EXTI13_PC   0x0020U

PC[13] pin

#define SYSCFG_EXTICR4_EXTI13_PD   0x0030U

PD[13] pin

#define SYSCFG_EXTICR4_EXTI13_PE   0x0040U

PE[13] pin

#define SYSCFG_EXTICR4_EXTI13_PF   0x0050U

PF[13] pin

#define SYSCFG_EXTICR4_EXTI13_PG   0x0060U

PG[13] pin

#define SYSCFG_EXTICR4_EXTI13_PH   0x0070U

PH[13] pin

#define SYSCFG_EXTICR4_EXTI13_PI   0x0080U

PI[13] pin

#define SYSCFG_EXTICR4_EXTI13_PJ   0x0090U

PJ[13] pin

#define SYSCFG_EXTICR4_EXTI14   0x0F00U

EXTI 14 configuration

#define SYSCFG_EXTICR4_EXTI14_PA   0x0000U

EXTI14 configuration.

PA[14] pin

#define SYSCFG_EXTICR4_EXTI14_PB   0x0100U

PB[14] pin

#define SYSCFG_EXTICR4_EXTI14_PC   0x0200U

PC[14] pin

#define SYSCFG_EXTICR4_EXTI14_PD   0x0300U

PD[14] pin

#define SYSCFG_EXTICR4_EXTI14_PE   0x0400U

PE[14] pin

#define SYSCFG_EXTICR4_EXTI14_PF   0x0500U

PF[14] pin

#define SYSCFG_EXTICR4_EXTI14_PG   0x0600U

PG[14] pin

#define SYSCFG_EXTICR4_EXTI14_PH   0x0700U

PH[14] pin

#define SYSCFG_EXTICR4_EXTI14_PI   0x0800U

PI[14] pin

#define SYSCFG_EXTICR4_EXTI14_PJ   0x0900U

PJ[14] pin

#define SYSCFG_EXTICR4_EXTI15   0xF000U

EXTI 15 configuration

#define SYSCFG_EXTICR4_EXTI15_PA   0x0000U

EXTI15 configuration.

PA[15] pin

#define SYSCFG_EXTICR4_EXTI15_PB   0x1000U

PB[15] pin

#define SYSCFG_EXTICR4_EXTI15_PC   0x2000U

PC[15] pin

#define SYSCFG_EXTICR4_EXTI15_PD   0x3000U

PD[15] pin

#define SYSCFG_EXTICR4_EXTI15_PE   0x4000U

PE[15] pin

#define SYSCFG_EXTICR4_EXTI15_PF   0x5000U

PF[15] pin

#define SYSCFG_EXTICR4_EXTI15_PG   0x6000U

PG[15] pin

#define SYSCFG_EXTICR4_EXTI15_PH   0x7000U

PH[15] pin

#define SYSCFG_EXTICR4_EXTI15_PI   0x8000U

PI[15] pin

#define SYSCFG_EXTICR4_EXTI15_PJ   0x9000U

PJ[15] pin

#define SYSCFG_MEMRMP_MEM_BOOT   0x00000001U

Boot information after Reset

#define SYSCFG_MEMRMP_SWP_FMC   0x00000C00U

FMC Memory Mapping swapping

#define SYSCFG_MEMRMP_SWP_FMC_0   0x00000400U
#define SYSCFG_MEMRMP_SWP_FMC_1   0x00000800U
#define SYSCFG_PMC_ADC1DC2   0x00010000U

Refer to AN4073 on how to use this bit

#define SYSCFG_PMC_ADC2DC2   0x00020000U

Refer to AN4073 on how to use this bit

#define SYSCFG_PMC_ADC3DC2   0x00040000U

Refer to AN4073 on how to use this bit

#define SYSCFG_PMC_ADCxDC2   0x00070000U

Refer to AN4073 on how to use this bit

#define SYSCFG_PMC_MII_RMII_SEL   0x00800000U

Ethernet PHY interface selection

#define TIM_ARR_ARR   0xFFFFU

actual auto-reload Value

#define TIM_BDTR_AOE   0x00004000U

Automatic Output enable

#define TIM_BDTR_BK2E   0x01000000U

Break enable for Break2

#define TIM_BDTR_BK2F   0x00F00000U

Break Filter for Break2

#define TIM_BDTR_BK2P   0x02000000U

Break Polarity for Break2

#define TIM_BDTR_BKE   0x00001000U

Break enable

#define TIM_BDTR_BKF   0x000F0000U

Break Filter for Break1

#define TIM_BDTR_BKP   0x00002000U

Break Polarity

#define TIM_BDTR_DTG   0x000000FFU

DTG[0:7] bits (Dead-Time Generator set-up)

#define TIM_BDTR_DTG_0   0x00000001U

Bit 0

#define TIM_BDTR_DTG_1   0x00000002U

Bit 1

#define TIM_BDTR_DTG_2   0x00000004U

Bit 2

#define TIM_BDTR_DTG_3   0x00000008U

Bit 3

#define TIM_BDTR_DTG_4   0x00000010U

Bit 4

#define TIM_BDTR_DTG_5   0x00000020U

Bit 5

#define TIM_BDTR_DTG_6   0x00000040U

Bit 6

#define TIM_BDTR_DTG_7   0x00000080U

Bit 7

#define TIM_BDTR_LOCK   0x00000300U

LOCK[1:0] bits (Lock Configuration)

#define TIM_BDTR_LOCK_0   0x00000100U

Bit 0

#define TIM_BDTR_LOCK_1   0x00000200U

Bit 1

#define TIM_BDTR_MOE   0x00008000U

Main Output enable

#define TIM_BDTR_OSSI   0x00000400U

Off-State Selection for Idle mode

#define TIM_BDTR_OSSR   0x00000800U

Off-State Selection for Run mode

#define TIM_CCER_CC1E   0x00000001U

Capture/Compare 1 output enable

#define TIM_CCER_CC1NE   0x00000004U

Capture/Compare 1 Complementary output enable

#define TIM_CCER_CC1NP   0x00000008U

Capture/Compare 1 Complementary output Polarity

#define TIM_CCER_CC1P   0x00000002U

Capture/Compare 1 output Polarity

#define TIM_CCER_CC2E   0x00000010U

Capture/Compare 2 output enable

#define TIM_CCER_CC2NE   0x00000040U

Capture/Compare 2 Complementary output enable

#define TIM_CCER_CC2NP   0x00000080U

Capture/Compare 2 Complementary output Polarity

#define TIM_CCER_CC2P   0x00000020U

Capture/Compare 2 output Polarity

#define TIM_CCER_CC3E   0x00000100U

Capture/Compare 3 output enable

#define TIM_CCER_CC3NE   0x00000400U

Capture/Compare 3 Complementary output enable

#define TIM_CCER_CC3NP   0x00000800U

Capture/Compare 3 Complementary output Polarity

#define TIM_CCER_CC3P   0x00000200U

Capture/Compare 3 output Polarity

#define TIM_CCER_CC4E   0x00001000U

Capture/Compare 4 output enable

#define TIM_CCER_CC4NP   0x00008000U

Capture/Compare 4 Complementary output Polarity

#define TIM_CCER_CC4P   0x00002000U

Capture/Compare 4 output Polarity

#define TIM_CCER_CC5E   0x00010000U

Capture/Compare 5 output enable

#define TIM_CCER_CC5P   0x00020000U

Capture/Compare 5 output Polarity

#define TIM_CCER_CC6E   0x00100000U

Capture/Compare 6 output enable

#define TIM_CCER_CC6P   0x00200000U

Capture/Compare 6 output Polarity

#define TIM_CCMR1_CC1S   0x00000003U

CC1S[1:0] bits (Capture/Compare 1 Selection)

#define TIM_CCMR1_CC1S_0   0x00000001U

Bit 0

#define TIM_CCMR1_CC1S_1   0x00000002U

Bit 1

#define TIM_CCMR1_CC2S   0x00000300U

CC2S[1:0] bits (Capture/Compare 2 Selection)

#define TIM_CCMR1_CC2S_0   0x00000100U

Bit 0

#define TIM_CCMR1_CC2S_1   0x00000200U

Bit 1

#define TIM_CCMR1_IC1F   0x00F0U

IC1F[3:0] bits (Input Capture 1 Filter)

#define TIM_CCMR1_IC1F_0   0x0010U

Bit 0

#define TIM_CCMR1_IC1F_1   0x0020U

Bit 1

#define TIM_CCMR1_IC1F_2   0x0040U

Bit 2

#define TIM_CCMR1_IC1F_3   0x0080U

Bit 3

#define TIM_CCMR1_IC1PSC   0x000CU

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

#define TIM_CCMR1_IC1PSC_0   0x0004U

Bit 0

#define TIM_CCMR1_IC1PSC_1   0x0008U

Bit 1

#define TIM_CCMR1_IC2F   0xF000U

IC2F[3:0] bits (Input Capture 2 Filter)

#define TIM_CCMR1_IC2F_0   0x1000U

Bit 0

#define TIM_CCMR1_IC2F_1   0x2000U

Bit 1

#define TIM_CCMR1_IC2F_2   0x4000U

Bit 2

#define TIM_CCMR1_IC2F_3   0x8000U

Bit 3

#define TIM_CCMR1_IC2PSC   0x0C00U

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

#define TIM_CCMR1_IC2PSC_0   0x0400U

Bit 0

#define TIM_CCMR1_IC2PSC_1   0x0800U

Bit 1

#define TIM_CCMR1_OC1CE   0x00000080U

Output Compare 1Clear Enable

#define TIM_CCMR1_OC1FE   0x00000004U

Output Compare 1 Fast enable

#define TIM_CCMR1_OC1M   0x00010070U

OC1M[2:0] bits (Output Compare 1 Mode)

#define TIM_CCMR1_OC1M_0   0x00000010U

Bit 0

#define TIM_CCMR1_OC1M_1   0x00000020U

Bit 1

#define TIM_CCMR1_OC1M_2   0x00000040U

Bit 2

#define TIM_CCMR1_OC1M_3   0x00010000U

Bit 3

#define TIM_CCMR1_OC1PE   0x00000008U

Output Compare 1 Preload enable

#define TIM_CCMR1_OC2CE   0x00008000U

Output Compare 2 Clear Enable

#define TIM_CCMR1_OC2FE   0x00000400U

Output Compare 2 Fast enable

#define TIM_CCMR1_OC2M   0x01007000U

OC2M[2:0] bits (Output Compare 2 Mode)

#define TIM_CCMR1_OC2M_0   0x00001000U

Bit 0

#define TIM_CCMR1_OC2M_1   0x00002000U

Bit 1

#define TIM_CCMR1_OC2M_2   0x00004000U

Bit 2

#define TIM_CCMR1_OC2M_3   0x01000000U

Bit 3

#define TIM_CCMR1_OC2PE   0x00000800U

Output Compare 2 Preload enable

#define TIM_CCMR2_CC3S   0x00000003U

CC3S[1:0] bits (Capture/Compare 3 Selection)

#define TIM_CCMR2_CC3S_0   0x00000001U

Bit 0

#define TIM_CCMR2_CC3S_1   0x00000002U

Bit 1

#define TIM_CCMR2_CC4S   0x00000300U

CC4S[1:0] bits (Capture/Compare 4 Selection)

#define TIM_CCMR2_CC4S_0   0x00000100U

Bit 0

#define TIM_CCMR2_CC4S_1   0x00000200U

Bit 1

#define TIM_CCMR2_IC3F   0x00F0U

IC3F[3:0] bits (Input Capture 3 Filter)

#define TIM_CCMR2_IC3F_0   0x0010U

Bit 0

#define TIM_CCMR2_IC3F_1   0x0020U

Bit 1

#define TIM_CCMR2_IC3F_2   0x0040U

Bit 2

#define TIM_CCMR2_IC3F_3   0x0080U

Bit 3

#define TIM_CCMR2_IC3PSC   0x000CU

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

#define TIM_CCMR2_IC3PSC_0   0x0004U

Bit 0

#define TIM_CCMR2_IC3PSC_1   0x0008U

Bit 1

#define TIM_CCMR2_IC4F   0xF000U

IC4F[3:0] bits (Input Capture 4 Filter)

#define TIM_CCMR2_IC4F_0   0x1000U

Bit 0

#define TIM_CCMR2_IC4F_1   0x2000U

Bit 1

#define TIM_CCMR2_IC4F_2   0x4000U

Bit 2

#define TIM_CCMR2_IC4F_3   0x8000U

Bit 3

#define TIM_CCMR2_IC4PSC   0x0C00U

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

#define TIM_CCMR2_IC4PSC_0   0x0400U

Bit 0

#define TIM_CCMR2_IC4PSC_1   0x0800U

Bit 1

#define TIM_CCMR2_OC3CE   0x00000080U

Output Compare 3 Clear Enable

#define TIM_CCMR2_OC3FE   0x00000004U

Output Compare 3 Fast enable

#define TIM_CCMR2_OC3M   0x00010070U

OC3M[2:0] bits (Output Compare 3 Mode)

#define TIM_CCMR2_OC3M_0   0x00000010U

Bit 0

#define TIM_CCMR2_OC3M_1   0x00000020U

Bit 1

#define TIM_CCMR2_OC3M_2   0x00000040U

Bit 2

#define TIM_CCMR2_OC3M_3   0x00010000U

Bit 3

#define TIM_CCMR2_OC3PE   0x00000008U

Output Compare 3 Preload enable

#define TIM_CCMR2_OC4CE   0x8000U

Output Compare 4 Clear Enable

#define TIM_CCMR2_OC4FE   0x00000400U

Output Compare 4 Fast enable

#define TIM_CCMR2_OC4M   0x01007000U

OC4M[2:0] bits (Output Compare 4 Mode)

#define TIM_CCMR2_OC4M_0   0x00001000U

Bit 0

#define TIM_CCMR2_OC4M_1   0x00002000U

Bit 1

#define TIM_CCMR2_OC4M_2   0x00004000U

Bit 2

#define TIM_CCMR2_OC4M_3   0x01000000U

Bit 3

#define TIM_CCMR2_OC4PE   0x00000800U

Output Compare 4 Preload enable

#define TIM_CCMR3_OC5CE   0x00000080U

Output Compare 5 Clear Enable

#define TIM_CCMR3_OC5FE   0x00000004U

Output Compare 5 Fast enable

#define TIM_CCMR3_OC5M   0x00010070U

OC5M[2:0] bits (Output Compare 5 Mode)

#define TIM_CCMR3_OC5M_0   0x00000010U

Bit 0

#define TIM_CCMR3_OC5M_1   0x00000020U

Bit 1

#define TIM_CCMR3_OC5M_2   0x00000040U

Bit 2

#define TIM_CCMR3_OC5M_3   0x00010000U

Bit 3

#define TIM_CCMR3_OC5PE   0x00000008U

Output Compare 5 Preload enable

#define TIM_CCMR3_OC6CE   0x00008000U

Output Compare 4 Clear Enable

#define TIM_CCMR3_OC6FE   0x00000400U

Output Compare 4 Fast enable

#define TIM_CCMR3_OC6M   0x01007000U

OC4M[2:0] bits (Output Compare 4 Mode)

#define TIM_CCMR3_OC6M_0   0x00001000U

Bit 0

#define TIM_CCMR3_OC6M_1   0x00002000U

Bit 1

#define TIM_CCMR3_OC6M_2   0x00004000U

Bit 2

#define TIM_CCMR3_OC6M_3   0x01000000U

Bit 3

#define TIM_CCMR3_OC6PE   0x00000800U

Output Compare 4 Preload enable

#define TIM_CCR1_CCR1   0xFFFFU

Capture/Compare 1 Value

#define TIM_CCR2_CCR2   0xFFFFU

Capture/Compare 2 Value

#define TIM_CCR3_CCR3   0xFFFFU

Capture/Compare 3 Value

#define TIM_CCR4_CCR4   0xFFFFU

Capture/Compare 4 Value

#define TIM_CCR5_CCR5   0xFFFFFFFFU

Capture/Compare 5 Value

#define TIM_CCR5_GC5C1   0x20000000U

Group Channel 5 and Channel 1

#define TIM_CCR5_GC5C2   0x40000000U

Group Channel 5 and Channel 2

#define TIM_CCR5_GC5C3   0x80000000U

Group Channel 5 and Channel 3

#define TIM_CCR6_CCR6   ((uint16_t)0xFFFFU)

Capture/Compare 6 Value

#define TIM_CNT_CNT   0xFFFFU

Counter Value

#define TIM_CR1_ARPE   0x0080U

Auto-reload preload enable

#define TIM_CR1_CEN   0x0001U

Counter enable

#define TIM_CR1_CKD   0x0300U

CKD[1:0] bits (clock division)

#define TIM_CR1_CKD_0   0x0100U

Bit 0

#define TIM_CR1_CKD_1   0x0200U

Bit 1

#define TIM_CR1_CMS   0x0060U

CMS[1:0] bits (Center-aligned mode selection)

#define TIM_CR1_CMS_0   0x0020U

Bit 0

#define TIM_CR1_CMS_1   0x0040U

Bit 1

#define TIM_CR1_DIR   0x0010U

Direction

#define TIM_CR1_OPM   0x0008U

One pulse mode

#define TIM_CR1_UDIS   0x0002U

Update disable

#define TIM_CR1_UIFREMAP   0x0800U

UIF status bit

#define TIM_CR1_URS   0x0004U

Update request source

#define TIM_CR2_CCDS   0x00000008U

Capture/Compare DMA Selection

#define TIM_CR2_CCPC   0x00000001U

Capture/Compare Preloaded Control

#define TIM_CR2_CCUS   0x00000004U

Capture/Compare Control Update Selection

#define TIM_CR2_MMS   0x0070U

MMS[2:0] bits (Master Mode Selection)

#define TIM_CR2_MMS2   0x00F00000U

MMS[2:0] bits (Master Mode Selection)

#define TIM_CR2_MMS2_0   0x00100000U

Bit 0

#define TIM_CR2_MMS2_1   0x00200000U

Bit 1

#define TIM_CR2_MMS2_2   0x00400000U

Bit 2

#define TIM_CR2_MMS2_3   0x00800000U

Bit 2

#define TIM_CR2_MMS_0   0x0010U

Bit 0

#define TIM_CR2_MMS_1   0x0020U

Bit 1

#define TIM_CR2_MMS_2   0x0040U

Bit 2

#define TIM_CR2_OIS1   0x0100U

Output Idle state 1 (OC1 output)

#define TIM_CR2_OIS1N   0x0200U

Output Idle state 1 (OC1N output)

#define TIM_CR2_OIS2   0x0400U

Output Idle state 2 (OC2 output)

#define TIM_CR2_OIS2N   0x0800U

Output Idle state 2 (OC2N output)

#define TIM_CR2_OIS3   0x1000U

Output Idle state 3 (OC3 output)

#define TIM_CR2_OIS3N   0x2000U

Output Idle state 3 (OC3N output)

#define TIM_CR2_OIS4   0x4000U

Output Idle state 4 (OC4 output)

#define TIM_CR2_OIS5   0x00010000U

Output Idle state 4 (OC4 output)

#define TIM_CR2_OIS6   0x00040000U

Output Idle state 4 (OC4 output)

#define TIM_CR2_TI1S   0x0080U

TI1 Selection

#define TIM_DCR_DBA   0x001FU

DBA[4:0] bits (DMA Base Address)

#define TIM_DCR_DBA_0   0x0001U

Bit 0

#define TIM_DCR_DBA_1   0x0002U

Bit 1

#define TIM_DCR_DBA_2   0x0004U

Bit 2

#define TIM_DCR_DBA_3   0x0008U

Bit 3

#define TIM_DCR_DBA_4   0x0010U

Bit 4

#define TIM_DCR_DBL   0x1F00U

DBL[4:0] bits (DMA Burst Length)

#define TIM_DCR_DBL_0   0x0100U

Bit 0

#define TIM_DCR_DBL_1   0x0200U

Bit 1

#define TIM_DCR_DBL_2   0x0400U

Bit 2

#define TIM_DCR_DBL_3   0x0800U

Bit 3

#define TIM_DCR_DBL_4   0x1000U

Bit 4

#define TIM_DIER_BIE   0x0080U

Break interrupt enable

#define TIM_DIER_CC1DE   0x0200U

Capture/Compare 1 DMA request enable

#define TIM_DIER_CC1IE   0x0002U

Capture/Compare 1 interrupt enable

#define TIM_DIER_CC2DE   0x0400U

Capture/Compare 2 DMA request enable

#define TIM_DIER_CC2IE   0x0004U

Capture/Compare 2 interrupt enable

#define TIM_DIER_CC3DE   0x0800U

Capture/Compare 3 DMA request enable

#define TIM_DIER_CC3IE   0x0008U

Capture/Compare 3 interrupt enable

#define TIM_DIER_CC4DE   0x1000U

Capture/Compare 4 DMA request enable

#define TIM_DIER_CC4IE   0x0010U

Capture/Compare 4 interrupt enable

#define TIM_DIER_COMDE   0x2000U

COM DMA request enable

#define TIM_DIER_COMIE   0x0020U

COM interrupt enable

#define TIM_DIER_TDE   0x4000U

Trigger DMA request enable

#define TIM_DIER_TIE   0x0040U

Trigger interrupt enable

#define TIM_DIER_UDE   0x0100U

Update DMA request enable

#define TIM_DIER_UIE   0x0001U

Update interrupt enable

#define TIM_DMAR_DMAB   0xFFFFU

DMA register for burst accesses

#define TIM_EGR_B2G   0x00000100U

Break2 Generation

#define TIM_EGR_BG   0x00000080U

Break Generation

#define TIM_EGR_CC1G   0x00000002U

Capture/Compare 1 Generation

#define TIM_EGR_CC2G   0x00000004U

Capture/Compare 2 Generation

#define TIM_EGR_CC3G   0x00000008U

Capture/Compare 3 Generation

#define TIM_EGR_CC4G   0x00000010U

Capture/Compare 4 Generation

#define TIM_EGR_COMG   0x00000020U

Capture/Compare Control Update Generation

#define TIM_EGR_TG   0x00000040U

Trigger Generation

#define TIM_EGR_UG   0x00000001U

Update Generation

#define TIM_OR_ITR1_RMP   0x0C00U

ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap)

#define TIM_OR_ITR1_RMP_0   0x0400U

Bit 0

#define TIM_OR_ITR1_RMP_1   0x0800U

Bit 1

#define TIM_OR_TI4_RMP   0x00C0U

TI4_RMP[1:0] bits (TIM5 Input 4 remap)

#define TIM_OR_TI4_RMP_0   0x0040U

Bit 0

#define TIM_OR_TI4_RMP_1   0x0080U

Bit 1

#define TIM_PSC_PSC   0xFFFFU

Prescaler Value

#define TIM_RCR_REP   ((uint8_t)0xFFU)

Repetition Counter Value

#define TIM_SMCR_ECE   0x4000U

External clock enable

#define TIM_SMCR_ETF   0x0F00U

ETF[3:0] bits (External trigger filter)

#define TIM_SMCR_ETF_0   0x0100U

Bit 0

#define TIM_SMCR_ETF_1   0x0200U

Bit 1

#define TIM_SMCR_ETF_2   0x0400U

Bit 2

#define TIM_SMCR_ETF_3   0x0800U

Bit 3

#define TIM_SMCR_ETP   0x8000U

External trigger polarity

#define TIM_SMCR_ETPS   0x3000U

ETPS[1:0] bits (External trigger prescaler)

#define TIM_SMCR_ETPS_0   0x1000U

Bit 0

#define TIM_SMCR_ETPS_1   0x2000U

Bit 1

#define TIM_SMCR_MSM   0x0080U

Master/slave mode

#define TIM_SMCR_OCCS   0x00000008U

OCREF clear selection

#define TIM_SMCR_SMS   0x00010007U

SMS[2:0] bits (Slave mode selection)

#define TIM_SMCR_SMS_0   0x00000001U

Bit 0

#define TIM_SMCR_SMS_1   0x00000002U

Bit 1

#define TIM_SMCR_SMS_2   0x00000004U

Bit 2

#define TIM_SMCR_SMS_3   0x00010000U

Bit 3

#define TIM_SMCR_TS   0x0070U

TS[2:0] bits (Trigger selection)

#define TIM_SMCR_TS_0   0x0010U

Bit 0

#define TIM_SMCR_TS_1   0x0020U

Bit 1

#define TIM_SMCR_TS_2   0x0040U

Bit 2

#define TIM_SR_B2IF   0x0100U

Break2 interrupt Flag

#define TIM_SR_BIF   0x0080U

Break interrupt Flag

#define TIM_SR_CC1IF   0x0002U

Capture/Compare 1 interrupt Flag

#define TIM_SR_CC1OF   0x0200U

Capture/Compare 1 Overcapture Flag

#define TIM_SR_CC2IF   0x0004U

Capture/Compare 2 interrupt Flag

#define TIM_SR_CC2OF   0x0400U

Capture/Compare 2 Overcapture Flag

#define TIM_SR_CC3IF   0x0008U

Capture/Compare 3 interrupt Flag

#define TIM_SR_CC3OF   0x0800U

Capture/Compare 3 Overcapture Flag

#define TIM_SR_CC4IF   0x0010U

Capture/Compare 4 interrupt Flag

#define TIM_SR_CC4OF   0x1000U

Capture/Compare 4 Overcapture Flag

#define TIM_SR_COMIF   0x0020U

COM interrupt Flag

#define TIM_SR_TIF   0x0040U

Trigger interrupt Flag

#define TIM_SR_UIF   0x0001U

Update interrupt Flag

#define USART_BRR_DIV_FRACTION   0x000FU

Fraction of USARTDIV

#define USART_BRR_DIV_MANTISSA   0xFFF0U

Mantissa of USARTDIV

#define USART_CR1_CMIE   0x00004000U

Character match interrupt enable

#define USART_CR1_DEAT   0x03E00000U

DEAT[4:0] bits (Driver Enable Assertion Time)

#define USART_CR1_DEAT_0   0x00200000U

Bit 0

#define USART_CR1_DEAT_1   0x00400000U

Bit 1

#define USART_CR1_DEAT_2   0x00800000U

Bit 2

#define USART_CR1_DEAT_3   0x01000000U

Bit 3

#define USART_CR1_DEAT_4   0x02000000U

Bit 4

#define USART_CR1_DEDT   0x001F0000U

DEDT[4:0] bits (Driver Enable Deassertion Time)

#define USART_CR1_DEDT_0   0x00010000U

Bit 0

#define USART_CR1_DEDT_1   0x00020000U

Bit 1

#define USART_CR1_DEDT_2   0x00040000U

Bit 2

#define USART_CR1_DEDT_3   0x00080000U

Bit 3

#define USART_CR1_DEDT_4   0x00100000U

Bit 4

#define USART_CR1_EOBIE   0x08000000U

End of Block interrupt enable

#define USART_CR1_IDLEIE   0x00000010U

IDLE Interrupt Enable

#define USART_CR1_M   0x10001000U

Word length

#define USART_CR1_M_0   0x00001000U

Word length - Bit 0

#define USART_CR1_M_1   0x10000000U

Word length - Bit 1

#define USART_CR1_MME   0x00002000U

Mute Mode Enable

#define USART_CR1_OVER8   0x00008000U

Oversampling by 8-bit or 16-bit mode

#define USART_CR1_PCE   0x00000400U

Parity Control Enable

#define USART_CR1_PEIE   0x00000100U

PE Interrupt Enable

#define USART_CR1_PS   0x00000200U

Parity Selection

#define USART_CR1_RE   0x00000004U

Receiver Enable

#define USART_CR1_RTOIE   0x04000000U

Receive Time Out interrupt enable

#define USART_CR1_RXNEIE   0x00000020U

RXNE Interrupt Enable

#define USART_CR1_TCIE   0x00000040U

Transmission Complete Interrupt Enable

#define USART_CR1_TE   0x00000008U

Transmitter Enable

#define USART_CR1_TXEIE   0x00000080U

TXE Interrupt Enable

#define USART_CR1_UE   0x00000001U

USART Enable

#define USART_CR1_WAKE   0x00000800U

Receiver Wakeup method

#define USART_CR2_ABREN   0x00100000U

Auto Baud-Rate Enable

#define USART_CR2_ABRMODE   0x00600000U

ABRMOD[1:0] bits (Auto Baud-Rate Mode)

#define USART_CR2_ABRMODE_0   0x00200000U

Bit 0

#define USART_CR2_ABRMODE_1   0x00400000U

Bit 1

#define USART_CR2_ADD   0xFF000000U

Address of the USART node

#define USART_CR2_ADDM7   0x00000010U

7-bit or 4-bit Address Detection

#define USART_CR2_CLKEN   0x00000800U

Clock Enable

#define USART_CR2_CPHA   0x00000200U

Clock Phase

#define USART_CR2_CPOL   0x00000400U

Clock Polarity

#define USART_CR2_DATAINV   0x00040000U

Binary data inversion

#define USART_CR2_LBCL   0x00000100U

Last Bit Clock pulse

#define USART_CR2_LBDIE   0x00000040U

LIN Break Detection Interrupt Enable

#define USART_CR2_LBDL   0x00000020U

LIN Break Detection Length

#define USART_CR2_LINEN   0x00004000U

LIN mode enable

#define USART_CR2_MSBFIRST   0x00080000U

Most Significant Bit First

#define USART_CR2_RTOEN   0x00800000U

Receiver Time-Out enable

#define USART_CR2_RXINV   0x00010000U

RX pin active level inversion

#define USART_CR2_STOP   0x00003000U

STOP[1:0] bits (STOP bits)

#define USART_CR2_STOP_0   0x00001000U

Bit 0

#define USART_CR2_STOP_1   0x00002000U

Bit 1

#define USART_CR2_SWAP   0x00008000U

SWAP TX/RX pins

#define USART_CR2_TXINV   0x00020000U

TX pin active level inversion

#define USART_CR3_CTSE   0x00000200U

CTS Enable

#define USART_CR3_CTSIE   0x00000400U

CTS Interrupt Enable

#define USART_CR3_DDRE   0x00002000U

DMA Disable on Reception Error

#define USART_CR3_DEM   0x00004000U

Driver Enable Mode

#define USART_CR3_DEP   0x00008000U

Driver Enable Polarity Selection

#define USART_CR3_DMAR   0x00000040U

DMA Enable Receiver

#define USART_CR3_DMAT   0x00000080U

DMA Enable Transmitter

#define USART_CR3_EIE   0x00000001U

Error Interrupt Enable

#define USART_CR3_HDSEL   0x00000008U

Half-Duplex Selection

#define USART_CR3_IREN   0x00000002U

IrDA mode Enable

#define USART_CR3_IRLP   0x00000004U

IrDA Low-Power

#define USART_CR3_NACK   0x00000010U

SmartCard NACK enable

#define USART_CR3_ONEBIT   0x00000800U

One sample bit method enable

#define USART_CR3_OVRDIS   0x00001000U

Overrun Disable

#define USART_CR3_RTSE   0x00000100U

RTS Enable

#define USART_CR3_SCARCNT   0x000E0000U

SCARCNT[2:0] bits (SmartCard Auto-Retry Count)

#define USART_CR3_SCARCNT_0   0x00020000U

Bit 0

#define USART_CR3_SCARCNT_1   0x00040000U

Bit 1

#define USART_CR3_SCARCNT_2   0x00080000U

Bit 2

#define USART_CR3_SCEN   0x00000020U

SmartCard mode enable

#define USART_GTPR_GT   0xFF00U

GT[7:0] bits (Guard time value)

#define USART_GTPR_PSC   0x00FFU

PSC[7:0] bits (Prescaler value)

#define USART_ICR_CMCF   0x00020000U

Character Match Clear Flag

#define USART_ICR_CTSCF   0x00000200U

CTS Interrupt Clear Flag

#define USART_ICR_EOBCF   0x00001000U

End Of Block Clear Flag

#define USART_ICR_FECF   0x00000002U

Framing Error Clear Flag

#define USART_ICR_IDLECF   0x00000010U

IDLE line detected Clear Flag

#define USART_ICR_LBDCF   0x00000100U

LIN Break Detection Clear Flag

#define USART_ICR_NCF   0x00000004U

Noise detected Clear Flag

#define USART_ICR_ORECF   0x00000008U

OverRun Error Clear Flag

#define USART_ICR_PECF   0x00000001U

Parity Error Clear Flag

#define USART_ICR_RTOCF   0x00000800U

Receiver Time Out Clear Flag

#define USART_ICR_TCCF   0x00000040U

Transmission Complete Clear Flag

#define USART_ICR_WUCF   0x00100000U

Wake Up from stop mode Clear Flag

#define USART_ISR_ABRE   0x00004000U

Auto-Baud Rate Error

#define USART_ISR_ABRF   0x00008000U

Auto-Baud Rate Flag

#define USART_ISR_BUSY   0x00010000U

Busy Flag

#define USART_ISR_CMF   0x00020000U

Character Match Flag

#define USART_ISR_CTS   0x00000400U

CTS flag

#define USART_ISR_CTSIF   0x00000200U

CTS interrupt flag

#define USART_ISR_EOBF   0x00001000U

End Of Block Flag

#define USART_ISR_FE   0x00000002U

Framing Error

#define USART_ISR_IDLE   0x00000010U

IDLE line detected

#define USART_ISR_LBD   USART_ISR_LBDF
#define USART_ISR_LBDF   0x00000100U

LIN Break Detection Flag

#define USART_ISR_NE   0x00000004U

Noise detected Flag

#define USART_ISR_ORE   0x00000008U

OverRun Error

#define USART_ISR_PE   0x00000001U

Parity Error

#define USART_ISR_REACK   0x00400000U

Receive Enable Acknowledge Flag

#define USART_ISR_RTOF   0x00000800U

Receiver Time Out

#define USART_ISR_RWU   0x00080000U

Receive Wake Up from mute mode Flag

#define USART_ISR_RXNE   0x00000020U

Read Data Register Not Empty

#define USART_ISR_SBKF   0x00040000U

Send Break Flag

#define USART_ISR_TC   0x00000040U

Transmission Complete

#define USART_ISR_TEACK   0x00200000U

Transmit Enable Acknowledge Flag

#define USART_ISR_TXE   0x00000080U

Transmit Data Register Empty

#define USART_ISR_WUF   0x00100000U

Wake Up from stop mode Flag

#define USART_RDR_RDR   0x01FFU

RDR[8:0] bits (Receive Data value)

#define USART_RQR_ABRRQ   0x0001U

Auto-Baud Rate Request

#define USART_RQR_MMRQ   0x0004U

Mute Mode Request

#define USART_RQR_RXFRQ   0x0008U

Receive Data flush Request

#define USART_RQR_SBKRQ   0x0002U

Send Break Request

#define USART_RQR_TXFRQ   0x0010U

Transmit data flush Request

#define USART_RTOR_BLEN   0xFF000000U

Block Length

#define USART_RTOR_RTO   0x00FFFFFFU

Receiver Time Out Value

#define USART_TDR_TDR   0x01FFU

TDR[8:0] bits (Transmit Data value)

#define USB_OTG_BCNT   0x00007FF0U

Byte count

#define USB_OTG_BCNT   0x00007FF0U

Byte count

#define USB_OTG_CHNUM   0x0000000FU

Channel number

#define USB_OTG_CHNUM   0x0000000FU

Channel number

#define USB_OTG_CHNUM_0   0x00000001U

Bit 0

#define USB_OTG_CHNUM_0   0x00000001U

Bit 0

#define USB_OTG_CHNUM_1   0x00000002U

Bit 1

#define USB_OTG_CHNUM_1   0x00000002U

Bit 1

#define USB_OTG_CHNUM_2   0x00000004U

Bit 2

#define USB_OTG_CHNUM_2   0x00000004U

Bit 2

#define USB_OTG_CHNUM_3   0x00000008U

Bit 3

#define USB_OTG_CHNUM_3   0x00000008U

Bit 3

#define USB_OTG_CID_PRODUCT_ID   0xFFFFFFFFU

Product ID field

#define USB_OTG_DAINT_IEPINT   0x0000FFFFU

IN endpoint interrupt bits

#define USB_OTG_DAINT_OEPINT   0xFFFF0000U

OUT endpoint interrupt bits

#define USB_OTG_DAINTMSK_IEPM   0x0000FFFFU

IN EP interrupt mask bits

#define USB_OTG_DAINTMSK_OEPM   0xFFFF0000U

OUT EP interrupt mask bits

#define USB_OTG_DCFG_DAD   0x000007F0U

Device address

#define USB_OTG_DCFG_DAD_0   0x00000010U

Bit 0

#define USB_OTG_DCFG_DAD_1   0x00000020U

Bit 1

#define USB_OTG_DCFG_DAD_2   0x00000040U

Bit 2

#define USB_OTG_DCFG_DAD_3   0x00000080U

Bit 3

#define USB_OTG_DCFG_DAD_4   0x00000100U

Bit 4

#define USB_OTG_DCFG_DAD_5   0x00000200U

Bit 5

#define USB_OTG_DCFG_DAD_6   0x00000400U

Bit 6

#define USB_OTG_DCFG_DSPD   0x00000003U

Device speed

#define USB_OTG_DCFG_DSPD_0   0x00000001U

Bit 0

#define USB_OTG_DCFG_DSPD_1   0x00000002U

Bit 1

#define USB_OTG_DCFG_NZLSOHSK   0x00000004U

Nonzero-length status OUT handshake

#define USB_OTG_DCFG_PERSCHIVL   0x03000000U

Periodic scheduling interval

#define USB_OTG_DCFG_PERSCHIVL_0   0x01000000U

Bit 0

#define USB_OTG_DCFG_PERSCHIVL_1   0x02000000U

Bit 1

#define USB_OTG_DCFG_PFIVL   0x00001800U

Periodic (micro)frame interval

#define USB_OTG_DCFG_PFIVL_0   0x00000800U

Bit 0

#define USB_OTG_DCFG_PFIVL_1   0x00001000U

Bit 1

#define USB_OTG_DCTL_CGINAK   0x00000100U

Clear global IN NAK

#define USB_OTG_DCTL_CGONAK   0x00000400U

Clear global OUT NAK

#define USB_OTG_DCTL_GINSTS   0x00000004U

Global IN NAK status

#define USB_OTG_DCTL_GONSTS   0x00000008U

Global OUT NAK status

#define USB_OTG_DCTL_POPRGDNE   0x00000800U

Power-on programming done

#define USB_OTG_DCTL_RWUSIG   0x00000001U

Remote wakeup signaling

#define USB_OTG_DCTL_SDIS   0x00000002U

Soft disconnect

#define USB_OTG_DCTL_SGINAK   0x00000080U

Set global IN NAK

#define USB_OTG_DCTL_SGONAK   0x00000200U

Set global OUT NAK

#define USB_OTG_DCTL_TCTL   0x00000070U

Test control

#define USB_OTG_DCTL_TCTL_0   0x00000010U

Bit 0

#define USB_OTG_DCTL_TCTL_1   0x00000020U

Bit 1

#define USB_OTG_DCTL_TCTL_2   0x00000040U

Bit 2

#define USB_OTG_DEACHINT_IEP1INT   0x00000002U

IN endpoint 1interrupt bit

#define USB_OTG_DEACHINT_OEP1INT   0x00020000U

OUT endpoint 1 interrupt bit

#define USB_OTG_DEACHINTMSK_IEP1INTM   0x00000002U

IN Endpoint 1 interrupt mask bit

#define USB_OTG_DEACHINTMSK_OEP1INTM   0x00020000U

OUT Endpoint 1 interrupt mask bit

#define USB_OTG_DIEPCTL_CNAK   0x04000000U

Clear NAK

#define USB_OTG_DIEPCTL_EONUM_DPID   0x00010000U

Even/odd frame

#define USB_OTG_DIEPCTL_EPDIS   0x40000000U

Endpoint disable

#define USB_OTG_DIEPCTL_EPENA   0x80000000U

Endpoint enable

#define USB_OTG_DIEPCTL_EPTYP   0x000C0000U

Endpoint type

#define USB_OTG_DIEPCTL_EPTYP_0   0x00040000U

Bit 0

#define USB_OTG_DIEPCTL_EPTYP_1   0x00080000U

Bit 1

#define USB_OTG_DIEPCTL_MPSIZ   0x000007FFU

Maximum packet size

#define USB_OTG_DIEPCTL_NAKSTS   0x00020000U

NAK status

#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM   0x10000000U

Set DATA0 PID

#define USB_OTG_DIEPCTL_SNAK   0x08000000U

Set NAK

#define USB_OTG_DIEPCTL_SODDFRM   0x20000000U

Set odd frame

#define USB_OTG_DIEPCTL_STALL   0x00200000U

STALL handshake

#define USB_OTG_DIEPCTL_TXFNUM   0x03C00000U

TxFIFO number

#define USB_OTG_DIEPCTL_TXFNUM_0   0x00400000U

Bit 0

#define USB_OTG_DIEPCTL_TXFNUM_1   0x00800000U

Bit 1

#define USB_OTG_DIEPCTL_TXFNUM_2   0x01000000U

Bit 2

#define USB_OTG_DIEPCTL_TXFNUM_3   0x02000000U

Bit 3

#define USB_OTG_DIEPCTL_USBAEP   0x00008000U

USB active endpoint

#define USB_OTG_DIEPDMA_DMAADDR   0xFFFFFFFFU

DMA address

#define USB_OTG_DIEPEACHMSK1_BIM   0x00000200U

BNA interrupt mask

#define USB_OTG_DIEPEACHMSK1_EPDM   0x00000002U

Endpoint disabled interrupt mask

#define USB_OTG_DIEPEACHMSK1_INEPNEM   0x00000040U

IN endpoint NAK effective mask

#define USB_OTG_DIEPEACHMSK1_INEPNMM   0x00000020U

IN token received with EP mismatch mask

#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK   0x00000010U

IN token received when TxFIFO empty mask

#define USB_OTG_DIEPEACHMSK1_NAKM   0x00002000U

NAK interrupt mask

#define USB_OTG_DIEPEACHMSK1_TOM   0x00000008U

Timeout condition mask (nonisochronous endpoints)

#define USB_OTG_DIEPEACHMSK1_TXFURM   0x00000100U

FIFO underrun mask

#define USB_OTG_DIEPEACHMSK1_XFRCM   0x00000001U

Transfer completed interrupt mask

#define USB_OTG_DIEPEMPMSK_INEPTXFEM   0x0000FFFFU

IN EP Tx FIFO empty interrupt mask bits

#define USB_OTG_DIEPINT_BERR   0x00001000U

Babble error interrupt

#define USB_OTG_DIEPINT_BNA   0x00000200U

Buffer not available interrupt

#define USB_OTG_DIEPINT_EPDISD   0x00000002U

Endpoint disabled interrupt

#define USB_OTG_DIEPINT_INEPNE   0x00000040U

IN endpoint NAK effective

#define USB_OTG_DIEPINT_ITTXFE   0x00000010U

IN token received when TxFIFO is empty

#define USB_OTG_DIEPINT_NAK   0x00002000U

NAK interrupt

#define USB_OTG_DIEPINT_PKTDRPSTS   0x00000800U

Packet dropped status

#define USB_OTG_DIEPINT_TOC   0x00000008U

Timeout condition

#define USB_OTG_DIEPINT_TXFE   0x00000080U

Transmit FIFO empty

#define USB_OTG_DIEPINT_TXFIFOUDRN   0x00000100U

Transmit Fifo Underrun

#define USB_OTG_DIEPINT_XFRC   0x00000001U

Transfer completed interrupt

#define USB_OTG_DIEPMSK_BIM   0x00000200U

BNA interrupt mask

#define USB_OTG_DIEPMSK_EPDM   0x00000002U

Endpoint disabled interrupt mask

#define USB_OTG_DIEPMSK_INEPNEM   0x00000040U

IN endpoint NAK effective mask

#define USB_OTG_DIEPMSK_INEPNMM   0x00000020U

IN token received with EP mismatch mask

#define USB_OTG_DIEPMSK_ITTXFEMSK   0x00000010U

IN token received when TxFIFO empty mask

#define USB_OTG_DIEPMSK_TOM   0x00000008U

Timeout condition mask (nonisochronous endpoints)

#define USB_OTG_DIEPMSK_TXFURM   0x00000100U

FIFO underrun mask

#define USB_OTG_DIEPMSK_XFRCM   0x00000001U

Transfer completed interrupt mask

#define USB_OTG_DIEPTSIZ_MULCNT   0x60000000U

Packet count

#define USB_OTG_DIEPTSIZ_PKTCNT   0x1FF80000U

Packet count

#define USB_OTG_DIEPTSIZ_XFRSIZ   0x0007FFFFU

Transfer size

#define USB_OTG_DIEPTXF_INEPTXFD   0xFFFF0000U

IN endpoint TxFIFO depth

#define USB_OTG_DIEPTXF_INEPTXSA   0x0000FFFFU

IN endpoint FIFOx transmit RAM start address

#define USB_OTG_DOEPCTL_CNAK   0x04000000U

Clear NAK

#define USB_OTG_DOEPCTL_EPDIS   0x40000000U

Endpoint disable

#define USB_OTG_DOEPCTL_EPENA   0x80000000U

Endpoint enable

#define USB_OTG_DOEPCTL_EPTYP   0x000C0000U

Endpoint type

#define USB_OTG_DOEPCTL_EPTYP_0   0x00040000U

Bit 0

#define USB_OTG_DOEPCTL_EPTYP_1   0x00080000U

Bit 1

#define USB_OTG_DOEPCTL_MPSIZ   0x000007FFU /*!< Maximum packet size */

Bit 1

#define USB_OTG_DOEPCTL_NAKSTS   0x00020000U

NAK status

#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM   0x10000000U

Set DATA0 PID

#define USB_OTG_DOEPCTL_SNAK   0x08000000U

Set NAK

#define USB_OTG_DOEPCTL_SNPM   0x00100000U

Snoop mode

#define USB_OTG_DOEPCTL_SODDFRM   0x20000000U

Set odd frame

#define USB_OTG_DOEPCTL_STALL   0x00200000U

STALL handshake

#define USB_OTG_DOEPCTL_USBAEP   0x00008000U

USB active endpoint

#define USB_OTG_DOEPEACHMSK1_BERRM   0x00001000U

Bubble error interrupt mask

#define USB_OTG_DOEPEACHMSK1_BIM   0x00000200U

BNA interrupt mask

#define USB_OTG_DOEPEACHMSK1_EPDM   0x00000002U

Endpoint disabled interrupt mask

#define USB_OTG_DOEPEACHMSK1_INEPNEM   0x00000040U

IN endpoint NAK effective mask

#define USB_OTG_DOEPEACHMSK1_INEPNMM   0x00000020U

IN token received with EP mismatch mask

#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK   0x00000010U

IN token received when TxFIFO empty mask

#define USB_OTG_DOEPEACHMSK1_NAKM   0x00002000U

NAK interrupt mask

#define USB_OTG_DOEPEACHMSK1_NYETM   0x00004000U

NYET interrupt mask

#define USB_OTG_DOEPEACHMSK1_TOM   0x00000008U

Timeout condition mask

#define USB_OTG_DOEPEACHMSK1_TXFURM   0x00000100U

OUT packet error mask

#define USB_OTG_DOEPEACHMSK1_XFRCM   0x00000001U

Transfer completed interrupt mask

#define USB_OTG_DOEPINT_B2BSTUP   0x00000040U

Back-to-back SETUP packets received

#define USB_OTG_DOEPINT_EPDISD   0x00000002U

Endpoint disabled interrupt

#define USB_OTG_DOEPINT_NYET   0x00004000U

NYET interrupt

#define USB_OTG_DOEPINT_OTEPDIS   0x00000010U

OUT token received when endpoint disabled

#define USB_OTG_DOEPINT_OTEPSPR   0x00000020U

Status Phase Received For Control Write

#define USB_OTG_DOEPINT_STUP   0x00000008U

SETUP phase done

#define USB_OTG_DOEPINT_XFRC   0x00000001U

Transfer completed interrupt

#define USB_OTG_DOEPMSK_B2BSTUP   0x00000040U

Back-to-back SETUP packets received mask

#define USB_OTG_DOEPMSK_BOIM   0x00000200U

BNA interrupt mask

#define USB_OTG_DOEPMSK_EPDM   0x00000002U

Endpoint disabled interrupt mask

#define USB_OTG_DOEPMSK_OPEM   0x00000100U

OUT packet error mask

#define USB_OTG_DOEPMSK_OTEPDM   0x00000010U

OUT token received when endpoint disabled mask

#define USB_OTG_DOEPMSK_OTEPSPRM   0x00000020U

Status Phase Received mask

#define USB_OTG_DOEPMSK_STUPM   0x00000008U

SETUP phase done mask

#define USB_OTG_DOEPMSK_XFRCM   0x00000001U

Transfer completed interrupt mask

#define USB_OTG_DOEPTSIZ_PKTCNT   0x1FF80000U

Packet count

#define USB_OTG_DOEPTSIZ_STUPCNT   0x60000000U

SETUP packet count

#define USB_OTG_DOEPTSIZ_STUPCNT_0   0x20000000U

Bit 0

#define USB_OTG_DOEPTSIZ_STUPCNT_1   0x40000000U

Bit 1

#define USB_OTG_DOEPTSIZ_XFRSIZ   0x0007FFFFU

Transfer size

#define USB_OTG_DPID   0x00018000U

Data PID

#define USB_OTG_DPID   0x00018000U

Data PID

#define USB_OTG_DPID_0   0x00008000U

Bit 0

#define USB_OTG_DPID_0   0x00008000U

Bit 0

#define USB_OTG_DPID_1   0x00010000U

Bit 1

#define USB_OTG_DPID_1   0x00010000U

Bit 1

#define USB_OTG_DSTS_EERR   0x00000008U

Erratic error

#define USB_OTG_DSTS_ENUMSPD   0x00000006U

Enumerated speed

#define USB_OTG_DSTS_ENUMSPD_0   0x00000002U

Bit 0

#define USB_OTG_DSTS_ENUMSPD_1   0x00000004U

Bit 1

#define USB_OTG_DSTS_FNSOF   0x003FFF00U

Frame number of the received SOF

#define USB_OTG_DSTS_SUSPSTS   0x00000001U

Suspend status

#define USB_OTG_DTHRCTL_ARPEN   0x08000000U

Arbiter parking enable

#define USB_OTG_DTHRCTL_ISOTHREN   0x00000002U

ISO IN endpoint threshold enable

#define USB_OTG_DTHRCTL_NONISOTHREN   0x00000001U

Nonisochronous IN endpoints threshold enable

#define USB_OTG_DTHRCTL_RXTHREN   0x00010000U

Receive threshold enable

#define USB_OTG_DTHRCTL_RXTHRLEN   0x03FE0000U

Receive threshold length

#define USB_OTG_DTHRCTL_RXTHRLEN_0   0x00020000U

Bit 0

#define USB_OTG_DTHRCTL_RXTHRLEN_1   0x00040000U

Bit 1

#define USB_OTG_DTHRCTL_RXTHRLEN_2   0x00080000U

Bit 2

#define USB_OTG_DTHRCTL_RXTHRLEN_3   0x00100000U

Bit 3

#define USB_OTG_DTHRCTL_RXTHRLEN_4   0x00200000U

Bit 4

#define USB_OTG_DTHRCTL_RXTHRLEN_5   0x00400000U

Bit 5

#define USB_OTG_DTHRCTL_RXTHRLEN_6   0x00800000U

Bit 6

#define USB_OTG_DTHRCTL_RXTHRLEN_7   0x01000000U

Bit 7

#define USB_OTG_DTHRCTL_RXTHRLEN_8   0x02000000U

Bit 8

#define USB_OTG_DTHRCTL_TXTHRLEN   0x000007FCU

Transmit threshold length

#define USB_OTG_DTHRCTL_TXTHRLEN_0   0x00000004U

Bit 0

#define USB_OTG_DTHRCTL_TXTHRLEN_1   0x00000008U

Bit 1

#define USB_OTG_DTHRCTL_TXTHRLEN_2   0x00000010U

Bit 2

#define USB_OTG_DTHRCTL_TXTHRLEN_3   0x00000020U

Bit 3

#define USB_OTG_DTHRCTL_TXTHRLEN_4   0x00000040U

Bit 4

#define USB_OTG_DTHRCTL_TXTHRLEN_5   0x00000080U

Bit 5

#define USB_OTG_DTHRCTL_TXTHRLEN_6   0x00000100U

Bit 6

#define USB_OTG_DTHRCTL_TXTHRLEN_7   0x00000200U

Bit 7

#define USB_OTG_DTHRCTL_TXTHRLEN_8   0x00000400U

Bit 8

#define USB_OTG_DTXFSTS_INEPTFSAV   0x0000FFFFU

IN endpoint TxFIFO space available

#define USB_OTG_DVBUSDIS_VBUSDT   0x0000FFFFU

Device VBUS discharge time

#define USB_OTG_DVBUSPULSE_DVBUSP   0x00000FFFU

Device VBUS pulsing time

#define USB_OTG_EPNUM   0x0000000FU

Endpoint number

#define USB_OTG_EPNUM   0x0000000FU

Endpoint number

#define USB_OTG_EPNUM_0   0x00000001U

Bit 0

#define USB_OTG_EPNUM_0   0x00000001U

Bit 0

#define USB_OTG_EPNUM_1   0x00000002U

Bit 1

#define USB_OTG_EPNUM_1   0x00000002U

Bit 1

#define USB_OTG_EPNUM_2   0x00000004U

Bit 2

#define USB_OTG_EPNUM_2   0x00000004U

Bit 2

#define USB_OTG_EPNUM_3   0x00000008U

Bit 3

#define USB_OTG_EPNUM_3   0x00000008U

Bit 3

#define USB_OTG_FRMNUM   0x01E00000U

Frame number

#define USB_OTG_FRMNUM   0x01E00000U

Frame number

#define USB_OTG_FRMNUM_0   0x00200000U

Bit 0

#define USB_OTG_FRMNUM_0   0x00200000U

Bit 0

#define USB_OTG_FRMNUM_1   0x00400000U

Bit 1

#define USB_OTG_FRMNUM_1   0x00400000U

Bit 1

#define USB_OTG_FRMNUM_2   0x00800000U

Bit 2

#define USB_OTG_FRMNUM_2   0x00800000U

Bit 2

#define USB_OTG_FRMNUM_3   0x01000000U

Bit 3

#define USB_OTG_FRMNUM_3   0x01000000U

Bit 3

#define USB_OTG_GAHBCFG_DMAEN   0x00000020U

DMA enable

#define USB_OTG_GAHBCFG_GINT   0x00000001U

Global interrupt mask

#define USB_OTG_GAHBCFG_HBSTLEN   0x0000001EU

Burst length/type

#define USB_OTG_GAHBCFG_HBSTLEN_0   0x00000002U

Bit 0

#define USB_OTG_GAHBCFG_HBSTLEN_1   0x00000004U

Bit 1

#define USB_OTG_GAHBCFG_HBSTLEN_2   0x00000008U

Bit 2

#define USB_OTG_GAHBCFG_HBSTLEN_3   0x00000010U

Bit 3

#define USB_OTG_GAHBCFG_PTXFELVL   0x00000100U

Periodic TxFIFO empty level

#define USB_OTG_GAHBCFG_TXFELVL   0x00000080U

TxFIFO empty level

#define USB_OTG_GCCFG_PWRDWN   0x00010000U

Power down

#define USB_OTG_GCCFG_VBDEN   0x00200000U

USB VBUS Detection Enable

#define USB_OTG_GINTMSK_CIDSCHGM   0x10000000U

Connector ID status change mask

#define USB_OTG_GINTMSK_DISCINT   0x20000000U

Disconnect detected interrupt mask

#define USB_OTG_GINTMSK_ENUMDNEM   0x00002000U

Enumeration done mask

#define USB_OTG_GINTMSK_EOPFM   0x00008000U

End of periodic frame interrupt mask

#define USB_OTG_GINTMSK_EPMISM   0x00020000U

Endpoint mismatch interrupt mask

#define USB_OTG_GINTMSK_ESUSPM   0x00000400U

Early suspend mask

#define USB_OTG_GINTMSK_FSUSPM   0x00400000U

Data fetch suspended mask

#define USB_OTG_GINTMSK_GINAKEFFM   0x00000040U

Global nonperiodic IN NAK effective mask

#define USB_OTG_GINTMSK_GONAKEFFM   0x00000080U

Global OUT NAK effective mask

#define USB_OTG_GINTMSK_HCIM   0x02000000U

Host channels interrupt mask

#define USB_OTG_GINTMSK_IEPINT   0x00040000U

IN endpoints interrupt mask

#define USB_OTG_GINTMSK_IISOIXFRM   0x00100000U

Incomplete isochronous IN transfer mask

#define USB_OTG_GINTMSK_ISOODRPM   0x00004000U

Isochronous OUT packet dropped interrupt mask

#define USB_OTG_GINTMSK_LPMINTM   0x08000000U

LPM interrupt Mask

#define USB_OTG_GINTMSK_MMISM   0x00000002U

Mode mismatch interrupt mask

#define USB_OTG_GINTMSK_NPTXFEM   0x00000020U

Nonperiodic TxFIFO empty mask

#define USB_OTG_GINTMSK_OEPINT   0x00080000U

OUT endpoints interrupt mask

#define USB_OTG_GINTMSK_OTGINT   0x00000004U

OTG interrupt mask

#define USB_OTG_GINTMSK_PRTIM   0x01000000U

Host port interrupt mask

#define USB_OTG_GINTMSK_PTXFEM   0x04000000U

Periodic TxFIFO empty mask

#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM   0x00200000U

Incomplete periodic transfer mask

#define USB_OTG_GINTMSK_RSTDEM   0x00800000U

Reset detected interrupt mask

#define USB_OTG_GINTMSK_RXFLVLM   0x00000010U

Receive FIFO nonempty mask

#define USB_OTG_GINTMSK_SOFM   0x00000008U

Start of frame mask

#define USB_OTG_GINTMSK_SRQIM   0x40000000U

Session request/new session detected interrupt mask

#define USB_OTG_GINTMSK_USBRST   0x00001000U

USB reset mask

#define USB_OTG_GINTMSK_USBSUSPM   0x00000800U

USB suspend mask

#define USB_OTG_GINTMSK_WUIM   0x80000000U

Resume/remote wakeup detected interrupt mask

#define USB_OTG_GINTSTS_BOUTNAKEFF   0x00000080U

Global OUT NAK effective

#define USB_OTG_GINTSTS_CIDSCHG   0x10000000U

Connector ID status change

#define USB_OTG_GINTSTS_CMOD   0x00000001U

Current mode of operation

#define USB_OTG_GINTSTS_DATAFSUSP   0x00400000U

Data fetch suspended

#define USB_OTG_GINTSTS_DISCINT   0x20000000U

Disconnect detected interrupt

#define USB_OTG_GINTSTS_ENUMDNE   0x00002000U

Enumeration done

#define USB_OTG_GINTSTS_EOPF   0x00008000U

End of periodic frame interrupt

#define USB_OTG_GINTSTS_ESUSP   0x00000400U

Early suspend

#define USB_OTG_GINTSTS_GINAKEFF   0x00000040U

Global IN nonperiodic NAK effective

#define USB_OTG_GINTSTS_HCINT   0x02000000U

Host channels interrupt

#define USB_OTG_GINTSTS_HPRTINT   0x01000000U

Host port interrupt

#define USB_OTG_GINTSTS_IEPINT   0x00040000U

IN endpoint interrupt

#define USB_OTG_GINTSTS_IISOIXFR   0x00100000U

Incomplete isochronous IN transfer

#define USB_OTG_GINTSTS_ISOODRP   0x00004000U

Isochronous OUT packet dropped interrupt

#define USB_OTG_GINTSTS_LPMINT   0x08000000U

LPM interrupt

#define USB_OTG_GINTSTS_MMIS   0x00000002U

Mode mismatch interrupt

#define USB_OTG_GINTSTS_NPTXFE   0x00000020U

Nonperiodic TxFIFO empty

#define USB_OTG_GINTSTS_OEPINT   0x00080000U

OUT endpoint interrupt

#define USB_OTG_GINTSTS_OTGINT   0x00000004U

OTG interrupt

#define USB_OTG_GINTSTS_PTXFE   0x04000000U

Periodic TxFIFO empty

#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT   0x00200000U

Incomplete periodic transfer

#define USB_OTG_GINTSTS_RSTDET   0x00800000U

Reset detected interrupt

#define USB_OTG_GINTSTS_RXFLVL   0x00000010U

RxFIFO nonempty

#define USB_OTG_GINTSTS_SOF   0x00000008U

Start of frame

#define USB_OTG_GINTSTS_SRQINT   0x40000000U

Session request/new session detected interrupt

#define USB_OTG_GINTSTS_USBRST   0x00001000U

USB reset

#define USB_OTG_GINTSTS_USBSUSP   0x00000800U

USB suspend

#define USB_OTG_GINTSTS_WKUINT   0x80000000U

Resume/remote wakeup detected interrupt

#define USB_OTG_GLPMCFG_BESL   0x0000003CU

BESL value received with last ACKed LPM Token

#define USB_OTG_GLPMCFG_BESLTHRS   0x00000F00U

BESL threshold

#define USB_OTG_GLPMCFG_ENBESL   0x10000000U

Enable best effort service latency

#define USB_OTG_GLPMCFG_L1DSEN   0x00001000U

L1 deep sleep enable

#define USB_OTG_GLPMCFG_L1RSMOK   0x00010000U

Sleep State Resume OK

#define USB_OTG_GLPMCFG_L1SSEN   0x00000080U

L1 shallow sleep enable

#define USB_OTG_GLPMCFG_LPMACK   0x00000002U

LPM Token acknowledge enable

#define USB_OTG_GLPMCFG_LPMCHIDX   0x001E0000U

LPM Channel Index

#define USB_OTG_GLPMCFG_LPMEN   0x00000001U

LPM support enable

#define USB_OTG_GLPMCFG_LPMRCNT   0x00E00000U

LPM retry count

#define USB_OTG_GLPMCFG_LPMRCNTSTS   0x0E000000U

LPM retry count status

#define USB_OTG_GLPMCFG_LPMRSP   0x00006000U

LPM response

#define USB_OTG_GLPMCFG_REMWAKE   0x00000040U

bRemoteWake value received with last ACKed LPM Token

#define USB_OTG_GLPMCFG_SLPSTS   0x00008000U

Port sleep status

#define USB_OTG_GLPMCFG_SNDLPM   0x01000000U

Send LPM transaction

#define USB_OTG_GNPTXSTS_NPTQXSAV   0x00FF0000U

Nonperiodic transmit request queue space available

#define USB_OTG_GNPTXSTS_NPTQXSAV_0   0x00010000U

Bit 0

#define USB_OTG_GNPTXSTS_NPTQXSAV_1   0x00020000U

Bit 1

#define USB_OTG_GNPTXSTS_NPTQXSAV_2   0x00040000U

Bit 2

#define USB_OTG_GNPTXSTS_NPTQXSAV_3   0x00080000U

Bit 3

#define USB_OTG_GNPTXSTS_NPTQXSAV_4   0x00100000U

Bit 4

#define USB_OTG_GNPTXSTS_NPTQXSAV_5   0x00200000U

Bit 5

#define USB_OTG_GNPTXSTS_NPTQXSAV_6   0x00400000U

Bit 6

#define USB_OTG_GNPTXSTS_NPTQXSAV_7   0x00800000U

Bit 7

#define USB_OTG_GNPTXSTS_NPTXFSAV   0x0000FFFFU

Nonperiodic TxFIFO space available

#define USB_OTG_GNPTXSTS_NPTXQTOP   0x7F000000U

Top of the nonperiodic transmit request queue

#define USB_OTG_GNPTXSTS_NPTXQTOP_0   0x01000000U

Bit 0

#define USB_OTG_GNPTXSTS_NPTXQTOP_1   0x02000000U

Bit 1

#define USB_OTG_GNPTXSTS_NPTXQTOP_2   0x04000000U

Bit 2

#define USB_OTG_GNPTXSTS_NPTXQTOP_3   0x08000000U

Bit 3

#define USB_OTG_GNPTXSTS_NPTXQTOP_4   0x10000000U

Bit 4

#define USB_OTG_GNPTXSTS_NPTXQTOP_5   0x20000000U

Bit 5

#define USB_OTG_GNPTXSTS_NPTXQTOP_6   0x40000000U

Bit 6

#define USB_OTG_GOTGCTL_ASVLD   0x00040000U

A-session valid

#define USB_OTG_GOTGCTL_AVALOEN   0x00000010U

A-peripheral session valid override enable

#define USB_OTG_GOTGCTL_AVALOVAL   0x00000020U

A-peripheral session valid override value

#define USB_OTG_GOTGCTL_BSESVLD   0x00080000U

B-session valid

#define USB_OTG_GOTGCTL_BVALOEN   0x00000040U

B-peripheral session valid override enable

#define USB_OTG_GOTGCTL_BVALOVAL   0x00000080U

B-peripheral session valid override value

#define USB_OTG_GOTGCTL_CIDSTS   0x00010000U

Connector ID status

#define USB_OTG_GOTGCTL_DBCT   0x00020000U

Long/short debounce time

#define USB_OTG_GOTGCTL_DHNPEN   0x00000800U

Device HNP enabled

#define USB_OTG_GOTGCTL_EHEN   0x00001000U

Embedded host enable

#define USB_OTG_GOTGCTL_HNGSCS   0x00000100U

Host set HNP enable

#define USB_OTG_GOTGCTL_HNPRQ   0x00000200U

HNP request

#define USB_OTG_GOTGCTL_HSHNPEN   0x00000400U

Host set HNP enable

#define USB_OTG_GOTGCTL_OTGVER   0x00100000U

OTG version

#define USB_OTG_GOTGCTL_SRQ   0x00000002U

Session request

#define USB_OTG_GOTGCTL_SRQSCS   0x00000001U

Session request success

#define USB_OTG_GOTGCTL_VBVALOEN   0x00000004U

VBUS valid override enable

#define USB_OTG_GOTGCTL_VBVALOVAL   0x00000008U

VBUS valid override value

#define USB_OTG_GOTGINT_ADTOCHG   0x00040000U

A-device timeout change

#define USB_OTG_GOTGINT_DBCDNE   0x00080000U

Debounce done

#define USB_OTG_GOTGINT_HNGDET   0x00020000U

Host negotiation detected

#define USB_OTG_GOTGINT_HNSSCHG   0x00000200U

Host negotiation success status change

#define USB_OTG_GOTGINT_IDCHNG   0x00100000U

Change in ID pin input value

#define USB_OTG_GOTGINT_SEDET   0x00000004U

Session end detected

#define USB_OTG_GOTGINT_SRSSCHG   0x00000100U

Session request success status change

#define USB_OTG_GPWRDN_ADPIF   0x00800000U

ADP Interrupt flag

#define USB_OTG_GPWRDN_ADPMEN   0x00000001U

ADP module enable

#define USB_OTG_GRSTCTL_AHBIDL   0x80000000U

AHB master idle

#define USB_OTG_GRSTCTL_CSRST   0x00000001U

Core soft reset

#define USB_OTG_GRSTCTL_DMAREQ   0x40000000U

DMA request signal

#define USB_OTG_GRSTCTL_FCRST   0x00000004U

Host frame counter reset

#define USB_OTG_GRSTCTL_HSRST   0x00000002U

HCLK soft reset

#define USB_OTG_GRSTCTL_RXFFLSH   0x00000010U

RxFIFO flush

#define USB_OTG_GRSTCTL_TXFFLSH   0x00000020U

TxFIFO flush

#define USB_OTG_GRSTCTL_TXFNUM   0x000007C0U

TxFIFO number

#define USB_OTG_GRSTCTL_TXFNUM_0   0x00000040U

Bit 0

#define USB_OTG_GRSTCTL_TXFNUM_1   0x00000080U

Bit 1

#define USB_OTG_GRSTCTL_TXFNUM_2   0x00000100U

Bit 2

#define USB_OTG_GRSTCTL_TXFNUM_3   0x00000200U

Bit 3

#define USB_OTG_GRSTCTL_TXFNUM_4   0x00000400U

Bit 4

#define USB_OTG_GRXFSIZ_RXFD   0x0000FFFFU

RxFIFO depth

#define USB_OTG_GRXSTSP_BCNT   0x00007FF0U

OUT EP interrupt mask bits

#define USB_OTG_GRXSTSP_DPID   0x00018000U

OUT EP interrupt mask bits

#define USB_OTG_GRXSTSP_EPNUM   0x0000000FU

IN EP interrupt mask bits

#define USB_OTG_GRXSTSP_PKTSTS   0x001E0000U

OUT EP interrupt mask bits

#define USB_OTG_GUSBCFG_CTXPKT   0x80000000U

Corrupt Tx packet

#define USB_OTG_GUSBCFG_FDMOD   0x40000000U

Forced peripheral mode

#define USB_OTG_GUSBCFG_FHMOD   0x20000000U

Forced host mode

#define USB_OTG_GUSBCFG_HNPCAP   0x00000200U

HNP-capable

#define USB_OTG_GUSBCFG_PCCI   0x00800000U

Indicator complement

#define USB_OTG_GUSBCFG_PHYLPCS   0x00008000U

PHY Low-power clock select

#define USB_OTG_GUSBCFG_PHYSEL   0x00000040U

USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select

#define USB_OTG_GUSBCFG_PTCI   0x01000000U

Indicator pass through

#define USB_OTG_GUSBCFG_SRPCAP   0x00000100U

SRP-capable

#define USB_OTG_GUSBCFG_TOCAL   0x00000007U

FS timeout calibration

#define USB_OTG_GUSBCFG_TOCAL_0   0x00000001U

Bit 0

#define USB_OTG_GUSBCFG_TOCAL_1   0x00000002U

Bit 1

#define USB_OTG_GUSBCFG_TOCAL_2   0x00000004U

Bit 2

#define USB_OTG_GUSBCFG_TRDT   0x00003C00U

USB turnaround time

#define USB_OTG_GUSBCFG_TRDT_0   0x00000400U

Bit 0

#define USB_OTG_GUSBCFG_TRDT_1   0x00000800U

Bit 1

#define USB_OTG_GUSBCFG_TRDT_2   0x00001000U

Bit 2

#define USB_OTG_GUSBCFG_TRDT_3   0x00002000U

Bit 3

#define USB_OTG_GUSBCFG_TSDPS   0x00400000U

TermSel DLine pulsing selection

#define USB_OTG_GUSBCFG_ULPIAR   0x00040000U

ULPI Auto-resume

#define USB_OTG_GUSBCFG_ULPICSM   0x00080000U

ULPI Clock SuspendM

#define USB_OTG_GUSBCFG_ULPIEVBUSD   0x00100000U

ULPI External VBUS Drive

#define USB_OTG_GUSBCFG_ULPIEVBUSI   0x00200000U

ULPI external VBUS indicator

#define USB_OTG_GUSBCFG_ULPIFSLS   0x00020000U

ULPI FS/LS select

#define USB_OTG_GUSBCFG_ULPIIPD   0x02000000U

ULPI interface protect disable

#define USB_OTG_HAINT_HAINT   0x0000FFFFU

Channel interrupts

#define USB_OTG_HAINTMSK_HAINTM   0x0000FFFFU

Channel interrupt mask

#define USB_OTG_HCCHAR_CHDIS   0x40000000U

Channel disable

#define USB_OTG_HCCHAR_CHENA   0x80000000U

Channel enable

#define USB_OTG_HCCHAR_DAD   0x1FC00000U

Device address

#define USB_OTG_HCCHAR_DAD_0   0x00400000U

Bit 0

#define USB_OTG_HCCHAR_DAD_1   0x00800000U

Bit 1

#define USB_OTG_HCCHAR_DAD_2   0x01000000U

Bit 2

#define USB_OTG_HCCHAR_DAD_3   0x02000000U

Bit 3

#define USB_OTG_HCCHAR_DAD_4   0x04000000U

Bit 4

#define USB_OTG_HCCHAR_DAD_5   0x08000000U

Bit 5

#define USB_OTG_HCCHAR_DAD_6   0x10000000U

Bit 6

#define USB_OTG_HCCHAR_EPDIR   0x00008000U

Endpoint direction

#define USB_OTG_HCCHAR_EPNUM   0x00007800U

Endpoint number

#define USB_OTG_HCCHAR_EPNUM_0   0x00000800U

Bit 0

#define USB_OTG_HCCHAR_EPNUM_1   0x00001000U

Bit 1

#define USB_OTG_HCCHAR_EPNUM_2   0x00002000U

Bit 2

#define USB_OTG_HCCHAR_EPNUM_3   0x00004000U

Bit 3

#define USB_OTG_HCCHAR_EPTYP   0x000C0000U

Endpoint type

#define USB_OTG_HCCHAR_EPTYP_0   0x00040000U

Bit 0

#define USB_OTG_HCCHAR_EPTYP_1   0x00080000U

Bit 1

#define USB_OTG_HCCHAR_LSDEV   0x00020000U

Low-speed device

#define USB_OTG_HCCHAR_MC   0x00300000U

Multi Count (MC) / Error Count (EC)

#define USB_OTG_HCCHAR_MC_0   0x00100000U

Bit 0

#define USB_OTG_HCCHAR_MC_1   0x00200000U

Bit 1

#define USB_OTG_HCCHAR_MPSIZ   0x000007FFU

Maximum packet size

#define USB_OTG_HCCHAR_ODDFRM   0x20000000U

Odd frame

#define USB_OTG_HCDMA_DMAADDR   0xFFFFFFFFU

DMA address

#define USB_OTG_HCFG_FSLSPCS   0x00000003U

FS/LS PHY clock select

#define USB_OTG_HCFG_FSLSPCS_0   0x00000001U

Bit 0

#define USB_OTG_HCFG_FSLSPCS_1   0x00000002U

Bit 1

#define USB_OTG_HCFG_FSLSS   0x00000004U

FS- and LS-only support

#define USB_OTG_HCINT_ACK   0x00000020U

ACK response received/transmitted interrupt

#define USB_OTG_HCINT_AHBERR   0x00000004U

AHB error

#define USB_OTG_HCINT_BBERR   0x00000100U

Babble error

#define USB_OTG_HCINT_CHH   0x00000002U

Channel halted

#define USB_OTG_HCINT_DTERR   0x00000400U

Data toggle error

#define USB_OTG_HCINT_FRMOR   0x00000200U

Frame overrun

#define USB_OTG_HCINT_NAK   0x00000010U

NAK response received interrupt

#define USB_OTG_HCINT_NYET   0x00000040U

Response received interrupt

#define USB_OTG_HCINT_STALL   0x00000008U

STALL response received interrupt

#define USB_OTG_HCINT_TXERR   0x00000080U

Transaction error

#define USB_OTG_HCINT_XFRC   0x00000001U

Transfer completed

#define USB_OTG_HCINTMSK_ACKM   0x00000020U

ACK response received/transmitted interrupt mask

#define USB_OTG_HCINTMSK_AHBERR   0x00000004U

AHB error

#define USB_OTG_HCINTMSK_BBERRM   0x00000100U

Babble error mask

#define USB_OTG_HCINTMSK_CHHM   0x00000002U

Channel halted mask

#define USB_OTG_HCINTMSK_DTERRM   0x00000400U

Data toggle error mask

#define USB_OTG_HCINTMSK_FRMORM   0x00000200U

Frame overrun mask

#define USB_OTG_HCINTMSK_NAKM   0x00000010U

NAK response received interrupt mask

#define USB_OTG_HCINTMSK_NYET   0x00000040U

response received interrupt mask

#define USB_OTG_HCINTMSK_STALLM   0x00000008U

STALL response received interrupt mask

#define USB_OTG_HCINTMSK_TXERRM   0x00000080U

Transaction error mask

#define USB_OTG_HCINTMSK_XFRCM   0x00000001U

Transfer completed mask

#define USB_OTG_HCSPLT_COMPLSPLT   0x00010000U

Do complete split

#define USB_OTG_HCSPLT_HUBADDR   0x00003F80U

Hub address

#define USB_OTG_HCSPLT_HUBADDR_0   0x00000080U

Bit 0

#define USB_OTG_HCSPLT_HUBADDR_1   0x00000100U

Bit 1

#define USB_OTG_HCSPLT_HUBADDR_2   0x00000200U

Bit 2

#define USB_OTG_HCSPLT_HUBADDR_3   0x00000400U

Bit 3

#define USB_OTG_HCSPLT_HUBADDR_4   0x00000800U

Bit 4

#define USB_OTG_HCSPLT_HUBADDR_5   0x00001000U

Bit 5

#define USB_OTG_HCSPLT_HUBADDR_6   0x00002000U

Bit 6

#define USB_OTG_HCSPLT_PRTADDR   0x0000007FU

Port address

#define USB_OTG_HCSPLT_PRTADDR_0   0x00000001U

Bit 0

#define USB_OTG_HCSPLT_PRTADDR_1   0x00000002U

Bit 1

#define USB_OTG_HCSPLT_PRTADDR_2   0x00000004U

Bit 2

#define USB_OTG_HCSPLT_PRTADDR_3   0x00000008U

Bit 3

#define USB_OTG_HCSPLT_PRTADDR_4   0x00000010U

Bit 4

#define USB_OTG_HCSPLT_PRTADDR_5   0x00000020U

Bit 5

#define USB_OTG_HCSPLT_PRTADDR_6   0x00000040U

Bit 6

#define USB_OTG_HCSPLT_SPLITEN   0x80000000U

Split enable

#define USB_OTG_HCSPLT_XACTPOS   0x0000C000U

XACTPOS

#define USB_OTG_HCSPLT_XACTPOS_0   0x00004000U

Bit 0

#define USB_OTG_HCSPLT_XACTPOS_1   0x00008000U

Bit 1

#define USB_OTG_HCTSIZ_DOPING   0x80000000U

Do PING

#define USB_OTG_HCTSIZ_DPID   0x60000000U

Data PID

#define USB_OTG_HCTSIZ_DPID_0   0x20000000U

Bit 0

#define USB_OTG_HCTSIZ_DPID_1   0x40000000U

Bit 1

#define USB_OTG_HCTSIZ_PKTCNT   0x1FF80000U

Packet count

#define USB_OTG_HCTSIZ_XFRSIZ   0x0007FFFFU

Transfer size

#define USB_OTG_HFIR_FRIVL   0x0000FFFFU

Frame interval

#define USB_OTG_HFNUM_FRNUM   0x0000FFFFU

Frame number

#define USB_OTG_HFNUM_FTREM   0xFFFF0000U

Frame time remaining

#define USB_OTG_HPRT_PCDET   0x00000002U

Port connect detected

#define USB_OTG_HPRT_PCSTS   0x00000001U

Port connect status

#define USB_OTG_HPRT_PENA   0x00000004U

Port enable

#define USB_OTG_HPRT_PENCHNG   0x00000008U

Port enable/disable change

#define USB_OTG_HPRT_PLSTS   0x00000C00U

Port line status

#define USB_OTG_HPRT_PLSTS_0   0x00000400U

Bit 0

#define USB_OTG_HPRT_PLSTS_1   0x00000800U

Bit 1

#define USB_OTG_HPRT_POCA   0x00000010U

Port overcurrent active

#define USB_OTG_HPRT_POCCHNG   0x00000020U

Port overcurrent change

#define USB_OTG_HPRT_PPWR   0x00001000U

Port power

#define USB_OTG_HPRT_PRES   0x00000040U

Port resume

#define USB_OTG_HPRT_PRST   0x00000100U

Port reset

#define USB_OTG_HPRT_PSPD   0x00060000U

Port speed

#define USB_OTG_HPRT_PSPD_0   0x00020000U

Bit 0

#define USB_OTG_HPRT_PSPD_1   0x00040000U

Bit 1

#define USB_OTG_HPRT_PSUSP   0x00000080U

Port suspend

#define USB_OTG_HPRT_PTCTL   0x0001E000U

Port test control

#define USB_OTG_HPRT_PTCTL_0   0x00002000U

Bit 0

#define USB_OTG_HPRT_PTCTL_1   0x00004000U

Bit 1

#define USB_OTG_HPRT_PTCTL_2   0x00008000U

Bit 2

#define USB_OTG_HPRT_PTCTL_3   0x00010000U

Bit 3

#define USB_OTG_HPTXFSIZ_PTXFD   0xFFFF0000U

Host periodic TxFIFO depth

#define USB_OTG_HPTXFSIZ_PTXSA   0x0000FFFFU

Host periodic TxFIFO start address

#define USB_OTG_HPTXSTS_PTXFSAVL   0x0000FFFFU

Periodic transmit data FIFO space available

#define USB_OTG_HPTXSTS_PTXQSAV   0x00FF0000U

Periodic transmit request queue space available

#define USB_OTG_HPTXSTS_PTXQSAV_0   0x00010000U

Bit 0

#define USB_OTG_HPTXSTS_PTXQSAV_1   0x00020000U

Bit 1

#define USB_OTG_HPTXSTS_PTXQSAV_2   0x00040000U

Bit 2

#define USB_OTG_HPTXSTS_PTXQSAV_3   0x00080000U

Bit 3

#define USB_OTG_HPTXSTS_PTXQSAV_4   0x00100000U

Bit 4

#define USB_OTG_HPTXSTS_PTXQSAV_5   0x00200000U

Bit 5

#define USB_OTG_HPTXSTS_PTXQSAV_6   0x00400000U

Bit 6

#define USB_OTG_HPTXSTS_PTXQSAV_7   0x00800000U

Bit 7

#define USB_OTG_HPTXSTS_PTXQTOP   0xFF000000U

Top of the periodic transmit request queue

#define USB_OTG_HPTXSTS_PTXQTOP_0   0x01000000U

Bit 0

#define USB_OTG_HPTXSTS_PTXQTOP_1   0x02000000U

Bit 1

#define USB_OTG_HPTXSTS_PTXQTOP_2   0x04000000U

Bit 2

#define USB_OTG_HPTXSTS_PTXQTOP_3   0x08000000U

Bit 3

#define USB_OTG_HPTXSTS_PTXQTOP_4   0x10000000U

Bit 4

#define USB_OTG_HPTXSTS_PTXQTOP_5   0x20000000U

Bit 5

#define USB_OTG_HPTXSTS_PTXQTOP_6   0x40000000U

Bit 6

#define USB_OTG_HPTXSTS_PTXQTOP_7   0x80000000U

Bit 7

#define USB_OTG_NPTXFD   0xFFFF0000U

Nonperiodic TxFIFO depth

#define USB_OTG_NPTXFSA   0x0000FFFFU

Nonperiodic transmit RAM start address

#define USB_OTG_PCGCCTL_GATECLK   0x00000002U

Bit 0

#define USB_OTG_PCGCCTL_PHYSUSP   0x00000010U

Bit 1

#define USB_OTG_PCGCCTL_STOPCLK   0x00000001U

SETUP packet count

#define USB_OTG_PCGCR_GATEHCLK   0x00000002U

Gate HCLK

#define USB_OTG_PCGCR_PHYSUSP   0x00000010U

PHY suspended

#define USB_OTG_PCGCR_STPPCLK   0x00000001U

Stop PHY clock

#define USB_OTG_PKTSTS   0x001E0000U

Packet status

#define USB_OTG_PKTSTS   0x001E0000U

Packet status

#define USB_OTG_PKTSTS_0   0x00020000U

Bit 0

#define USB_OTG_PKTSTS_0   0x00020000U

Bit 0

#define USB_OTG_PKTSTS_1   0x00040000U

Bit 1

#define USB_OTG_PKTSTS_1   0x00040000U

Bit 1

#define USB_OTG_PKTSTS_2   0x00080000U

Bit 2

#define USB_OTG_PKTSTS_2   0x00080000U

Bit 2

#define USB_OTG_PKTSTS_3   0x00100000U

Bit 3

#define USB_OTG_PKTSTS_3   0x00100000U

Bit 3

#define USB_OTG_TX0FD   0xFFFF0000U

Endpoint 0 TxFIFO depth

#define USB_OTG_TX0FSA   0x0000FFFFU

Endpoint 0 transmit RAM start address

#define WWDG_CFR_EWI   0x0200U

Early Wakeup Interrupt

#define WWDG_CFR_W   0x007FU

W[6:0] bits (7-bit window value)

#define WWDG_CFR_W0   WWDG_CFR_W_0

Bit 0

#define WWDG_CFR_W1   WWDG_CFR_W_1

Bit 1

#define WWDG_CFR_W2   WWDG_CFR_W_2

Bit 2

#define WWDG_CFR_W3   WWDG_CFR_W_3

Bit 3

#define WWDG_CFR_W4   WWDG_CFR_W_4

Bit 4

#define WWDG_CFR_W5   WWDG_CFR_W_5

Bit 5

#define WWDG_CFR_W6   WWDG_CFR_W_6

Bit 6

#define WWDG_CFR_W_0   0x0001U

Bit 0

#define WWDG_CFR_W_1   0x0002U

Bit 1

#define WWDG_CFR_W_2   0x0004U

Bit 2

#define WWDG_CFR_W_3   0x0008U

Bit 3

#define WWDG_CFR_W_4   0x0010U

Bit 4

#define WWDG_CFR_W_5   0x0020U

Bit 5

#define WWDG_CFR_W_6   0x0040U

Bit 6

#define WWDG_CFR_WDGTB   0x0180U

WDGTB[1:0] bits (Timer Base)

#define WWDG_CFR_WDGTB0   WWDG_CFR_WDGTB_0

Bit 0

#define WWDG_CFR_WDGTB1   WWDG_CFR_WDGTB_1

Bit 1

#define WWDG_CFR_WDGTB_0   0x0080U

Bit 0

#define WWDG_CFR_WDGTB_1   0x0100U

Bit 1

#define WWDG_CR_T   0x7FU

T[6:0] bits (7-Bit counter (MSB to LSB))

#define WWDG_CR_T0   WWDG_CR_T_0

Bit 0

#define WWDG_CR_T1   WWDG_CR_T_1

Bit 1

#define WWDG_CR_T2   WWDG_CR_T_2

Bit 2

#define WWDG_CR_T3   WWDG_CR_T_3

Bit 3

#define WWDG_CR_T4   WWDG_CR_T_4

Bit 4

#define WWDG_CR_T5   WWDG_CR_T_5

Bit 5

#define WWDG_CR_T6   WWDG_CR_T_6

Bit 6

#define WWDG_CR_T_0   0x01U

Bit 0

#define WWDG_CR_T_1   0x02U

Bit 1

#define WWDG_CR_T_2   0x04U

Bit 2

#define WWDG_CR_T_3   0x08U

Bit 3

#define WWDG_CR_T_4   0x10U

Bit 4

#define WWDG_CR_T_5   0x20U

Bit 5

#define WWDG_CR_T_6   0x40U

Bit 6

#define WWDG_CR_WDGA   0x80U

Activation bit

#define WWDG_SR_EWIF   0x01U

Early Wakeup Interrupt Flag