EU1KY AA FW
QUADSPI_TypeDef Struct Reference

QUAD Serial Peripheral Interface. More...

#include <stm32f746xx.h>

Data Fields

__IO uint32_t CR
 
__IO uint32_t DCR
 
__IO uint32_t SR
 
__IO uint32_t FCR
 
__IO uint32_t DLR
 
__IO uint32_t CCR
 
__IO uint32_t AR
 
__IO uint32_t ABR
 
__IO uint32_t DR
 
__IO uint32_t PSMKR
 
__IO uint32_t PSMAR
 
__IO uint32_t PIR
 
__IO uint32_t LPTR
 

Detailed Description

QUAD Serial Peripheral Interface.

Field Documentation

__IO uint32_t QUADSPI_TypeDef::ABR

QUADSPI Alternate Bytes register, Address offset: 0x1C

__IO uint32_t QUADSPI_TypeDef::AR

QUADSPI Address register, Address offset: 0x18

__IO uint32_t QUADSPI_TypeDef::CCR

QUADSPI Communication Configuration register, Address offset: 0x14

__IO uint32_t QUADSPI_TypeDef::CR

QUADSPI Control register, Address offset: 0x00

__IO uint32_t QUADSPI_TypeDef::DCR

QUADSPI Device Configuration register, Address offset: 0x04

__IO uint32_t QUADSPI_TypeDef::DLR

QUADSPI Data Length register, Address offset: 0x10

__IO uint32_t QUADSPI_TypeDef::DR

QUADSPI Data register, Address offset: 0x20

__IO uint32_t QUADSPI_TypeDef::FCR

QUADSPI Flag Clear register, Address offset: 0x0C

__IO uint32_t QUADSPI_TypeDef::LPTR

QUADSPI Low Power Timeout register, Address offset: 0x30

__IO uint32_t QUADSPI_TypeDef::PIR

QUADSPI Polling Interval register, Address offset: 0x2C

__IO uint32_t QUADSPI_TypeDef::PSMAR

QUADSPI Polling Status Match register, Address offset: 0x28

__IO uint32_t QUADSPI_TypeDef::PSMKR

QUADSPI Polling Status Mask register, Address offset: 0x24

__IO uint32_t QUADSPI_TypeDef::SR

QUADSPI Status register, Address offset: 0x08


The documentation for this struct was generated from the following file: