EU1KY AA FW
DAC_TypeDef Struct Reference

Digital to Analog Converter. More...

#include <stm32f746xx.h>

Data Fields

__IO uint32_t CR
 
__IO uint32_t SWTRIGR
 
__IO uint32_t DHR12R1
 
__IO uint32_t DHR12L1
 
__IO uint32_t DHR8R1
 
__IO uint32_t DHR12R2
 
__IO uint32_t DHR12L2
 
__IO uint32_t DHR8R2
 
__IO uint32_t DHR12RD
 
__IO uint32_t DHR12LD
 
__IO uint32_t DHR8RD
 
__IO uint32_t DOR1
 
__IO uint32_t DOR2
 
__IO uint32_t SR
 

Detailed Description

Digital to Analog Converter.

Field Documentation

__IO uint32_t DAC_TypeDef::CR

DAC control register, Address offset: 0x00

__IO uint32_t DAC_TypeDef::DHR12L1

DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C

__IO uint32_t DAC_TypeDef::DHR12L2

DAC channel2 12-bit left aligned data holding register, Address offset: 0x18

__IO uint32_t DAC_TypeDef::DHR12LD

DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24

__IO uint32_t DAC_TypeDef::DHR12R1

DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08

__IO uint32_t DAC_TypeDef::DHR12R2

DAC channel2 12-bit right aligned data holding register, Address offset: 0x14

__IO uint32_t DAC_TypeDef::DHR12RD

Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20

__IO uint32_t DAC_TypeDef::DHR8R1

DAC channel1 8-bit right aligned data holding register, Address offset: 0x10

__IO uint32_t DAC_TypeDef::DHR8R2

DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C

__IO uint32_t DAC_TypeDef::DHR8RD

DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28

__IO uint32_t DAC_TypeDef::DOR1

DAC channel1 data output register, Address offset: 0x2C

__IO uint32_t DAC_TypeDef::DOR2

DAC channel2 data output register, Address offset: 0x30

__IO uint32_t DAC_TypeDef::SR

DAC status register, Address offset: 0x34

__IO uint32_t DAC_TypeDef::SWTRIGR

DAC software trigger register, Address offset: 0x04


The documentation for this struct was generated from the following file: