EU1KY AA FW
DMA2D_TypeDef Struct Reference

DMA2D Controller. More...

#include <stm32f746xx.h>

Data Fields

__IO uint32_t CR
 
__IO uint32_t ISR
 
__IO uint32_t IFCR
 
__IO uint32_t FGMAR
 
__IO uint32_t FGOR
 
__IO uint32_t BGMAR
 
__IO uint32_t BGOR
 
__IO uint32_t FGPFCCR
 
__IO uint32_t FGCOLR
 
__IO uint32_t BGPFCCR
 
__IO uint32_t BGCOLR
 
__IO uint32_t FGCMAR
 
__IO uint32_t BGCMAR
 
__IO uint32_t OPFCCR
 
__IO uint32_t OCOLR
 
__IO uint32_t OMAR
 
__IO uint32_t OOR
 
__IO uint32_t NLR
 
__IO uint32_t LWR
 
__IO uint32_t AMTCR
 
uint32_t RESERVED [236]
 
__IO uint32_t FGCLUT [256]
 
__IO uint32_t BGCLUT [256]
 

Detailed Description

DMA2D Controller.

Field Documentation

__IO uint32_t DMA2D_TypeDef::AMTCR

DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C

__IO uint32_t DMA2D_TypeDef::BGCLUT[256]

DMA2D Background CLUT, Address offset:800-BFF

__IO uint32_t DMA2D_TypeDef::BGCMAR

DMA2D Background CLUT Memory Address Register, Address offset: 0x30

__IO uint32_t DMA2D_TypeDef::BGCOLR

DMA2D Background Color Register, Address offset: 0x28

__IO uint32_t DMA2D_TypeDef::BGMAR

DMA2D Background Memory Address Register, Address offset: 0x14

__IO uint32_t DMA2D_TypeDef::BGOR

DMA2D Background Offset Register, Address offset: 0x18

__IO uint32_t DMA2D_TypeDef::BGPFCCR

DMA2D Background PFC Control Register, Address offset: 0x24

__IO uint32_t DMA2D_TypeDef::CR

DMA2D Control Register, Address offset: 0x00

__IO uint32_t DMA2D_TypeDef::FGCLUT[256]

DMA2D Foreground CLUT, Address offset:400-7FF

__IO uint32_t DMA2D_TypeDef::FGCMAR

DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C

__IO uint32_t DMA2D_TypeDef::FGCOLR

DMA2D Foreground Color Register, Address offset: 0x20

__IO uint32_t DMA2D_TypeDef::FGMAR

DMA2D Foreground Memory Address Register, Address offset: 0x0C

__IO uint32_t DMA2D_TypeDef::FGOR

DMA2D Foreground Offset Register, Address offset: 0x10

__IO uint32_t DMA2D_TypeDef::FGPFCCR

DMA2D Foreground PFC Control Register, Address offset: 0x1C

__IO uint32_t DMA2D_TypeDef::IFCR

DMA2D Interrupt Flag Clear Register, Address offset: 0x08

__IO uint32_t DMA2D_TypeDef::ISR

DMA2D Interrupt Status Register, Address offset: 0x04

__IO uint32_t DMA2D_TypeDef::LWR

DMA2D Line Watermark Register, Address offset: 0x48

__IO uint32_t DMA2D_TypeDef::NLR

DMA2D Number of Line Register, Address offset: 0x44

__IO uint32_t DMA2D_TypeDef::OCOLR

DMA2D Output Color Register, Address offset: 0x38

__IO uint32_t DMA2D_TypeDef::OMAR

DMA2D Output Memory Address Register, Address offset: 0x3C

__IO uint32_t DMA2D_TypeDef::OOR

DMA2D Output Offset Register, Address offset: 0x40

__IO uint32_t DMA2D_TypeDef::OPFCCR

DMA2D Output PFC Control Register, Address offset: 0x34

uint32_t DMA2D_TypeDef::RESERVED[236]

Reserved, 0x50-0x3FF


The documentation for this struct was generated from the following file: