EU1KY AA FW
SDMMC_TypeDef Struct Reference

SD host Interface. More...

#include <stm32f746xx.h>

Data Fields

__IO uint32_t POWER
 
__IO uint32_t CLKCR
 
__IO uint32_t ARG
 
__IO uint32_t CMD
 
__I uint32_t RESPCMD
 
__I uint32_t RESP1
 
__I uint32_t RESP2
 
__I uint32_t RESP3
 
__I uint32_t RESP4
 
__IO uint32_t DTIMER
 
__IO uint32_t DLEN
 
__IO uint32_t DCTRL
 
__I uint32_t DCOUNT
 
__I uint32_t STA
 
__IO uint32_t ICR
 
__IO uint32_t MASK
 
uint32_t RESERVED0 [2]
 
__I uint32_t FIFOCNT
 
uint32_t RESERVED1 [13]
 
__IO uint32_t FIFO
 

Detailed Description

SD host Interface.

Field Documentation

__IO uint32_t SDMMC_TypeDef::ARG

SDMMC argument register, Address offset: 0x08

__IO uint32_t SDMMC_TypeDef::CLKCR

SDMMClock control register, Address offset: 0x04

__IO uint32_t SDMMC_TypeDef::CMD

SDMMC command register, Address offset: 0x0C

__I uint32_t SDMMC_TypeDef::DCOUNT

SDMMC data counter register, Address offset: 0x30

__IO uint32_t SDMMC_TypeDef::DCTRL

SDMMC data control register, Address offset: 0x2C

__IO uint32_t SDMMC_TypeDef::DLEN

SDMMC data length register, Address offset: 0x28

__IO uint32_t SDMMC_TypeDef::DTIMER

SDMMC data timer register, Address offset: 0x24

__IO uint32_t SDMMC_TypeDef::FIFO

SDMMC data FIFO register, Address offset: 0x80

__I uint32_t SDMMC_TypeDef::FIFOCNT

SDMMC FIFO counter register, Address offset: 0x48

__IO uint32_t SDMMC_TypeDef::ICR

SDMMC interrupt clear register, Address offset: 0x38

__IO uint32_t SDMMC_TypeDef::MASK

SDMMC mask register, Address offset: 0x3C

__IO uint32_t SDMMC_TypeDef::POWER

SDMMC power control register, Address offset: 0x00

uint32_t SDMMC_TypeDef::RESERVED0[2]

Reserved, 0x40-0x44

uint32_t SDMMC_TypeDef::RESERVED1[13]

Reserved, 0x4C-0x7C

__I uint32_t SDMMC_TypeDef::RESP1

SDMMC response 1 register, Address offset: 0x14

__I uint32_t SDMMC_TypeDef::RESP2

SDMMC response 2 register, Address offset: 0x18

__I uint32_t SDMMC_TypeDef::RESP3

SDMMC response 3 register, Address offset: 0x1C

__I uint32_t SDMMC_TypeDef::RESP4

SDMMC response 4 register, Address offset: 0x20

__I uint32_t SDMMC_TypeDef::RESPCMD

SDMMC command response register, Address offset: 0x10

__I uint32_t SDMMC_TypeDef::STA

SDMMC status register, Address offset: 0x34


The documentation for this struct was generated from the following file: