.include "m8515def.inc"

;definitions

.def temp 				= r20
.def tempH				= r21
.def dmx_byte			= r22
.def dmx_status			= r23
.def DMXcountL			= r5
.def DMXcountH			= r6
.def adresseL			= r3
.def adresseH			= r4
.def null				= r1

.equ BIT9= PE2

;interrupt vectors
	
	rjmp init 		;reset vector address
	reti			;External Interrupt0 Vector Address
	reti			;External Interrupt1 Vector Address
	reti			;Input Capture1 Interrupt Vector Address
	reti			;Output Compare1A Interrupt Vector Address
	reti			;Output Compare1B Interrupt Vector Address
	reti			;Overflow1 Interrupt Vector Address
	reti			;Overflow0 Interrupt Vector Address
	reti			;SPI Interrupt Vector Address
	rjmp get_byte	;UART Receive Complete Interrupt Vector Address
	reti			;UART Data Register Empty Interrupt Vector Address
	reti			;UART Transmit Complete Interrupt Vector Address
	reti			;Analog Comparator Interrupt Vector Address
	reti			;External Interrupt2 Vector Address
	reti			;Output Compare0 Interrupt Vector Address
	reti			; EEPROM Interrupt Vector Address
	reti			; SPM complete Interrupt Vector Address
	reti			; SPM complete Interrupt Vector Address

; INIT

init:

; PWM

	sbi	 	DDRB,PB0
	ldi		r16,0b01100001
	out 	TCCR0,r16

; Stack
	ldi	tempH,high(RAMEND)
	ldi	temp,low(RAMEND)
	out	SPH,tempH
	out	SPL,temp

; PortC
	clr temp
	out DDRC, temp
	ser temp
	out PortC, temp  ;DIP eingänge mit pullup

; PortD
	ldi temp, 0b10000100
	out DDRD, temp
	ldi temp, 0b00001000
	out PortD, temp ; DMX, LED1 on

; PortE
	clr temp
	out DDRE, temp
	ser	temp
	out PortE, temp ; BIT9 DIP-pullup

;USART
	
    ldi 	temp, 0x01	;setze Uart to 250 kbaud @ 8Mhz
    out 	UBRRL, temp
    ldi 	temp, 0x00
    out 	UBRRH, temp
    ldi 	temp, (1<<URSEL)|(3<<UCSZ0);	(nur 1 Stopbit!!)
    out 	UCSRC, temp			;
	clr 	dmx_status			;setze DMX-Status Byte to 'wait for Reset'
	in		temp,UDR			;clear Uart Receive Interrupt Flag
 	out		UCSRA,dmx_status	;clear all error ErrFlags, disable U2X and MPCM
	sbi 	UCSRB,RXCIE			;enable Uart Receive Interrupt
	sbi 	UCSRB,RXEN			;enable Uart Receive
	
; set Register
	clr null		

	sei

;forever: rjmp forever


get_byte:		

		in		temp,UCSRA		; get status register before data register
		in		dmx_byte,UDR

		sbrc	temp,DOR		; check for overrun -> wait for reset
		rjmp	overrun
 		sbrc	temp,FE			; check for frame error -> got reset
		rjmp	frame_error

		inc 	DMXcountL		; count incoming frames
		brne	gb_1
		inc		DMXcountH
	   gb_1:		
		
		cpi		dmx_status, 1   ; check for startbyte (else frame error -> reset)
		breq	startbyte

		cpi 	dmx_status, 2   ; check for start adress
		breq    startadr
  
 back:	cpi 	dmx_status, 3	;
  		brsh	handle_byte

		reti	;return interrupt
		

	startbyte:
		cp	 	dmx_byte, null 			; compare Startbyte
		brne 	overrun
		inc  	dmx_status 				; next -> Startadresse
		clr		DMXcountH				; reset frame counter
		clr		DMXcountL
		in 		adresseL, PinC 			; Einlesen der Startadresse
		com     adresseL
		clr		adresseH
		sbis	PinE, BIT9				; 9. bit
		inc		adresseH
		reti

 	startadr:
		clc
		cp		DMXcountL, adresseL
		cpc		DMXcountH, adresseH	
		brne	gb_exit
		inc  	dmx_status 				; next -> Byte-Verarbeitung
		rjmp 	back 					; springe zurück zur Verarbeitung...
	   gb_exit:
		reti
	
	handle_byte:	
		clr dmx_status					; all bytes received -> wait for BREAK
		out		OCR0,dmx_byte

		reti
	
 	frame_error:
		inc		dmx_status				; frame-error detected as break
		cbi		UCSRA,FE
		reti

	overrun:
	 	clr 	dmx_status				; warte auf frame-error
		reti