================================================================== 2.dqs window x=pass dqs delay value (min~max)center y=0-7bit DQ of every group input delay:DQS0 =50 DQS1 = 40 DQS2 =48 DQS3 = 44 ================================================================== bit DQS0 bit DQS1 bit DQS2 bit DQS3 0 (19~68)43 8 (7~56)31 16 (22~69)45 24 (17~60)38 1 (19~66)42 9 (9~57)33 17 (23~64)43 25 (17~57)37 2 (20~70)45 10 (15~61)38 18 (26~69)47 26 (19~64)41 3 (17~68)42 11 (13~58)35 19 (21~64)42 27 (19~61)40 4 (21~71)46 12 (17~63)40 20 (23~71)47 28 (23~66)44 5 (20~71)45 13 (16~62)39 21 (23~73)48 29 (19~65)42 6 (25~71)48 14 (13~62)37 22 (25~70)47 30 (17~62)39 7 (29~72)50 15 (17~61)39 23 (26~71)48 31 (19~64)41 ================================================================== 3.dq delay value last ================================================================== bit| 0 1 2 3 4 5 6 7 8 9 -------------------------------------- 0 | 7 8 5 8 4 5 2 0 9 7 10 | 2 5 0 1 3 1 3 5 1 6 20 | 1 0 1 0 6 7 3 4 0 2 30 | 5 3 ================================================================== *DQIDLY1 = 0x8050807 *DQIDLY2 = 0x20504 *DQIDLY3 = 0x5020709 *DQIDLY4 = 0x1030100 *DQIDLY5 = 0x6010503 *DQIDLY6 = 0x10001 *DQIDLY7 = 0x4030706 *DQIDLY8 = 0x3050200 *DRAMC_R0DELDLY = 0x2C302832 [MEM]CONA:F3A2,conf1:F07486A3 DM4BitMux = 1 [Warning] DQSO 0 in TX per-bit = 4 > DQSO 0 in WL = 1 DQSO 1 in TX per-bit = 0 <= DQSO 1 in WL = 0 [Warning] DQSO 2 in TX per-bit = 7 > DQSO 2 in WL = 0 [Warning] DQSO 3 in TX per-bit = 9 > DQSO 3 in WL = 0 Tx DQM dly = 0x2022 Tx DQM dly bit4 = 0x0 DRAMC_DQODLY1=3432333h DRAMC_DQODLY2=24213133h DRAMC_DQODLY3=4214h DRAMC_DQODLY4=32103012h Tx DQ dly bit4 = 0x0 Tx DQS dly = 0x9704 Tx DQS dly bit4 = 0x0 TX Byte0: DQ - 13, DQS - 19. win_sum= 31 TX Byte1: DQ - 18, DQS - 14. win_sum= 31 TX Byte2: DQ - 9, DQS - 22. win_sum= 30 TX Byte3: DQ - 6, DQS - 22. win_sum= 27 DRAMC calibration takes 650406561 CPU cycles [EMI] DRAMC calibration passed [MEM] complex R/W mem test pass 0:dram_rank_size:80000000 [Dram_Buffer] dram size:-2147483648 [Dram_Buffer] structure size: 1725560 [Dram_Buffer] MAX_TEE_DRAM_SIZE: 0 Load u-boot from eMMC... [PLFM] Init Boot Device: OK(0) [PART] blksz: 512B [PART] [0x0000000000000000-0x000000000003FFFF] "PRELOADER" (512 blocks) [PART] [0x0000000000000000-0x000000000003FFFF] "MBR" (512 blocks) [PART] [0x0000000000040000-0x00000000000BFFFF] "UBOOT" (1024 blocks) [PART] [0x00000000000C0000-0x00000000000FFFFF] "CONFIG" (512 blocks) [PART] [0x0000000000100000-0x000000000013FFFF] "FACTORY" (512 blocks) [PART] [0x0000000000140000-0x000000000213FFFF] "BOOTIMG" (65536 blocks) [PART] [0x0000000002140000-0x000000000413FFFF] "RECOVERY" (65536 blocks) [PART] [0x0000000004140000-0x000000004413FFFF] "ROOTFS" (2097152 blocks) [PART] [0x0000000044140000-0x000001FFC413FFFF] "USER" (-4194304 blocks) [platform_vusb_on] PASS [TOOL] PMIC not dectect usb cable! [TOOL] listen ended, receive size:0! [TOOL] wait sync time 150ms->5ms [TOOL] receieved data: () Device APC domain init setup: bootloader load uboot ,the address of uboot is 81E00000 [PART]partition name UBOOT [PART]partition start block 0x200 [PART]partition size 0x80000 [PART]partition blks 0x400 [PART]partition flags 0x0 [PART]partition name 0x8 [bean] part->startblk(0x200) bdev->blksz(0x200) part->part_id(8) hdr(0xFFB50000) [BlkDev.c 101 ]partition block size 0x200 ,blks:0xE90000 [BlkDev.c 101 ]partition block erase size 0x200 [PART] load "UBOOT" from 0x0000000000050000 (dev) to 0x81E00000 (mem) [SUCCESS] [PART] load speed: 10462KB/s, 300000 bytes, 28ms [BT_SD_PG] device info 0x8590 0x8A00 0xCB01 0x102 0:dram_rank_size:80000000 [PLFM] md_type[0] = 255 [PLFM] md_type[1] = 255 [PLFM] boot reason: 0 [PLFM] boot mode: 0 [PLFM] META COM0: 0 [PLFM] <0xFFB7CC10>: 0x0 [PLFM] boot time: 3045ms [PLFM] DDR reserve mode: enable = 0, success = 0 [BLDR] jump to 0x81E00000 [BLDR] <0x81E00000>=0xEA0000B8 [BLDR] <0x81E00004>=0xE59FF014