library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; use ieee.math_real.all; entity delay is port ( set : in std_logic; result : out std_logic := '0' ); end; architecture arch of delay is shared variable seed1 : positive; shared variable seed2 : positive; signal latchchain : unsigned(15 downto 0) := (others => '0'); signal clear : std_logic := '0'; impure function get_rand(min : integer; max: integer) return time is variable value : real; variable random : integer; variable randtime : time; begin uniform(seed1, seed2, value); random := integer(floor(value * real(max-min))); randtime := (random + min) * 1 ps; return randtime; end function; begin process (set, latchchain, clear) begin if (latchchain = 0) then clear <= '0' after get_rand(50, 50000); elsif (latchchain = (latchchain'left downto 0 => '1')) then clear <= '1' after get_rand(50, 50000); end if; if (set = '1') then latchchain(0) <= '1' after get_rand(50, 50000); elsif clear = '1' then latchchain(0) <= '0' after get_rand(50, 50000); end if; if (latchchain > 256) then result <= '1' after get_rand(50, 50000); else result <= '0' after get_rand(50, 50000); end if; for i in 1 to latchchain'left loop if clear = '1' then latchchain(i) <= '0' after get_rand(50, 50000); elsif (latchchain(i-1) = '1') then latchchain(i) <= '1' after get_rand(50, 50000); end if; end loop; end process; end;