library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity top_level_tb is end entity top_level_tb; architecture testbench of top_level_tb is constant clk_period : time := 1 sec / 50_000_000; signal simulation_run : boolean := true; signal tb_clk_50 : std_logic := '0'; signal tb_rst_n : std_logic := '0'; signal tb_vga_r : std_logic_vector(7 downto 0); signal tb_vga_g : std_logic_vector(7 downto 0); signal tb_vga_b : std_logic_vector(7 downto 0); signal tb_vga_clk : std_logic; signal tb_vga_blank_n : std_logic; signal tb_vga_hs : std_logic; signal tb_vga_vs : std_logic; signal tb_vga_sync : std_logic; begin tb_clk_50 <= not tb_clk_50 after clk_period / 2 when simulation_run; tb_rst_n <= '0', '1' after 5 * clk_period; dut: entity work.top_level port map ( clk_50 => tb_clk_50, --: in std_logic; rst_n => tb_rst_n, --: in std_logic; ------------VGA interface-------------- vga_r => tb_vga_r, --: out std_logic_vector(7 downto 0); vga_g => tb_vga_g, --: out std_logic_vector(7 downto 0); vga_b => tb_vga_b, --: out std_logic_vector(7 downto 0); vga_clk => tb_vga_clk, --: out std_logic; vga_blank_n => tb_vga_blank_n, --: out std_logic; vga_hs => tb_vga_hs, --: out std_logic; vga_vs => tb_vga_vs, --: out std_logic; vga_sync => tb_vga_sync --: out std_logic ); sim_control: process begin wait for 1 ms; simulation_run <= false; report "Simulation ends."; wait; end process; end architecture testbench;