Timing Summary Report ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes check_timing report Table of Contents ----------------- 1. checking no_clock 2. checking constant_clock 3. checking pulse_width_clock 4. checking unconstrained_internal_endpoints 5. checking no_input_delay 6. checking no_output_delay 7. checking multiple_clock 8. checking generated_clocks 9. checking loops 10. checking partial_input_delay 11. checking partial_output_delay 12. checking latch_loops 1. checking no_clock -------------------- There are 0 register/latch pins with no clock. 2. checking constant_clock -------------------------- There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock ----------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints -------------------------------------------- There are 0 pins that are not constrained for maximum delay. There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay -------------------------- There are 2 input ports with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay --------------------------- There are 9 ports with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock -------------------------- There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks ---------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops ----------------- There are 0 combinational loops in the design. 10. checking partial_input_delay -------------------------------- There are 0 input ports with partial input delay specified. 11. checking partial_output_delay --------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops ------------------------ There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 0.422 0.000 0 1004 0.067 0.000 0 1004 3.020 0.000 0 457 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sys_clk_pin {0.000 4.000} 8.000 125.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin 0.422 0.000 0 977 0.067 0.000 0 977 3.020 0.000 0 457 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- **async_default** sys_clk_pin sys_clk_pin 5.203 0.000 0 27 0.711 0.000 0 27 ------------------------------------------------------------------------------------------------ | Timing Details | -------------- ------------------------------------------------------------------------------------------------ --------------------------------------------------------------------------------------------------- From Clock: sys_clk_pin To Clock: sys_clk_pin Setup : 0 Failing Endpoints, Worst Slack 0.422ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.067ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.020ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.422ns (required time - arrival time) Source: FIR_Test_inst/counter_filter_reg[1]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: FIR_Test_inst/temp_result0/A[3] (rising edge-triggered cell DSP48E1 clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Setup (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 3.849ns (logic 1.431ns (37.177%) route 2.418ns (62.823%)) Logic Levels: 4 (LUT5=1 LUT6=1 MUXF7=1 MUXF8=1) Clock Path Skew: 0.029ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.477ns = ( 13.477 - 8.000 ) Source Clock Delay (SCD): 5.872ns Clock Pessimism Removal (CPR): 0.424ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r K17 0.000 0.000 r MAIN_CLK_IN (IN) net (fo=0) 0.000 0.000 MAIN_CLK_IN K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r MAIN_CLK_IN_IBUF_inst/O net (fo=1, routed) 2.522 3.997 MAIN_CLK_IN_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 4.098 r MAIN_CLK_IN_IBUF_BUFG_inst/O net (fo=456, routed) 1.774 5.872 FIR_Test_inst/MAIN_CLK_IN_IBUF_BUFG SLICE_X104Y81 FDRE r FIR_Test_inst/counter_filter_reg[1]/C ------------------------------------------------------------------- ------------------- SLICE_X104Y81 FDRE (Prop_fdre_C_Q) 0.478 6.350 r FIR_Test_inst/counter_filter_reg[1]/Q net (fo=76, routed) 1.425 7.774 FIR_Test_inst/counter_filter_reg_n_0_[1] SLICE_X104Y75 LUT6 (Prop_lut6_I2_O) 0.295 8.069 r FIR_Test_inst/temp_result0_i_95/O net (fo=1, routed) 0.000 8.069 FIR_Test_inst/temp_result0_i_95_n_0 SLICE_X104Y75 MUXF7 (Prop_muxf7_I0_O) 0.241 8.310 r FIR_Test_inst/temp_result0_i_55/O net (fo=1, routed) 0.000 8.310 FIR_Test_inst/temp_result0_i_55_n_0 SLICE_X104Y75 MUXF8 (Prop_muxf8_I0_O) 0.098 8.408 r FIR_Test_inst/temp_result0_i_32/O net (fo=1, routed) 0.596 9.005 FIR_Test_inst/temp_result0_i_32_n_0 SLICE_X104Y80 LUT5 (Prop_lut5_I4_O) 0.319 9.324 r FIR_Test_inst/temp_result0_i_11/O net (fo=1, routed) 0.397 9.721 FIR_Test_inst/x[0]_1[3] DSP48_X4Y32 DSP48E1 r FIR_Test_inst/temp_result0/A[3] ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r K17 0.000 8.000 r MAIN_CLK_IN (IN) net (fo=0) 0.000 8.000 MAIN_CLK_IN K17 IBUF (Prop_ibuf_I_O) 1.404 9.404 r MAIN_CLK_IN_IBUF_inst/O net (fo=1, routed) 2.293 11.697 MAIN_CLK_IN_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.788 r MAIN_CLK_IN_IBUF_BUFG_inst/O net (fo=456, routed) 1.688 13.477 FIR_Test_inst/MAIN_CLK_IN_IBUF_BUFG DSP48_X4Y32 DSP48E1 r FIR_Test_inst/temp_result0/CLK clock pessimism 0.424 13.900 clock uncertainty -0.035 13.865 DSP48_X4Y32 DSP48E1 (Setup_dsp48e1_CLK_A[3]) -3.722 10.143 FIR_Test_inst/temp_result0 ------------------------------------------------------------------- required time 10.143 arrival time -9.721 ------------------------------------------------------------------- slack 0.422 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.067ns (arrival time - required time) Source: DA2_standalone_inst/saveRegisterA_reg[11]/C (rising edge-triggered cell FDRE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: DA2_standalone_inst/saveRegisterA_reg[13]_srl2___DA2_standalone_inst_saveRegisterA_reg_r_0/D (rising edge-triggered cell SRL16E clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: sys_clk_pin Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.241ns Source Clock Delay (SCD): 1.714ns Clock Pessimism Removal (CPR): 0.513ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r K17 0.000 0.000 r MAIN_CLK_IN (IN) net (fo=0) 0.000 0.000 MAIN_CLK_IN K17 IBUF (Prop_ibuf_I_O) 0.243 0.243 r MAIN_CLK_IN_IBUF_inst/O net (fo=1, routed) 0.842 1.084 MAIN_CLK_IN_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 1.110 r MAIN_CLK_IN_IBUF_BUFG_inst/O net (fo=456, routed) 0.604 1.714 DA2_standalone_inst/MAIN_CLK_IN_IBUF_BUFG SLICE_X105Y85 FDRE r DA2_standalone_inst/saveRegisterA_reg[11]/C ------------------------------------------------------------------- ------------------- SLICE_X105Y85 FDRE (Prop_fdre_C_Q) 0.141 1.855 r DA2_standalone_inst/saveRegisterA_reg[11]/Q net (fo=1, routed) 0.056 1.911 DA2_standalone_inst/saveRegisterA[11] SLICE_X104Y85 SRL16E r DA2_standalone_inst/saveRegisterA_reg[13]_srl2___DA2_standalone_inst_saveRegisterA_reg_r_0/D ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r K17 0.000 0.000 r MAIN_CLK_IN (IN) net (fo=0) 0.000 0.000 MAIN_CLK_IN K17 IBUF (Prop_ibuf_I_O) 0.431 0.431 r MAIN_CLK_IN_IBUF_inst/O net (fo=1, routed) 0.907 1.338 MAIN_CLK_IN_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.367 r MAIN_CLK_IN_IBUF_BUFG_inst/O net (fo=456, routed) 0.874 2.241 DA2_standalone_inst/MAIN_CLK_IN_IBUF_BUFG SLICE_X104Y85 SRL16E r DA2_standalone_inst/saveRegisterA_reg[13]_srl2___DA2_standalone_inst_saveRegisterA_reg_r_0/CLK clock pessimism -0.513 1.727 SLICE_X104Y85 SRL16E (Hold_srl16e_CLK_D) 0.117 1.844 DA2_standalone_inst/saveRegisterA_reg[13]_srl2___DA2_standalone_inst_saveRegisterA_reg_r_0 ------------------------------------------------------------------- required time -1.844 arrival time 1.911 ------------------------------------------------------------------- slack 0.067 Pulse Width Checks -------------------------------------------------------------------------------------- Clock Name: sys_clk_pin Waveform(ns): { 0.000 4.000 } Period(ns): 8.000 Sources: { MAIN_CLK_IN } Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin Min Period n/a BUFG/I n/a 2.155 8.000 5.845 BUFGCTRL_X0Y16 MAIN_CLK_IN_IBUF_BUFG_inst/I Low Pulse Width Slow SRL16E/CLK n/a 0.980 4.000 3.020 SLICE_X104Y85 DA2_standalone_inst/saveRegisterA_reg[13]_srl2___DA2_standalone_inst_saveRegisterA_reg_r_0/CLK High Pulse Width Fast SRL16E/CLK n/a 0.980 4.000 3.020 SLICE_X104Y85 DA2_standalone_inst/saveRegisterA_reg[13]_srl2___DA2_standalone_inst_saveRegisterA_reg_r_0/CLK --------------------------------------------------------------------------------------------------- Path Group: **async_default** From Clock: sys_clk_pin To Clock: sys_clk_pin Setup : 0 Failing Endpoints, Worst Slack 5.203ns, Total Violation 0.000ns Hold : 0 Failing Endpoints, Worst Slack 0.711ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 5.203ns (required time - arrival time) Source: iic_protocol_inst/reset_reg/C (rising edge-triggered cell FDPE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: iic_protocol_inst/data_rd_reg[0]/CLR (recovery check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Recovery (Max at Slow Process Corner) Requirement: 8.000ns (sys_clk_pin rise@8.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 2.296ns (logic 0.642ns (27.963%) route 1.654ns (72.037%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: -0.061ns (DCD - SCD + CPR) Destination Clock Delay (DCD): 5.460ns = ( 13.460 - 8.000 ) Source Clock Delay (SCD): 5.945ns Clock Pessimism Removal (CPR): 0.424ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r K17 0.000 0.000 r MAIN_CLK_IN (IN) net (fo=0) 0.000 0.000 MAIN_CLK_IN K17 IBUF (Prop_ibuf_I_O) 1.475 1.475 r MAIN_CLK_IN_IBUF_inst/O net (fo=1, routed) 2.522 3.997 MAIN_CLK_IN_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.101 4.098 r MAIN_CLK_IN_IBUF_BUFG_inst/O net (fo=456, routed) 1.847 5.945 iic_protocol_inst/MAIN_CLK_IN_IBUF_BUFG SLICE_X112Y76 FDPE r iic_protocol_inst/reset_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y76 FDPE (Prop_fdpe_C_Q) 0.518 6.463 r iic_protocol_inst/reset_reg/Q net (fo=23, routed) 0.638 7.101 iic_protocol_inst/reset_reg_n_0 SLICE_X108Y76 LUT1 (Prop_lut1_I0_O) 0.124 7.225 f iic_protocol_inst/bit_cnt[3]_i_3/O net (fo=27, routed) 1.016 8.241 iic_protocol_inst/bit_cnt[3]_i_3_n_0 SLICE_X106Y79 FDCE f iic_protocol_inst/data_rd_reg[0]/CLR ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 8.000 8.000 r K17 0.000 8.000 r MAIN_CLK_IN (IN) net (fo=0) 0.000 8.000 MAIN_CLK_IN K17 IBUF (Prop_ibuf_I_O) 1.404 9.404 r MAIN_CLK_IN_IBUF_inst/O net (fo=1, routed) 2.293 11.697 MAIN_CLK_IN_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 11.788 r MAIN_CLK_IN_IBUF_BUFG_inst/O net (fo=456, routed) 1.672 13.460 iic_protocol_inst/MAIN_CLK_IN_IBUF_BUFG SLICE_X106Y79 FDCE r iic_protocol_inst/data_rd_reg[0]/C clock pessimism 0.424 13.884 clock uncertainty -0.035 13.848 SLICE_X106Y79 FDCE (Recov_fdce_C_CLR) -0.405 13.443 iic_protocol_inst/data_rd_reg[0] ------------------------------------------------------------------- required time 13.443 arrival time -8.241 ------------------------------------------------------------------- slack 5.203 Min Delay Paths -------------------------------------------------------------------------------------- Slack (MET) : 0.711ns (arrival time - required time) Source: iic_protocol_inst/reset_reg/C (rising edge-triggered cell FDPE clocked by sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Destination: iic_protocol_inst/bit_cnt_reg[0]/PRE (removal check against rising-edge clock sys_clk_pin {rise@0.000ns fall@4.000ns period=8.000ns}) Path Group: **async_default** Path Type: Removal (Min at Fast Process Corner) Requirement: 0.000ns (sys_clk_pin rise@0.000ns - sys_clk_pin rise@0.000ns) Data Path Delay: 0.672ns (logic 0.209ns (31.099%) route 0.463ns (68.901%)) Logic Levels: 1 (LUT1=1) Clock Path Skew: 0.032ns (DCD - SCD - CPR) Destination Clock Delay (DCD): 2.257ns Source Clock Delay (SCD): 1.734ns Clock Pessimism Removal (CPR): 0.490ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r K17 0.000 0.000 r MAIN_CLK_IN (IN) net (fo=0) 0.000 0.000 MAIN_CLK_IN K17 IBUF (Prop_ibuf_I_O) 0.243 0.243 r MAIN_CLK_IN_IBUF_inst/O net (fo=1, routed) 0.842 1.084 MAIN_CLK_IN_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 1.110 r MAIN_CLK_IN_IBUF_BUFG_inst/O net (fo=456, routed) 0.624 1.734 iic_protocol_inst/MAIN_CLK_IN_IBUF_BUFG SLICE_X112Y76 FDPE r iic_protocol_inst/reset_reg/C ------------------------------------------------------------------- ------------------- SLICE_X112Y76 FDPE (Prop_fdpe_C_Q) 0.164 1.898 r iic_protocol_inst/reset_reg/Q net (fo=23, routed) 0.236 2.134 iic_protocol_inst/reset_reg_n_0 SLICE_X108Y76 LUT1 (Prop_lut1_I0_O) 0.045 2.179 f iic_protocol_inst/bit_cnt[3]_i_3/O net (fo=27, routed) 0.227 2.406 iic_protocol_inst/bit_cnt[3]_i_3_n_0 SLICE_X108Y76 FDPE f iic_protocol_inst/bit_cnt_reg[0]/PRE ------------------------------------------------------------------- ------------------- (clock sys_clk_pin rise edge) 0.000 0.000 r K17 0.000 0.000 r MAIN_CLK_IN (IN) net (fo=0) 0.000 0.000 MAIN_CLK_IN K17 IBUF (Prop_ibuf_I_O) 0.431 0.431 r MAIN_CLK_IN_IBUF_inst/O net (fo=1, routed) 0.907 1.338 MAIN_CLK_IN_IBUF BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.367 r MAIN_CLK_IN_IBUF_BUFG_inst/O net (fo=456, routed) 0.890 2.257 iic_protocol_inst/MAIN_CLK_IN_IBUF_BUFG SLICE_X108Y76 FDPE r iic_protocol_inst/bit_cnt_reg[0]/C clock pessimism -0.490 1.766 SLICE_X108Y76 FDPE (Remov_fdpe_C_PRE) -0.071 1.695 iic_protocol_inst/bit_cnt_reg[0] ------------------------------------------------------------------- required time -1.695 arrival time 2.406 ------------------------------------------------------------------- slack 0.711