| Synthesis Messages - Errors, Warnings, and Infos |
New |
| WARNING Xst:2211 - "D:/XilinxISEProjects/ttd_test/calc.vhd" line 41:
Instantiating black box module <mult20x20>. |
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| WARNING Xst:819 - "D:/XilinxISEProjects/ttd_test/calc.vhd" line 60:
One or more signals are missing in the process sensitivity list. To enable
synthesis of FPGA/CPLD hardware, XST will assume that all necessary
signals are present in the sensitivity list. Please note that the result
of the synthesis may differ from the initial design specification. The
missing signals are: <num1>, <num2>, <mu1_product>,
<num3>, <num4> |
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| WARNING Xst:737 - Found 40-bit latch for signal <result12>.
Latches may be generated from incomplete case or if statements. We do not
recommend the use of latches in FPGA/CPLD designs, as they may lead to
timing problems. |
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| WARNING Xst:737 - Found 40-bit latch for signal <result34>.
Latches may be generated from incomplete case or if statements. We do not
recommend the use of latches in FPGA/CPLD designs, as they may lead to
timing problems. |
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| WARNING Xst:737 - Found 40-bit latch for signal <result>.
Latches may be generated from incomplete case or if statements. We do not
recommend the use of latches in FPGA/CPLD designs, as they may lead to
timing problems. |
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| WARNING Xst:737 - Found 20-bit latch for signal <mu1_b>. Latches
may be generated from incomplete case or if statements. We do not
recommend the use of latches in FPGA/CPLD designs, as they may lead to
timing problems. |
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| INFO Xst:2371 - HDL ADVISOR - Logic functions respectively driving the
data and gate enable inputs of this latch share common terms. This
situation will potentially lead to setup/hold violations and, as a result,
to simulation problems. This situation may come from an incomplete case
statement (all selector values are not covered). You should carefully
review if it was in your intentions to describe such a latch. |
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| WARNING Xst:737 - Found 20-bit latch for signal <mu1_a>. Latches
may be generated from incomplete case or if statements. We do not
recommend the use of latches in FPGA/CPLD designs, as they may lead to
timing problems. |
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| INFO Xst:2371 - HDL ADVISOR - Logic functions respectively driving the
data and gate enable inputs of this latch share common terms. This
situation will potentially lead to setup/hold violations and, as a result,
to simulation problems. This situation may come from an incomplete case
statement (all selector values are not covered). You should carefully
review if it was in your intentions to describe such a latch. |
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