library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity debounce_fsm is generic( MAX_CNT : integer := 40); port( clk, rst, taster : in std_logic; debounced : out std_logic); end entity debounce_fsm; architecture behavorial of debounce_fsm is type state is (IDLE, WAITING); signal current_state : state := IDLE; signal counting, endCount : std_logic := '0'; signal countval : integer range 0 to MAX_CNT := 0; begin counter : process (clk) begin if rising_edge(clk) then if countval = MAX_CNT then countval <= 0; endCount <= '1'; else endCount <= '0'; if counting = '1' then countval <= countval + 1; end if; end if; end if; end process counter; transfer_function : process (clk) begin if rising_edge(clk) then case current_state is when IDLE => if taster = '0' then current_state <= WAITING; else current_state <= IDLE; end if; when WAITING => if endCount = '1' then if taster = '1' then current_state <= IDLE; else current_state <= WAITING; end if; end if; end case; end if; end process transfer_function; output_function : process (current_state) begin case current_state is when IDLE => counting <= '0'; debounced <= '1'; when WAITING => counting <= '1'; debounced <= '0'; end case; end process output_function; end behavorial;