library IEEE; use IEEE.std_logic_1164.all; use ieee.numeric_std.all; use work.all; entity testbench is end testbench; architecture tb of testbench is constant k: natural := 4; signal a: std_logic_vector(2**k-1 downto 0); signal b: std_logic_vector(k downto 0); begin TEST: entity nbitdecoder -- generic map (k) port map (a, b); process variable c, d: integer := 0; begin report "Sie simulieren mit " & "k = " & integer'image(k); for i in 0 to 2**k loop a <= std_logic_vector(to_unsigned(c, 2**k)); wait for 1 ns; d := to_integer(unsigned(b)); assert d = i report "error " & integer'image(i) & " = " & integer'image(d); c := c + 2**i; end loop; wait; end process; end;