Iterations:        100
Instructions:      400
Total Cycles:      213
Total uOps:        800

Dispatch Width:    4
uOps Per Cycle:    3.76
IPC:               1.88
Block RThroughput: 2.0


Instruction Info:
[1]: #uOps
[2]: Latency
[3]: RThroughput
[4]: MayLoad
[5]: MayStore
[6]: HasSideEffects (U)

[1]    [2]    [3]    [4]    [5]    [6]    Instructions:
 1      5     0.50    *                   movsd	(%rdi), %xmm0
 2      10    0.50    *                   mulsd	(%rdi), %xmm0
 2      1     1.00           *            movsd	%xmm0, (%rdi)
 3      7     1.00                  U     retq


Resources:
[0]   - HWDivider
[1]   - HWFPDivider
[2]   - HWPort0
[3]   - HWPort1
[4]   - HWPort2
[5]   - HWPort3
[6]   - HWPort4
[7]   - HWPort5
[8]   - HWPort6
[9]   - HWPort7


Resource pressure per iteration:
[0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    
 -      -     0.66   0.67   1.51   1.51   1.00   0.67   1.00   0.98   

Resource pressure by instruction:
[0]    [1]    [2]    [3]    [4]    [5]    [6]    [7]    [8]    [9]    Instructions:
 -      -      -      -     0.50   0.50    -      -      -      -     movsd	(%rdi), %xmm0
 -      -     0.33   0.67   0.50   0.50    -      -      -      -     mulsd	(%rdi), %xmm0
 -      -      -      -     0.01   0.01   1.00    -      -     0.98   movsd	%xmm0, (%rdi)
 -      -     0.33    -     0.50   0.50    -     0.67   1.00    -     retq