library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all; 
library synplify;
use synplify.attributes.all;

-- input and output signals of module cam

entity cam is
port(
		sysclk:			in std_logic; 
		data_in: 		in bit_vector (7 downto 0);
		wr_adr: 		in integer range 15 downto 0;
		enable:			in std_logic;
		write:			in std_logic;
		search:			in std_logic;
		pattern_adr:		out integer range 15 downto 0;
		match:			out std_logic;
		single_match:		out std_logic;
		multiple_match:		out std_logic;
		busy:			out std_logic;
		-- Optionale Testsignale für Logic Analyzer
		t0:			out std_logic;
		t1:			out std_logic;
		t2:			out std_logic
	);

-- Zuordnung der Ein-/Ausgangssignale zu Pin- Nummern des FPGA-Bausteins LFEC1E-3T144C

-- general attribute set-up
attribute loc : string;

-- inputs
attribute loc of sysclk : signal is "9";
attribute loc of data_in : signal is ("83,82,81,79,78,76,75,74");
attribute loc of wr_adr : signal is ("141,139,137,134");
attribute loc of enable : signal is "132";
attribute loc of write : signal is "127";
attribute loc of search : signal is "130";

-- outputs
attribute loc of pattern_adr : signal is ("31,30,29,27");
attribute loc of match : signal is "32";
attribute loc of single_match : signal is "33";
attribute loc of multiple_match: signal is "34";
attribute loc of busy : signal is "57";
attribute loc of t0: signal is "59";
attribute loc of t1: signal is "61";
attribute loc of t2: signal is "64";



end cam;

-- Ende der Signalbeschreibung

-- Beschreibung der logischen Funktionen und internen Signale des Moduls cam

architecture behavior of cam is

-- data types to construct a two dimensional memory array of 16 x 8 bit
type word is array (7 downto 0) of bit;
type memory is array (15 downto 0) of word;
--type memory is array (0 to 3, 0 to 7) of bit;

-- internal signals
signal pat_buf: word;
signal rd_adr: integer range 16 downto 0;
signal match_count: integer range 15 downto 0;
signal search_cycle,enable_t0,enable_t1: std_logic;
signal sram: memory;
signal data_buffer: word;

--logic functions
begin

--connect pattern bus
pat_buf(0) <= data_in(0);
pat_buf(1) <= data_in(1);
pat_buf(2) <= data_in(2);
pat_buf(3) <= data_in(3);
pat_buf(4) <= data_in(4);
pat_buf(5) <= data_in(5);
pat_buf(6) <= data_in(6);
pat_buf(7) <= data_in(7);

--connect data bus
data_buffer(0) <= data_in(0);
data_buffer(1) <= data_in(1);
data_buffer(2) <= data_in(2);
data_buffer(3) <= data_in(3);
data_buffer(4) <= data_in(4);
data_buffer(5) <= data_in(5);
data_buffer(6) <= data_in(6);
data_buffer(7) <= data_in(7);


process (sysclk)
begin
if (sysclk'event and sysclk = '1') then	
end if;
end process;

t0 <= write;
t1 <= search;
t2 <= enable;


end behavior;