library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity clockdiv is generic ( divisor: integer := 8 ); port ( rstn: in std_logic; clk_i: in std_logic; clk_o: out std_logic ); end clockdiv; architecture behaviour of clockdiv is constant cnt_hi: integer := (divisor / 2) - 1; signal ctr: integer range 0 to cnt_hi; signal clk_out: std_logic; begin process (rstn, clk_i) is begin if rstn = '0' then clk_out <= '0'; ctr <= 0; elsif rising_edge(clk_i) then if ctr = cnt_hi then clk_out <= not clk_out; ctr <= 0; else ctr <= ctr + 1; end if; end if; clk_o <= clk_out; end process; end behaviour;