library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity down_ungleich is port ( clk : in std_logic; led : out std_logic ); end entity down_ungleich; architecture rtl of down_ungleich is constant count_max : natural := 10000000 - 1; signal count : integer range 0 to count_max := count_max; signal toggle : std_logic := '0'; begin process begin wait until rising_edge( clk); if count /= 0 then count <= count - 1; else count <= count_max; toggle <= not toggle; end if; end process; led <= toggle; end architecture rtl;