---------------------------------------------------------------------------------- -- Testbench for Audiointerface for Zedboard -- -- Stefan Scholl, DC9ST -- Microelectronic Systems Design Research Group -- TU Kaiserslautern -- 2014 ---------------------------------------------------------------------------------- -- This testbench can operate in two different modes: -- -- 1: sawtooth mode: outputs a simple sawtool signal on l and right headphone output (discards input signals) -- 2: loopback mode: line in signals are routed to the headphone output -- -- choose between the two mode by commenting the code blocks below -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. library UNISIM; use UNISIM.VComponents.all; entity audio_testbench is Port ( sysclk_p : in STD_LOGIC; -- 100 mhz master takt -- clk_100 : in STD_LOGIC; -- 100 mhz master takt sysclk_n : in STD_LOGIC; aud_adr0 : out STD_LOGIC; -- control signals to ADAU chip -- AC_ADR0 : out STD_LOGIC; -- control signals to ADAU chip aud_adr1 : out STD_LOGIC; -- AC_ADR1 : out STD_LOGIC; aud_dac_sdata : out STD_LOGIC; -- I2S MISO -- AC_GPIO0 : out STD_LOGIC; -- I2S MISO aud_adc_sdata : in STD_LOGIC; -- I2S MOSI -- AC_GPIO1 : in STD_LOGIC; -- I2S MOSI aud_bclk : in STD_LOGIC; -- I2S_bclk -- AC_GPIO2 : in STD_LOGIC; -- I2S_bclk aud_lrclk : in STD_LOGIC; -- I2S_LR -- AC_GPIO3 : in STD_LOGIC; -- I2S_LR aud_mclk : out STD_LOGIC; -- AC_MCLK : out STD_LOGIC; aud_scl : out STD_LOGIC; -- AC_SCK : out STD_LOGIC; aud_sda : inout STD_LOGIC -- AC_SDA : inout STD_LOGIC ); end audio_testbench; architecture Behavioral of audio_testbench is COMPONENT audio_top Port ( clk_48_MHz : in STD_LOGIC; clk_100_MHz : in STD_LOGIC; -- aud_adr0 : out STD_LOGIC; -- contol signals to audio chip -- AC_ADR0 : out STD_LOGIC; -- contol signals to audio chip aud_adr1 : out STD_LOGIC; -- AC_ADR1 : out STD_LOGIC; aud_dac_sdata : out STD_LOGIC; -- I2S MISO-- AC_GPIO0 : out STD_LOGIC; -- I2S MISO aud_adc_sdata : in STD_LOGIC; -- I2S MOSI-- AC_GPIO1 : in STD_LOGIC; -- I2S MOSI aud_bclk : in STD_LOGIC; -- I2S_bclk-- AC_GPIO2 : in STD_LOGIC; -- I2S_bclk aud_lrclk : in STD_LOGIC; -- I2S_LR-- AC_GPIO3 : in STD_LOGIC; -- I2S_LR aud_mclk : out STD_LOGIC; -- AC_MCLK : out STD_LOGIC; aud_scl : out STD_LOGIC; -- AC_SCK : out STD_LOGIC; aud_sda : inout STD_LOGIC; -- AC_SDA : inout STD_LOGIC; hphone_l : in STD_LOGIC_VECTOR(23 downto 0); hphone_l_valid : in std_logic; hphone_r : in STD_LOGIC_VECTOR(23 downto 0); hphone_r_valid_dummy : in std_logic; line_in_l : out STD_LOGIC_VECTOR(23 downto 0); line_in_r : out STD_LOGIC_VECTOR(23 downto 0); new_sample : out STD_LOGIC; -- goes up for 1 clk cycle if new sample is transmitted received sample_clk_48k : out std_logic -- sample clock ); END COMPONENT; --***********************30_06_2020********************************* -- create 48 MHz and 100 MHz Clock out of 100 MHz differential component clk_wiz_0 port ( clk_out1 : out std_logic; clk_out2 : out std_logic; clk_in1_p : in std_logic; clk_in1_n : in std_logic ); end component; --*************************************************************************** --*****************30_06_2020*************************************** signal s_clk_48_MHz : std_logic; -- this is the master clock of the design signal s_clk_100_MHz : std_logic; --*************************************************************************** --*************************************************************** -- signal sclk_100_MHz_buffered : std_logic := '0'; -- signal sclk_48_MHz_buffered : std_logic := '0'; --*************************************************************** -- signal counter : unsigned (5 downto 0); -- todo not needed for talkthrough 22_07_2020 signal hphone_l : std_logic_vector (23 downto 0); signal hphone_r : std_logic_vector (23 downto 0); signal hphone_valid : std_logic; signal new_sample : std_logic; signal sample_clk_48k : std_logic; signal line_in_l : std_logic_vector (23 downto 0); signal line_in_r : std_logic_vector (23 downto 0); --********************from old version********************************* -- keep signals for tracking them with the Logic Analyzer -- attribute keep : string; -- attribute keep of sample_clk_48k : signal is "true"; -- attribute keep of hphone_l : signal is "true"; -- attribute keep of hphone_r : signal is "true"; -- attribute keep of line_in_l : signal is "true"; -- attribute keep of line_in_r : signal is "true"; --********************************************************************* begin i_audio : audio_top port map( clk_48_MHz => s_clk_48_MHz, --sclk_48_MHz_buffered, --clk_48_MHz, -- todo 22_07_2020 clk_100_MHz => s_clk_100_MHz, --sclk_100_MHz_buffered, --clk_100_MHz, -- todo 22_07_2020 aud_adr0 => aud_adr0, -- AC_ADR0 => AC_ADR0, aud_adr1 => aud_adr1, -- AC_ADR1 => AC_ADR1, aud_dac_sdata => aud_dac_sdata, -- AC_GPIO0 => AC_GPIO0, aud_adc_sdata => aud_adc_sdata, -- AC_GPIO1 => AC_GPIO1, aud_bclk => aud_bclk , -- AC_GPIO2 => AC_GPIO2, aud_lrclk => aud_lrclk, -- AC_GPIO3 => AC_GPIO3, aud_mclk => aud_mclk, -- AC_MCLK => AC_MCLK, aud_scl => aud_scl, -- AC_SCK => AC_SCK, aud_sda => aud_sda, -- AC_SDA => AC_SDA, hphone_l => hphone_l, hphone_l_valid => hphone_valid, hphone_r => hphone_r, hphone_r_valid_dummy => hphone_valid, -- this valid will be discarded later line_in_l => line_in_l, line_in_r => line_in_r, new_sample => new_sample, sample_clk_48k => sample_clk_48k ); --**********************30_06_2020****************************************** clk_wiz : clk_wiz_0 port map ( -- Clock out ports clk_out1 => s_clk_48_MHz, clk_out2 => s_clk_100_MHz, -- Clock in ports clk_in1_p => sysclk_p, clk_in1_n => sysclk_n ); --**************************************************************************** --********************from old version********************************* -- use comments to switch between TEST 1 (sawtooth) and 2 (loopback) -------------------------------------------------- -- TEST 1: output sawtooth signal, discard input data -- process (clk_100) -- begin -- if (clk_100'event and clk_100 = '1') then -- hphone_valid <= '0'; -- hphone_l <= (others => '0'); -- hphone_r <= (others => '0'); -- if new_sample = '1' then -- counter <= counter + 1; -- hphone_valid <= '1'; -- hphone_l <= std_logic_vector(counter) & "000000000000000000" ; -- hphone_r <= std_logic_vector(counter) & "000000000000000000"; -- end if; -- end if; -- end process; ----------------------------------------------------- --**************************************************************************** process (s_clk_100_MHz) begin if (s_clk_100_MHz'event and s_clk_100_MHz = '1') then hphone_valid <= '0'; hphone_l <= (others => '0'); hphone_r <= (others => '0'); if new_sample = '1' then -- counter <= counter + 1; -- todo not needed for talkthrough hphone_valid <= '1'; hphone_l <= line_in_l; --(others => '0'); --> has no effect on the output (music is still there) -> itīs probably still the startup default program hphone_r <= line_in_r; --(others => '0'); --> has no effect on the output (music is still there) -> itīs probably still the startup default program end if; end if; end process; --*************************************************************************** --********************from old version********************************** -- global clock buffer for the clock signal -- BUFG_inst : BUFG -- port map -- ( -- O => clk_100_buffered, -- 1-bit output: Clock output-- O => clk_100_buffered, -- 1-bit output: Clock output -- I => clk_100 -- 1-bit input: Clock input -- ); --**********************added new BUFG************************************ -- BUFG_inst1 : BUFG -- todo 22_07_2020 -- port map -- ( -- O => sclk_100_MHz_buffered, -- 1-bit output: Clock output-- O => clk_100_buffered, -- 1-bit output: Clock output -- I => clk_100_MHz -- 1-bit input: Clock input -- ); --************************************************************************ --*********************added new BUFG*************************************** -- BUFG_inst2 : BUFG -- todo 22_07_2020 -- port map -- ( -- O => sclk_48_MHz_buffered, -- 1-bit output: Clock output-- O => clk_100_buffered, -- 1-bit output: Clock output -- I => clk_48_MHz -- 1-bit input: Clock input -- ); --************************************************************************* end Behavioral;