/*
 * Copyright 2015 Mario Richter, Peter Stephan
 * This file is part of NeMo.
 *
 * NeMo is free software: you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation, either version 3 of the License, or
 * (at your option) any later version.
 *
 * NeMo is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with NeMo.  If not, see <http://www.gnu.org/licenses/>.
 */

/*!
 * \file enc28j60.h
 * \ingroup	ethernet
 * \brief	Treiber-Routinen für den Ethernet-Chip ENC28J60 und Ansteuerung der SPI-Schnittstelle
 */

#ifndef __ENC28J60_H__
#define __ENC28J60_H__



#define EEMEM   __attribute__((section(".eeprom")))

// --------------------------------------
// ENC28J60 Konfiguration

// 0..19FF = 6656 Bytes Empfangspuffer
#define ENC_MEM_RX_START				0x0000						//!< Startadresse des Empfangsbuffers des ENC28J60
#define ENC_MEM_RX_END					0x19FF						//!< Endadresse des Empfangsbuffers des ENC28J60

// 1A00..1FFF = 1536 Bytes Sendepuffer
#define ENC_MEM_TX_START				0x1A00						//!< Startadresse des Sendebuffers des ENC28J60
#define ENC_MEM_TX_END					0x1FFF						//!< Endadresse des Sendebuffers des ENC28J60

//! Full Duplex Mode (auskommentieren für Half Duplex Mode)
#define ENC_FULL_DUPLEX

//! Maximale Framelänge in Bytes
#define ENC_MAX_FRAMELEN				1518

// MAC-Adresse
#define ENC_MAC_ADDRESS1				0x00			        //!< MAC-Adresse (Byte 1, <47:40>)
#define ENC_MAC_ADDRESS2				0x0B			        //!< MAC-Adresse (Byte 2, <39:32>)
#define ENC_MAC_ADDRESS3				0x6A			        //!< MAC-Adresse (Byte 3, <31:24>)
#define ENC_MAC_ADDRESS4			  0x16			        //!< MAC-Adresse (Byte 4, <23:16>)
#define ENC_MAC_ADDRESS5				0xCA			        //!< MAC-Adresse (Byte 5, <15:8>)
#define ENC_MAC_ADDRESS6  			0x72			        //!< MAC-Adresse (Byte 6, <7:0>)

// --------------------------------------
// Portpins für die SPI-Kommunikation zum ENC28J60

#define ENC_PORT							  PORTB							//!< Controllerport, an dem der ENC28J60 angeschlossen ist
#define ENC_PIN								  PINB							//!< PIN-Register für die Ports zum ENC28J60
#define ENC_DDR								  DDRB							//!< DDR-Register für die Ports zum ENC28J60

#define ENC_PIN_CS							PB0								//!< Chip Select für ENC28J60
#define ENC_PIN_SCK							PB1								//!< Serial Clock für ENC28J60
#define ENC_PIN_SO							PB3								//!< Dateneingang vom ENC28J60 (ENC -> ATmega)
#define ENC_PIN_SI							PB2								//!< Datenausgang zum ENC28J60 (ENC <- ATmega)

// --------------------------------------
// Interrupt des INT-Pins

#define ETH_INTERRUPT_ENABLE()	(PCMSK3 |=  (1 << PCINT31))					      //!< INT-Pin-Interrupt freigeben
#define ETH_INTERRUPT_DISABLE()	(PCMSK3 &= ~(1 << PCINT31))								//!< INT-Pin-Interrupt deaktivieren
#define ETH_INTERRUPT_ACTIVE		!(PIND & (1 << PIND7))			          //!< Abfrage auf aktiven Interrupt

// --------------------------------------
// Chip Select-Makros

#define ENC_CS_ACTIVE()					(ENC_PORT &= ~(1 << ENC_PIN_CS))			//!< Chip Select des ENC28J60 aktivieren
#define ENC_CS_INACTIVE()				(ENC_PORT |=  (1 << ENC_PIN_CS))			//!< Chip Select des ENC28J60 deaktivieren

// --------------------------------------
// Funktionsdeklarationen

void enc28Init(void);
uint16_t enc28GetPacket(uint8_t * buf);
void enc28SendPacket(uint8_t * buf, uint16_t length);

void enc28ReadBufferMem(uint8_t *, uint16_t);
void enc28WriteBufferMem(uint8_t *, uint16_t);
uint8_t enc28ReadControlReg(uint8_t);
void enc28WriteControlReg(uint8_t, uint8_t);
uint16_t enc28ReadPhyReg(uint8_t);
void enc28WritePhyReg(uint8_t, uint16_t);
void enc28BitFieldSet(uint8_t, uint8_t);
void enc28BitFieldClear(uint8_t, uint8_t);
void enc28SoftwareReset(void);
void enc28SetBank(uint8_t);

void spiInit(void);
void spiWrite(uint8_t);
uint8_t spiRead(void);

void printMem(uint8_t *, uint16_t);


// --------------------------------------
// Globale Variablen

extern uint8_t       myMacAddr[];
extern uint8_t EEMEM  eeMacAddr[];

// ENC28J60-Registeradressen
// --------------------------------------
// 	Bits 8 und 7: 	Bankadresse
// 	Bit 6: 					MAC- oder MII-Register (benötigen zusätzlichen SPI-Lesezyklus)
// --------------------------------------

// -------------- BANK 0 --------------

#define ENC_ADR_ERDPTL					(0x00 | 0x00)			//!< ERDPTL: Read Pointer Low Byte <7:0>
#define ENC_ADR_ERDPTH					(0x00 | 0x01)			//!< ERDPTH: Read Pointer High Byte <12:8>
#define ENC_ADR_EWRPTL					(0x00 | 0x02)			//!< EWRPTL: Write Pointer Low Byte <7:0>
#define ENC_ADR_EWRPTH					(0x00 | 0x03)			//!< EWRPTH: Write Pointer High Byte <12:8>
#define ENC_ADR_ETXSTL					(0x00 | 0x04)			//!< ETXSTL: TX Start Low Byte <7:0>
#define ENC_ADR_ETXSTH					(0x00 | 0x05)			//!< ETXSTH: TX Start High Byte <12:8>
#define ENC_ADR_ETXNDL					(0x00 | 0x06)			//!< ETXNDL: TX End Low Byte <7:0>
#define ENC_ADR_ETXNDH					(0x00 | 0x07)			//!< ETXNDH: TX End High Byte <12:8>
#define ENC_ADR_ERXSTL					(0x00 | 0x08)			//!< ERXSTL: RX Start Low Byte <7:0>
#define ENC_ADR_ERXSTH					(0x00 | 0x09)			//!< ERXSTH: RX Start High Byte <12:8>
#define ENC_ADR_ERXNDL					(0x00 | 0x0A)			//!< ERXNDL: RX End Low Byte <7:0>
#define ENC_ADR_ERXNDH					(0x00 | 0x0B)			//!< ERXNDH: RX End High Byte <12:8>
#define ENC_ADR_ERXRDPTL  			(0x00 | 0x0C)			//!< ERXRDPTL: RX Read Pointer Low Byte <7:0>
#define ENC_ADR_ERXRDPTH				(0x00 | 0x0D)			//!< ERXRDPTH: RX Read Pointer High Byte <12:8>
#define ENC_ADR_ERXWRPTL  			(0x00 | 0x0E)			//!< ERXWRPTL: RX Write Pointer Low Byte <7:0>
#define ENC_ADR_ERXWRPTH				(0x00 | 0x0F)			//!< ERXWRPTH: RX Write Pointer High Byte <12:8>
#define ENC_ADR_EDMASTL					(0x00 | 0x10)			//!< EDMASTL: DMA Start Low Byte <7:0>
#define ENC_ADR_EDMASTH					(0x00 | 0x11)			//!< EDMASTH: DMA Start High Byte <12:8>
#define ENC_ADR_EDMANDL					(0x00 | 0x12)			//!< EDMANDL: DMA End Low Byte <7:0>
#define ENC_ADR_EDMANDH					(0x00 | 0x13)			//!< EDMANDH: DMA End High Byte <12:8>
#define ENC_ADR_EDMADSTL				(0x00 | 0x14)			//!< EDMADSTL: DMA Destination Low Byte <7:0>
#define ENC_ADR_EDMADSTH				(0x00 | 0x15)			//!< EDMADSTH: DMA Destination High Byte <12:8>
#define ENC_ADR_EDMACSL					(0x00 | 0x16)			//!< EDMACSL: DMA Checksum Low Byte <7:0>
#define ENC_ADR_EDMACSH					(0x00 | 0x17)			//!< EDMACSH: DMA Checksum High Byte <15:8>

// Folgende Register sind in jeder Bank vorhanden, bedürfen also keiner Bankumschaltung.

#define ENC_ADR_EIE							(0x00 | 0x1B)			//!< EIE: Interrupt Enable Register
 #define ENC_BIT_INTIE						7								//!< EIE-INTIE <7>: Global INT Interrupt Enable Bit
 #define ENC_BIT_PKTIE						6								//!< EIE-PKTIE <6>: Receive Packet Pending Interrupt Enable Bit
 #define ENC_BIT_DMAIE						5								//!< EIE-DMAIE <5>: DMA Interrupt Enable Bit
 #define ENC_BIT_LINKIE						4								//!< EIE-LINKIE <4>: Link Status Change Interrupt Enable Bit
 #define ENC_BIT_TXIE						  3								//!< EIE-TXIE <3>: Transmit Interrupt Enable Bit
 #define ENC_BIT_TXERIE						1								//!< EIE-TXERIE <1>: Transmit Error Interrupt Enable Bit
 #define ENC_BIT_RXERIE						0								//!< EIE-RXERIE <0>: Receive Error Interrupt Enable Bit 
 
#define ENC_ADR_EIR							(0x00 | 0x1C)			//!< EIR: Interrupt Request (Flag) Register
 #define ENC_BIT_PKTIF            6               //!< EIR-PKTIF <6>: Receive Packet Pending Interrupt Flag
 #define ENC_BIT_DMAIF            5               //!< EIR-DMAIF <5>: DMA Interrupt Flag
 #define ENC_BIT_LINKIF           4               //!< EIR-LINKIF <4>: Link Status Change Interrupt Flag
 #define ENC_BIT_TXIF             3               //!< EIR-TXIF <3>: Transmit Interrupt Flag
 #define ENC_BIT_TXERIF           1               //!< EIR-TXERIF <1>: Transmit Error Interrupt Flag
 #define ENC_BIT_RXERIF           0               //!< EIR-RXERIF <0>: Receive Error Interrupt Flag

#define ENC_ADR_ESTAT						(0x00 | 0x1D)			//!< ESTAT: Ethernet Status Register
 #define ENC_BIT_CLKRDY						0  							//!< ESTAT-CLKRDY <0>: Clock ready bit
 
#define ENC_ADR_ECON2						(0x00 | 0x1E)			//!< ECON2: Ethernet Control Register 2
 #define ENC_BIT_AUTOINC					7								//!< ECON2-AUTOINC <7>: Automatic Buffer Pointer Increment Enable Bit
 #define ENC_BIT_PKTDEC 					6								//!< ECON2-PKTDEC <6>: Packet Decrement Bit
 #define ENC_BIT_PWRSV			  		5								//!< ECON2-PWRSV <5>: Power Save Enable Bit
 #define ENC_BIT_VRPS				    	3								//!< ECON2-VRPS <3>: Voltage Regulator Power Save Enable Bit
 
#define ENC_ADR_ECON1						(0x00 | 0x1F)			//!< ECON1: Ethernet Control Register 1
 #define ENC_BIT_TXRST  		    	7								//!< ECON1-TXRST <3>: Transmit Logic Reset Bit
 #define ENC_BIT_RXRST			    	6								//!< ECON1-RXRST <6>: Receive Logic Reset Bit
 #define ENC_BIT_DMAST				   	5								//!< ECON1-DMAST <5>: DMA Start and Busy Bit
 #define ENC_BIT_CSUMEN				    4								//!< ECON1-CSUMEN <4>: DMA Checksum Enable Bit
 #define ENC_BIT_TXRTS				    3								//!< ECON1-TXRTS <3>: Transmit Request to Send Bit
 #define ENC_BIT_RXEN				    	2								//!< ECON1-RXEN <2>: Receiver Enable Bit
 #define ENC_BIT_BSEL0			    	3								//!< ECON1-BSEL <1-0>: Bank Select Bits


// -------------- BANK 1 --------------

#define ENC_ADR_EHT0						(0x40 | 0x00)			//!< EHT0: Hash Table Byte 0 <7:0>
#define ENC_ADR_EHT1						(0x40 | 0x01)			//!< EHT1: Hash Table Byte 1 <15:8>
#define ENC_ADR_EHT2						(0x40 | 0x02)			//!< EHT2: Hash Table Byte 2 <23:16>
#define ENC_ADR_EHT3						(0x40 | 0x03)			//!< EHT3: Hash Table Byte 3 <31:24>
#define ENC_ADR_EHT4						(0x40 | 0x04)			//!< EHT4: Hash Table Byte 4 <39:32>
#define ENC_ADR_EHT5						(0x40 | 0x05)			//!< EHT5: Hash Table Byte 5 <47:40>
#define ENC_ADR_EHT6						(0x40 | 0x06)			//!< EHT6: Hash Table Byte 6 <55:48>
#define ENC_ADR_EHT7						(0x40 | 0x07)			//!< EHT7: Hash Table Byte 7 <63:56>
#define ENC_ADR_EPMM0						(0x40 | 0x08)			//!< EPMM0: Pattern Match Mask Byte 0 <7:0>
#define ENC_ADR_EPMM1						(0x40 | 0x09)			//!< EPMM1: Pattern Match Mask Byte 1 <15:8>
#define ENC_ADR_EPMM2						(0x40 | 0x0A)			//!< EPMM2: Pattern Match Mask Byte 2 <23:16>
#define ENC_ADR_EPMM3						(0x40 | 0x0B)			//!< EPMM3: Pattern Match Mask Byte 3 <31:24>
#define ENC_ADR_EPMM4						(0x40 | 0x0C)			//!< EPMM4: Pattern Match Mask Byte 4 <39:32>
#define ENC_ADR_EPMM5						(0x40 | 0x0D)			//!< EPMM5: Pattern Match Mask Byte 5 <47:40>
#define ENC_ADR_EPMM6						(0x40 | 0x0E)			//!< EPMM6: Pattern Match Mask Byte 6 <55:48>
#define ENC_ADR_EPMM7						(0x40 | 0x0F)			//!< EPMM7: Pattern Match Mask Byte 7 <63:56>
#define ENC_ADR_EPMCSL					(0x40 | 0x10)			//!< EPMCSL: Pattern Match Checksum Low Byte <7:0>
#define ENC_ADR_EPMCSH					(0x40 | 0x11)			//!< EPMCSH: Pattern Match Checksum High Byte <15:8>
#define ENC_ADR_EPMOL 					(0x40 | 0x14)			//!< EPMOL: Pattern Match Offset Low Byte <7:0>
#define ENC_ADR_EPMOH 					(0x40 | 0x15)			//!< EPMOH: Pattern Match Offset High Byte <12:8>
#define ENC_ADR_ERXFCON					(0x40 | 0x18)			//!< ERXFCON: Ethernet Receive Filter Control Register
#define ENC_ADR_EPKTCNT					(0x40 | 0x19)			//!< EPKTCNT: Ethernet Packet Count

// -------------- BANK 2 --------------

#define ENC_ADR_MACON1					(0xA0 | 0x00)			//!< MACON1: MAC Control Register 1
 #define ENC_BIT_TXPAUS						3								//!< MACON1-TXPAUS <3>: Pause Control Frame Transmission Enable Bit
 #define ENC_BIT_RXPAUS						2								//!< MACON1-RXPAUS <2>: Pause Control Frame Reception Enable Bit
 #define ENC_BIT_PASSALL					1								//!< MACON1-PASSALL <1>: Pass ALl Received Frame Enable Bit
 #define ENC_BIT_MARXEN						0								//!< MACON1-MARXEN <0>: MAC Receive Enable Bit
 
#define ENC_ADR_MACON3					(0xA0 | 0x02)			//!< MACON3: MAC Control Register 3
 #define ENC_BIT_PADCFG0					5								//!< MACON3-PADCFG0 <7:5>: Automatic PAD and CRC Configuration Bits
 #define ENC_BIT_TXCRCEN					4								//!< MACON3-TXCRCEN <4>: Transmit CRC Enable Bit
 #define ENC_BIT_PHDREN 					3								//!< MACON3-PHDREN <3>: Proprietary Header Enable Bit
 #define ENC_BIT_HFRMEN						2								//!< MACON3-HFRMEN <2>: Huge Frame Enable Bit
 #define ENC_BIT_FRMLNEN					1								//!< MACON3-FRMLNEN <1>: Frame Length Checking Enable Bit
 #define ENC_BIT_FULDPLX					0								//!< MACON3-FULDPLX <0>: MAC Full Duplex Enable Bit

#define ENC_ADR_MACON4					(0xA0 | 0x03)			//!< MACON3: MAC Control Register 4
 #define ENC_BIT_DEFER  					6								//!< MACON3-DEFER <6>: Defer Transmission Enable Bit
 #define ENC_BIT_BPEN					    5								//!< MACON3-BPEN <5>: No Backoff During Backpressure Enable Bit
 #define ENC_BIT_NOBKOFF					4								//!< MACON3-NOBKOFF <4>: No Backoff Enable Bit

#define ENC_ADR_MABBIPG					(0xA0 | 0x04)			//!< MABBIPG: MAC Back-to-Back Inter-Packet Gap <6:0>
#define ENC_ADR_MAIPGL					(0xA0 | 0x06)			//!< MABIPGL: MAC Non-Back-to-Back Inter-Packet Gap Low Byte <6:0>
#define ENC_ADR_MAIPGH					(0xA0 | 0x07)			//!< MABIPGH: MAC Non-Back-to-Back Inter-Packet Gap High Byte <6:0>
#define ENC_ADR_MACLCON1				(0xA0 | 0x08)			//!< MACLCON1: Retransmission Maximum <3:0>
#define ENC_ADR_MACLCON2				(0xA0 | 0x09)			//!< MACLCON2: Collision Window <5:0>
#define ENC_ADR_MAMXFLL 				(0xA0 | 0x0A)			//!< MAMXFLL: Maximum Frame Length Low Byte <7:0>
#define ENC_ADR_MAMXFLH 				(0xA0 | 0x0B)			//!< MAMXFLH: Maximum Frame Length High Byte <7:0>

#define ENC_ADR_MICMD 					(0xA0 | 0x12)			//!< MICMD: MII Command Register
 #define ENC_BIT_MIISCAN					1								//!< MICMD-MIISCAN <1>: MII Scan Enable Bit
 #define ENC_BIT_MIIRD						0								//!< MICMD-MIIRD <0>: MII Read Enable Bit
 
#define ENC_ADR_MIREGADR				(0xA0 | 0x14)			//!< MIREGADR: MII Register Address
#define ENC_ADR_MIWRL						(0xA0 | 0x16)			//!< MIWRL: MII Write Data Low Byte <7:0>
#define ENC_ADR_MIWRH						(0xA0 | 0x17)			//!< MIWRH: MII Write Data High Byte <15:8>
#define ENC_ADR_MIRDL						(0xA0 | 0x18)			//!< MIRDL: MII Read Data Low Byte <7:0>
#define ENC_ADR_MIRDH						(0xA0 | 0x19)			//!< MIRDH: MII Read Data High Byte <15:8>

// -------------- BANK 3 --------------

#define ENC_ADR_MAADR5					(0xE0 | 0x00)			//!< MAADR5: MAC Address Byte 5 <15:8>
#define ENC_ADR_MAADR6					(0xE0 | 0x01)			//!< MAADR6: MAC Address Byte 6 <7:0>
#define ENC_ADR_MAADR3					(0xE0 | 0x02)			//!< MAADR3: MAC Address Byte 3 <31:24>, OUI Byte 3
#define ENC_ADR_MAADR4					(0xE0 | 0x03)			//!< MAADR4: MAC Address Byte 4 <23:16>
#define ENC_ADR_MAADR1					(0xE0 | 0x04)			//!< MAADR1: MAC Address Byte 1 <47:40>, OUI Byte 1
#define ENC_ADR_MAADR2					(0xE0 | 0x05)			//!< MAADR2: MAC Address Byte 2 <39:32>, OUI Byte 2
#define ENC_ADR_EBSTSD					(0xC0 | 0x06)			//!< EBSTSD: Built-in Self-Test Fill Seed <7:0>
#define ENC_ADR_EBSTCON					(0xC0 | 0x07)			//!< EBSTCON: Ethernet Self-Test Control Register
#define ENC_ADR_EBSTCSL					(0xC0 | 0x08)			//!< EBSTCSL: Built-in Self-Test Checksum Low Byte <7:0>
#define ENC_ADR_EBSTCSH					(0xC0 | 0x09)			//!< EBSTCSH: Built-in Self-Test Checksum High Byte <15:8>

#define ENC_ADR_MISTAT					(0xE0 | 0x0A)			//!< MISTAT: MII Status Register
 #define ENC_BIT_NVALID						2								//!< MISTAT-NVALID <2>: MII Management Read Data Not Valid Bit
 #define ENC_BIT_SCAN 						1								//!< MISTAT-SCAN <1>: MII Management Scan Operation Bit
 #define ENC_BIT_BUSY 						0								//!< MISTAT-BUSY <0>: MII Management Busy Bit

#define ENC_ADR_EREVID					(0xC0 | 0x12)			//!< EREVID: Ethernet Revision ID <4:0>
#define ENC_ADR_ECOCON					(0xC0 | 0x15)			//!< ECOCON: Clock Output Control Register
#define ENC_ADR_EFLOCON					(0xC0 | 0x17)			//!< EFLOCON: Ethernet Flow Control Register
#define ENC_ADR_EPAUSL					(0xC0 | 0x18)			//!< EPAUSL: Pause Timer Value Low Byte <7:0>
#define ENC_ADR_EPAUSH					(0xC0 | 0x19)			//!< EPAUSH: Pause Timer Value High Byte <15:8>

// --------------------------------------
// PHY-Register

#define ENC_ADR_PHCON1					0x00							//!< PHCON1: PHY Control Register 1
 #define ENC_BIT_PRST							15							//!< PHCON1-PRST <15>: PHY Software Reset Bit
 #define ENC_BIT_PLOOPBK					14							//!< PHCON1-PLOOPBK <14>: PHY Loopback Bit
 #define ENC_BIT_PPWRSV						11							//!< PHCON1-PPWRSV <11>: PHY Power-Down Bit
 #define ENC_BIT_PDPXMD						8 							//!< PHCON1-PDPXMD <8>: PHY Duplex Mode Bit

#define ENC_ADR_PHSTAT1					0x01							//!< PHSTAT1: Physical Layer Status Register 1
 #define ENC_BIT_PFDPX						12							//!< PHSTAT1-PFDPX <12>: PHY Full-Duplex Capable Bit
 #define ENC_BIT_PHDPX						11							//!< PHSTAT1-PHDPX <12>: PHY Half-Duplex Capable Bit
 #define ENC_BIT_LLSTAT						2							  //!< PHSTAT1-LLSTAT <2>: PHY Latching Link Status Bit
 #define ENC_BIT_JBSTAT						1 							//!< PHSTAT1-JBSTAT <1>: PHY Latching Jabber Status Bit

#define ENC_ADR_PHID1						0x02							//!< PHID1: PHY Identifier Register 1
#define ENC_ADR_PHID2						0x03							//!< PHID2: PHY Identifier Register 2

#define ENC_ADR_PHCON2					0x10							//!< PHCON1: PHY Control Register 2
 #define ENC_BIT_FRCLNK						14							//!< PHCON2-FRCLNK <14>: PHY Force Linkup Bit
 #define ENC_BIT_TXDIS						13							//!< PHCON2-TXDIS <13>: Twisted-Pair Transmitter Disable Bit
 #define ENC_BIT_JABBER						10						  //!< PHCON2-JABBER <10>: Jabber Correction Disable Bit
 #define ENC_BIT_HDLDIS						8  							//!< PHCON2-HDLDIS <8>: PHY Half-Duplex Loopback Disable Bit
 
#define ENC_ADR_PHSTAT2					0x11							//!< PHSTAT2: Physical Layer Status Register 2
 #define ENC_BIT_TXSTAT						13							//!< PHSTAT2-TXSTAT <13>: PHY Transmit Status Bit
 #define ENC_BIT_RXSTAT						12							//!< PHSTAT2-RXSTAT <12>: PHY Receive Status Bit
 #define ENC_BIT_COLSTAT					11							//!< PHSTAT2-COLSTAT <11>: PHY Collision Status Bit
 #define ENC_BIT_LSTAT						10							//!< PHSTAT2-LSTAT <10>: PHY Link Status Bit
 #define ENC_BIT_DPXSTAT					9							  //!< PHSTAT2-DPXSTAT <9>: PHY Duplex Status Bit
 #define ENC_BIT_PLRITY 					5							  //!< PHSTAT2-PLRITY <5>: Polarity Status Bit

#define ENC_ADR_PHIE						0x12							//!< PHIE: PHY Interrupt Enable Register
 #define ENC_BIT_PLNKIE						4								//!< PHIE-PLNKIE <4>: PHY Link Change Interrupt Enable Bit
 #define ENC_BIT_PGEIE		 				1								//!< PHIE-PLNKIE <4>: PHY Global Interrupt Enable Bit

#define ENC_ADR_PHIR						0x13							//!< PHIR: PHY Interrupt Request (Flag) Register
 #define ENC_BIT_PLNKIF						4								//!< PHIR-PLNKIF <4>: PHY Link Change Interrupt Flag Bit
 #define ENC_BIT_PGIF 		 				2								//!< PHIR-PGIF <2>: PHY Global Interrupt Flag Bit

#define ENC_ADR_PHLCON					0x14							//!< PHLCON: PHY Module LED Control Register
 #define ENC_BIT_LACFG0						8								//!< PHLCON-LACFG3..0 <11..8>: LED A Configuration Bits
 #define ENC_BIT_LBCFG0						4								//!< PHLCON-LBCFG3..0 <7..4>: LED B Configuration Bits
 #define ENC_BIT_LFRQ0						2								//!< PHLCON-LFRQ1..0 <3..2>: LED Pulse Stretch Time Configuration Bits
 #define ENC_BIT_STRCH						1								//!< PHLCON-STRCH <1>: LED Pulse Stretching Enable Bit

// --------------------------------------
// Registermasken

#define ENC_REG_ADDR_MASK				0x1F							//!< Maske für die Registeradresse der Kontrollregister
#define ENC_BANK_ADDR_MASK			0xC0							//!< Maske für die Bankadresse der Kontrollregister
#define ENC_MAC_MII_MASK				0x20							//!< Maske für MAC- und MII-Register (benötigen zusätzlichen SPI-Lesezyklus)
#define ENC_BANK_ADDR_SHIFT			6									//!< Breite des Shifts für Bankadresse, passend zu ECON1
#define ENC_ECON1_BSEL_MASK			0x03							//!< Maske für die Bank Select-Bits im ECON1-Register

// --------------------------------------
// SPI-Befehle

#define ENC_SPI_RCR							0x00							//!< SPI-Befehl: Read Control Register
#define ENC_SPI_RBM							0x20							//!< SPI-Befehl: Read Buffer Memory
#define ENC_SPI_WCR							0x40							//!< SPI-Befehl: Write Control Register
#define ENC_SPI_WBM							0x60							//!< SPI-Befehl: Write Buffer Memory
#define ENC_SPI_BFS							0x80							//!< SPI-Befehl: Bit Field Set
#define ENC_SPI_BFC							0xA0							//!< SPI-Befehl: Bit Field Clear
#define ENC_SPI_SRC							0xE0							//!< SPI-Befehl: System Reset Command


#endif
