
Slave_Test_AT8.elf:     file format elf32-avr

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         000003e2  00000000  00000000  00000094  2**1
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .data         00000014  00800060  000003e2  00000476  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  2 .bss          00000002  00800074  00800074  0000048a  2**0
                  ALLOC
  3 .comment      00000030  00000000  00000000  0000048a  2**0
                  CONTENTS, READONLY
  4 .note.gnu.avr.deviceinfo 0000003c  00000000  00000000  000004bc  2**2
                  CONTENTS, READONLY
  5 .debug_aranges 000001b8  00000000  00000000  000004f8  2**0
                  CONTENTS, READONLY, DEBUGGING
  6 .debug_info   00001be9  00000000  00000000  000006b0  2**0
                  CONTENTS, READONLY, DEBUGGING
  7 .debug_abbrev 00000ac5  00000000  00000000  00002299  2**0
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_line   00000dd3  00000000  00000000  00002d5e  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_frame  000004a4  00000000  00000000  00003b34  2**2
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_str    0000071e  00000000  00000000  00003fd8  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_loc    000010e1  00000000  00000000  000046f6  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_ranges 00000178  00000000  00000000  000057d7  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

00000000 <__vectors>:
   0:	12 c0       	rjmp	.+36     	; 0x26 <__ctors_end>
   2:	77 c0       	rjmp	.+238    	; 0xf2 <__vector_1>
   4:	2b c0       	rjmp	.+86     	; 0x5c <__bad_interrupt>
   6:	2a c0       	rjmp	.+84     	; 0x5c <__bad_interrupt>
   8:	29 c0       	rjmp	.+82     	; 0x5c <__bad_interrupt>
   a:	28 c0       	rjmp	.+80     	; 0x5c <__bad_interrupt>
   c:	27 c0       	rjmp	.+78     	; 0x5c <__bad_interrupt>
   e:	26 c0       	rjmp	.+76     	; 0x5c <__bad_interrupt>
  10:	25 c0       	rjmp	.+74     	; 0x5c <__bad_interrupt>
  12:	5e c0       	rjmp	.+188    	; 0xd0 <__vector_9>
  14:	23 c0       	rjmp	.+70     	; 0x5c <__bad_interrupt>
  16:	22 c0       	rjmp	.+68     	; 0x5c <__bad_interrupt>
  18:	21 c0       	rjmp	.+66     	; 0x5c <__bad_interrupt>
  1a:	20 c0       	rjmp	.+64     	; 0x5c <__bad_interrupt>
  1c:	1f c0       	rjmp	.+62     	; 0x5c <__bad_interrupt>
  1e:	1e c0       	rjmp	.+60     	; 0x5c <__bad_interrupt>
  20:	1d c0       	rjmp	.+58     	; 0x5c <__bad_interrupt>
  22:	1c c0       	rjmp	.+56     	; 0x5c <__bad_interrupt>
  24:	1b c0       	rjmp	.+54     	; 0x5c <__bad_interrupt>

00000026 <__ctors_end>:
  26:	11 24       	eor	r1, r1
  28:	1f be       	out	0x3f, r1	; 63
  2a:	cf e5       	ldi	r28, 0x5F	; 95
  2c:	d4 e0       	ldi	r29, 0x04	; 4
  2e:	de bf       	out	0x3e, r29	; 62
  30:	cd bf       	out	0x3d, r28	; 61

00000032 <__do_copy_data>:
  32:	10 e0       	ldi	r17, 0x00	; 0
  34:	a0 e6       	ldi	r26, 0x60	; 96
  36:	b0 e0       	ldi	r27, 0x00	; 0
  38:	e2 ee       	ldi	r30, 0xE2	; 226
  3a:	f3 e0       	ldi	r31, 0x03	; 3
  3c:	02 c0       	rjmp	.+4      	; 0x42 <__SREG__+0x3>
  3e:	05 90       	lpm	r0, Z+
  40:	0d 92       	st	X+, r0
  42:	a4 37       	cpi	r26, 0x74	; 116
  44:	b1 07       	cpc	r27, r17
  46:	d9 f7       	brne	.-10     	; 0x3e <__SP_H__>

00000048 <__do_clear_bss>:
  48:	20 e0       	ldi	r18, 0x00	; 0
  4a:	a4 e7       	ldi	r26, 0x74	; 116
  4c:	b0 e0       	ldi	r27, 0x00	; 0
  4e:	01 c0       	rjmp	.+2      	; 0x52 <.do_clear_bss_start>

00000050 <.do_clear_bss_loop>:
  50:	1d 92       	st	X+, r1

00000052 <.do_clear_bss_start>:
  52:	a6 37       	cpi	r26, 0x76	; 118
  54:	b2 07       	cpc	r27, r18
  56:	e1 f7       	brne	.-8      	; 0x50 <.do_clear_bss_loop>
  58:	02 d0       	rcall	.+4      	; 0x5e <main>
  5a:	c1 c1       	rjmp	.+898    	; 0x3de <_exit>

0000005c <__bad_interrupt>:
  5c:	d1 cf       	rjmp	.-94     	; 0x0 <__vectors>

0000005e <main>:
#include "RS232.h"

volatile uint8_t timercounter;

int main(void)
{
  5e:	cf 93       	push	r28
  60:	df 93       	push	r29
  62:	cd b7       	in	r28, 0x3d	; 61
  64:	de b7       	in	r29, 0x3e	; 62
  66:	60 97       	sbiw	r28, 0x10	; 16
  68:	0f b6       	in	r0, 0x3f	; 63
  6a:	f8 94       	cli
  6c:	de bf       	out	0x3e, r29	; 62
  6e:	0f be       	out	0x3f, r0	; 63
  70:	cd bf       	out	0x3d, r28	; 61
	uint8_t payload[wl_module_PAYLOAD];		//Array for Payload
	uint8_t maincounter =0;
	uint8_t k;
	uart_init();
  72:	94 d0       	rcall	.+296    	; 0x19c <uart_init>
	wl_module_init();	//initialise nRF24L01+ Module
  74:	d0 d0       	rcall	.+416    	; 0x216 <wl_module_init>
	#else
		//round up by default
		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
	#endif

	__builtin_avr_delay_cycles(__ticks_dc);
  76:	8f e0       	ldi	r24, 0x0F	; 15
  78:	97 e2       	ldi	r25, 0x27	; 39
  7a:	01 97       	sbiw	r24, 0x01	; 1
  7c:	f1 f7       	brne	.-4      	; 0x7a <main+0x1c>
  7e:	00 c0       	rjmp	.+0      	; 0x80 <main+0x22>
  80:	00 00       	nop
	_delay_ms(50);		//wait for nRF24L01+ Module

	sei();
  82:	78 94       	sei

	wl_module_tx_config(wl_module_TX_NR_0);		//Config Module
  84:	80 e0       	ldi	r24, 0x00	; 0
  86:	f8 d0       	rcall	.+496    	; 0x278 <wl_module_tx_config>
//wl_module_config();
	TCCR0 |= ( (1<<CS02) | (1<<CS00));		//Prescaler auf 1024 ATMEGA8
  88:	83 b7       	in	r24, 0x33	; 51
  8a:	85 60       	ori	r24, 0x05	; 5
  8c:	83 bf       	out	0x33, r24	; 51
	TIMSK |= ( (1<<TOIE0));					//enable TOVF ATMEGA8
  8e:	89 b7       	in	r24, 0x39	; 57
  90:	81 60       	ori	r24, 0x01	; 1
  92:	89 bf       	out	0x39, r24	; 57
#include "RS232.h"

volatile uint8_t timercounter;

int main(void)
{
  94:	10 e0       	ldi	r17, 0x00	; 0
	TIMSK |= ( (1<<TOIE0));					//enable TOVF ATMEGA8

	
    while(1)
    {
		if (timercounter >= 30)			//30 entspricht ~1 Sekunde bei 8MHz
  96:	80 91 74 00 	lds	r24, 0x0074	; 0x800074 <__data_end>
  9a:	8e 31       	cpi	r24, 0x1E	; 30
  9c:	e0 f3       	brcs	.-8      	; 0x96 <main+0x38>
			{
				timercounter = 0;
  9e:	10 92 74 00 	sts	0x0074, r1	; 0x800074 <__data_end>
  a2:	fe 01       	movw	r30, r28
  a4:	31 96       	adiw	r30, 0x01	; 1
			
				
				for (k=0; k<=wl_module_PAYLOAD-1; k++)
  a6:	80 e0       	ldi	r24, 0x00	; 0
				{
					payload[k] = k;
  a8:	81 93       	st	Z+, r24
		if (timercounter >= 30)			//30 entspricht ~1 Sekunde bei 8MHz
			{
				timercounter = 0;
			
				
				for (k=0; k<=wl_module_PAYLOAD-1; k++)
  aa:	8f 5f       	subi	r24, 0xFF	; 255
  ac:	80 31       	cpi	r24, 0x10	; 16
  ae:	e1 f7       	brne	.-8      	; 0xa8 <main+0x4a>
				{
					payload[k] = k;
				}
			
				payload[0] = maincounter;
  b0:	19 83       	std	Y+1, r17	; 0x01
				payload[1] = maincounter+1;				
  b2:	1f 5f       	subi	r17, 0xFF	; 255
  b4:	1a 83       	std	Y+2, r17	; 0x02
			uart_puts("r");
  b6:	80 e6       	ldi	r24, 0x60	; 96
  b8:	90 e0       	ldi	r25, 0x00	; 0
  ba:	7d d0       	rcall	.+250    	; 0x1b6 <uart_puts>
				wl_module_send(payload,wl_module_PAYLOAD);
  bc:	60 e1       	ldi	r22, 0x10	; 16
  be:	ce 01       	movw	r24, r28
  c0:	01 96       	adiw	r24, 0x01	; 1
  c2:	60 d1       	rcall	.+704    	; 0x384 <wl_module_send>
				
				maincounter++;
				if (maincounter >250)
  c4:	1b 3f       	cpi	r17, 0xFB	; 251
  c6:	39 f7       	brne	.-50     	; 0x96 <main+0x38>
				{
					maincounter = 0; 
					uart_puts(maincounter);
  c8:	80 e0       	ldi	r24, 0x00	; 0
  ca:	90 e0       	ldi	r25, 0x00	; 0
  cc:	74 d0       	rcall	.+232    	; 0x1b6 <uart_puts>
  ce:	e2 cf       	rjmp	.-60     	; 0x94 <main+0x36>

000000d0 <__vector_9>:
			}
    }
}

ISR(TIMER0_OVF_vect)
{
  d0:	1f 92       	push	r1
  d2:	0f 92       	push	r0
  d4:	0f b6       	in	r0, 0x3f	; 63
  d6:	0f 92       	push	r0
  d8:	11 24       	eor	r1, r1
  da:	8f 93       	push	r24
	timercounter++;
  dc:	80 91 74 00 	lds	r24, 0x0074	; 0x800074 <__data_end>
  e0:	8f 5f       	subi	r24, 0xFF	; 255
  e2:	80 93 74 00 	sts	0x0074, r24	; 0x800074 <__data_end>
}
  e6:	8f 91       	pop	r24
  e8:	0f 90       	pop	r0
  ea:	0f be       	out	0x3f, r0	; 63
  ec:	0f 90       	pop	r0
  ee:	1f 90       	pop	r1
  f0:	18 95       	reti

000000f2 <__vector_1>:



ISR(INT0_vect)
{uart_puts(" x ");
  f2:	1f 92       	push	r1
  f4:	0f 92       	push	r0
  f6:	0f b6       	in	r0, 0x3f	; 63
  f8:	0f 92       	push	r0
  fa:	11 24       	eor	r1, r1
  fc:	2f 93       	push	r18
  fe:	3f 93       	push	r19
 100:	4f 93       	push	r20
 102:	5f 93       	push	r21
 104:	6f 93       	push	r22
 106:	7f 93       	push	r23
 108:	8f 93       	push	r24
 10a:	9f 93       	push	r25
 10c:	af 93       	push	r26
 10e:	bf 93       	push	r27
 110:	cf 93       	push	r28
 112:	ef 93       	push	r30
 114:	ff 93       	push	r31
 116:	82 e6       	ldi	r24, 0x62	; 98
 118:	90 e0       	ldi	r25, 0x00	; 0
 11a:	4d d0       	rcall	.+154    	; 0x1b6 <uart_puts>
    uint8_t status;   
    
        // Read wl_module status 
        wl_module_CSN_lo;                               // Pull down chip select
 11c:	c1 98       	cbi	0x18, 1	; 24
        status = spi_fast_shift(NOP);					// Read status register
 11e:	8f ef       	ldi	r24, 0xFF	; 255
 120:	75 d0       	rcall	.+234    	; 0x20c <spi_fast_shift>
 122:	c8 2f       	mov	r28, r24
 124:	8f e1       	ldi	r24, 0x1F	; 31
 126:	9e e4       	ldi	r25, 0x4E	; 78
 128:	01 97       	sbiw	r24, 0x01	; 1
 12a:	f1 f7       	brne	.-4      	; 0x128 <__vector_1+0x36>
 12c:	00 c0       	rjmp	.+0      	; 0x12e <__vector_1+0x3c>
 12e:	00 00       	nop
		_delay_ms(100);
        wl_module_CSN_hi;                               // Pull up chip select
 130:	c1 9a       	sbi	0x18, 1	; 24
		
		
		if (status & (1<<TX_DS))							// IRQ: Package has been sent
 132:	c5 ff       	sbrs	r28, 5
 134:	08 c0       	rjmp	.+16     	; 0x146 <__vector_1+0x54>
		{
			wl_module_config_register(STATUS, (1<<TX_DS));	//Clear Interrupt Bit
 136:	60 e2       	ldi	r22, 0x20	; 32
 138:	87 e0       	ldi	r24, 0x07	; 7
 13a:	78 d0       	rcall	.+240    	; 0x22c <wl_module_config_register>
			PTX=0;
 13c:	10 92 75 00 	sts	0x0075, r1	; 0x800075 <PTX>
			uart_puts(" y ");
 140:	86 e6       	ldi	r24, 0x66	; 102
 142:	90 e0       	ldi	r25, 0x00	; 0
 144:	38 d0       	rcall	.+112    	; 0x1b6 <uart_puts>
		}
		
		if (status & (1<<MAX_RT))							// IRQ: Package has not been sent, send again
 146:	c4 ff       	sbrs	r28, 4
 148:	0e c0       	rjmp	.+28     	; 0x166 <__vector_1+0x74>
		{
			wl_module_config_register(STATUS, (1<<MAX_RT));	// Clear Interrupt Bit
 14a:	60 e1       	ldi	r22, 0x10	; 16
 14c:	87 e0       	ldi	r24, 0x07	; 7
 14e:	6e d0       	rcall	.+220    	; 0x22c <wl_module_config_register>
			wl_module_CE_hi;								// Start transmission
 150:	c0 9a       	sbi	0x18, 0	; 24
 152:	8f e1       	ldi	r24, 0x1F	; 31
 154:	9e e4       	ldi	r25, 0x4E	; 78
 156:	01 97       	sbiw	r24, 0x01	; 1
 158:	f1 f7       	brne	.-4      	; 0x156 <__vector_1+0x64>
 15a:	00 c0       	rjmp	.+0      	; 0x15c <__vector_1+0x6a>
 15c:	00 00       	nop
			_delay_ms(100);								
			wl_module_CE_lo;
 15e:	c0 98       	cbi	0x18, 0	; 24
			uart_puts(" z ");
 160:	8a e6       	ldi	r24, 0x6A	; 106
 162:	90 e0       	ldi	r25, 0x00	; 0
 164:	28 d0       	rcall	.+80     	; 0x1b6 <uart_puts>
		}
		
		if (status & (1<<TX_FULL))							//TX_FIFO Full <-- this is not an IRQ
 166:	c0 ff       	sbrs	r28, 0
 168:	07 c0       	rjmp	.+14     	; 0x178 <__vector_1+0x86>
		{
			wl_module_CSN_lo;                               // Pull down chip select
 16a:	c1 98       	cbi	0x18, 1	; 24
			spi_fast_shift(FLUSH_TX);						// Flush TX-FIFO
 16c:	81 ee       	ldi	r24, 0xE1	; 225
 16e:	4e d0       	rcall	.+156    	; 0x20c <spi_fast_shift>
			wl_module_CSN_hi;                               // Pull up chip select
 170:	c1 9a       	sbi	0x18, 1	; 24
			uart_puts(" b ");
 172:	8e e6       	ldi	r24, 0x6E	; 110
 174:	90 e0       	ldi	r25, 0x00	; 0
 176:	1f d0       	rcall	.+62     	; 0x1b6 <uart_puts>
		}
		
 178:	ff 91       	pop	r31
 17a:	ef 91       	pop	r30
 17c:	cf 91       	pop	r28
 17e:	bf 91       	pop	r27
 180:	af 91       	pop	r26
 182:	9f 91       	pop	r25
 184:	8f 91       	pop	r24
 186:	7f 91       	pop	r23
 188:	6f 91       	pop	r22
 18a:	5f 91       	pop	r21
 18c:	4f 91       	pop	r20
 18e:	3f 91       	pop	r19
 190:	2f 91       	pop	r18
 192:	0f 90       	pop	r0
 194:	0f be       	out	0x3f, r0	; 63
 196:	0f 90       	pop	r0
 198:	1f 90       	pop	r1
 19a:	18 95       	reti

0000019c <uart_init>:
}


void uart_init(void)
{
	UBRRH = UBRR_VAL >> 8;	//Baudrate festlegen
 19c:	10 bc       	out	0x20, r1	; 32
	UBRRL = UBRR_VAL & 0xFF;
 19e:	83 e3       	ldi	r24, 0x33	; 51
 1a0:	89 b9       	out	0x09, r24	; 9
	
	UCSRB |= (1 << TXEN) | (1<<RXEN);	//Senden einschatel TX
 1a2:	8a b1       	in	r24, 0x0a	; 10
 1a4:	88 61       	ori	r24, 0x18	; 24
 1a6:	8a b9       	out	0x0a, r24	; 10
	UCSRC =  (1<<URSEL) | (1<<UCSZ1) | (1<<UCSZ0); //Asynchron 8N1
 1a8:	86 e8       	ldi	r24, 0x86	; 134
 1aa:	80 bd       	out	0x20, r24	; 32
 1ac:	08 95       	ret

000001ae <uart_putc>:

//Senden

int uart_putc(unsigned char c)
{
	while (!(UCSRA & (1<<UDRE))) //Warten bis senden möglich
 1ae:	5d 9b       	sbis	0x0b, 5	; 11
 1b0:	fe cf       	rjmp	.-4      	; 0x1ae <uart_putc>
	{}
	UDR = c;	//Zeichen senden
 1b2:	8c b9       	out	0x0c, r24	; 12
	
}
 1b4:	08 95       	ret

000001b6 <uart_puts>:

void uart_puts(char *s)
{
 1b6:	cf 93       	push	r28
 1b8:	df 93       	push	r29
 1ba:	ec 01       	movw	r28, r24
	while (*s)
 1bc:	88 81       	ld	r24, Y
 1be:	88 23       	and	r24, r24
 1c0:	29 f0       	breq	.+10     	; 0x1cc <uart_puts+0x16>
 1c2:	21 96       	adiw	r28, 0x01	; 1
	{// so lange *s != '\0' also ungleich dem "String-Endezeichen(Terminator)"
		uart_putc(*s);
 1c4:	f4 df       	rcall	.-24     	; 0x1ae <uart_putc>
	
}

void uart_puts(char *s)
{
	while (*s)
 1c6:	89 91       	ld	r24, Y+
 1c8:	81 11       	cpse	r24, r1
 1ca:	fc cf       	rjmp	.-8      	; 0x1c4 <uart_puts+0xe>
	{// so lange *s != '\0' also ungleich dem "String-Endezeichen(Terminator)"
		uart_putc(*s);
		s++;
	}
}
 1cc:	df 91       	pop	r29
 1ce:	cf 91       	pop	r28
 1d0:	08 95       	ret

000001d2 <spi_init>:

void spi_transfer_sync (uint8_t * dataout, uint8_t * datain, uint8_t len)
// Shift full array through target device
{
       uint8_t i;      
       for (i = 0; i < len; i++) {
 1d2:	87 b3       	in	r24, 0x17	; 23
 1d4:	83 7c       	andi	r24, 0xC3	; 195
 1d6:	87 bb       	out	0x17, r24	; 23
 1d8:	87 b3       	in	r24, 0x17	; 23
 1da:	8c 62       	ori	r24, 0x2C	; 44
 1dc:	87 bb       	out	0x17, r24	; 23
 1de:	81 e5       	ldi	r24, 0x51	; 81
 1e0:	8d b9       	out	0x0d, r24	; 13
 1e2:	81 e0       	ldi	r24, 0x01	; 1
 1e4:	8e b9       	out	0x0e, r24	; 14
 1e6:	08 95       	ret

000001e8 <spi_transmit_sync>:

void spi_transmit_sync (uint8_t * dataout, uint8_t len)
// Shift full array to target device without receiving any byte
{
       uint8_t i;      
       for (i = 0; i < len; i++) {
 1e8:	66 23       	and	r22, r22
 1ea:	79 f0       	breq	.+30     	; 0x20a <spi_transmit_sync+0x22>
 1ec:	fc 01       	movw	r30, r24
 1ee:	61 50       	subi	r22, 0x01	; 1
 1f0:	26 2f       	mov	r18, r22
 1f2:	30 e0       	ldi	r19, 0x00	; 0
 1f4:	2f 5f       	subi	r18, 0xFF	; 255
 1f6:	3f 4f       	sbci	r19, 0xFF	; 255
 1f8:	28 0f       	add	r18, r24
 1fa:	39 1f       	adc	r19, r25
             SPDR = dataout[i];
 1fc:	91 91       	ld	r25, Z+
 1fe:	9f b9       	out	0x0f, r25	; 15
             while((SPSR & (1<<SPIF))==0);
 200:	77 9b       	sbis	0x0e, 7	; 14
 202:	fe cf       	rjmp	.-4      	; 0x200 <spi_transmit_sync+0x18>

void spi_transmit_sync (uint8_t * dataout, uint8_t len)
// Shift full array to target device without receiving any byte
{
       uint8_t i;      
       for (i = 0; i < len; i++) {
 204:	e2 17       	cp	r30, r18
 206:	f3 07       	cpc	r31, r19
 208:	c9 f7       	brne	.-14     	; 0x1fc <spi_transmit_sync+0x14>
 20a:	08 95       	ret

0000020c <spi_fast_shift>:
}

uint8_t spi_fast_shift (uint8_t data)
// Clocks only one byte to target device and returns the received one
{
    SPDR = data;
 20c:	8f b9       	out	0x0f, r24	; 15
    while((SPSR & (1<<SPIF))==0);
 20e:	77 9b       	sbis	0x0e, 7	; 14
 210:	fe cf       	rjmp	.-4      	; 0x20e <spi_fast_shift+0x2>
    return SPDR;
 212:	8f b1       	in	r24, 0x0f	; 15
}
 214:	08 95       	ret

00000216 <wl_module_init>:
  
    // Start receiver 
    PTX = 0;        // Start in receiving mode
    RX_POWERUP;     // Power up in receiving mode
    wl_module_CE_hi;     // Listening for pakets
}
 216:	87 b3       	in	r24, 0x17	; 23
 218:	83 60       	ori	r24, 0x03	; 3
 21a:	87 bb       	out	0x17, r24	; 23
 21c:	c0 98       	cbi	0x18, 0	; 24
 21e:	c1 9a       	sbi	0x18, 1	; 24
 220:	8a e0       	ldi	r24, 0x0A	; 10
 222:	85 bf       	out	0x35, r24	; 53
 224:	80 e4       	ldi	r24, 0x40	; 64
 226:	8b bf       	out	0x3b, r24	; 59
 228:	d4 df       	rcall	.-88     	; 0x1d2 <spi_init>
 22a:	08 95       	ret

0000022c <wl_module_config_register>:
 22c:	cf 93       	push	r28
 22e:	c6 2f       	mov	r28, r22
 230:	c1 98       	cbi	0x18, 1	; 24
 232:	8f 71       	andi	r24, 0x1F	; 31
 234:	80 62       	ori	r24, 0x20	; 32
 236:	ea df       	rcall	.-44     	; 0x20c <spi_fast_shift>
 238:	8c 2f       	mov	r24, r28
 23a:	e8 df       	rcall	.-48     	; 0x20c <spi_fast_shift>
 23c:	c1 9a       	sbi	0x18, 1	; 24
 23e:	cf 91       	pop	r28
 240:	08 95       	ret

00000242 <wl_module_write_register>:
 242:	1f 93       	push	r17
 244:	cf 93       	push	r28
 246:	df 93       	push	r29
 248:	eb 01       	movw	r28, r22
 24a:	14 2f       	mov	r17, r20
 24c:	c1 98       	cbi	0x18, 1	; 24
 24e:	8f 71       	andi	r24, 0x1F	; 31
 250:	80 62       	ori	r24, 0x20	; 32
 252:	dc df       	rcall	.-72     	; 0x20c <spi_fast_shift>
 254:	61 2f       	mov	r22, r17
 256:	ce 01       	movw	r24, r28
 258:	c7 df       	rcall	.-114    	; 0x1e8 <spi_transmit_sync>
 25a:	c1 9a       	sbi	0x18, 1	; 24
 25c:	df 91       	pop	r29
 25e:	cf 91       	pop	r28
 260:	1f 91       	pop	r17
 262:	08 95       	ret

00000264 <wl_module_set_RADDR>:
 264:	45 e0       	ldi	r20, 0x05	; 5
 266:	bc 01       	movw	r22, r24
 268:	8a e0       	ldi	r24, 0x0A	; 10
 26a:	eb df       	rcall	.-42     	; 0x242 <wl_module_write_register>
 26c:	08 95       	ret

0000026e <wl_module_set_TADDR>:
 26e:	45 e0       	ldi	r20, 0x05	; 5
 270:	bc 01       	movw	r22, r24
 272:	80 e1       	ldi	r24, 0x10	; 16
 274:	e6 df       	rcall	.-52     	; 0x242 <wl_module_write_register>
 276:	08 95       	ret

00000278 <wl_module_tx_config>:
 278:	1f 93       	push	r17
 27a:	cf 93       	push	r28
 27c:	df 93       	push	r29
 27e:	00 d0       	rcall	.+0      	; 0x280 <wl_module_tx_config+0x8>
 280:	00 d0       	rcall	.+0      	; 0x282 <wl_module_tx_config+0xa>
 282:	1f 92       	push	r1
 284:	cd b7       	in	r28, 0x3d	; 61
 286:	de b7       	in	r29, 0x3e	; 62
 288:	18 2f       	mov	r17, r24
 28a:	62 e0       	ldi	r22, 0x02	; 2
 28c:	85 e0       	ldi	r24, 0x05	; 5
 28e:	ce df       	rcall	.-100    	; 0x22c <wl_module_config_register>
 290:	67 e0       	ldi	r22, 0x07	; 7
 292:	86 e0       	ldi	r24, 0x06	; 6
 294:	cb df       	rcall	.-106    	; 0x22c <wl_module_config_register>
 296:	6c e4       	ldi	r22, 0x4C	; 76
 298:	80 e0       	ldi	r24, 0x00	; 0
 29a:	c8 df       	rcall	.-112    	; 0x22c <wl_module_config_register>
 29c:	60 e1       	ldi	r22, 0x10	; 16
 29e:	81 e1       	ldi	r24, 0x11	; 17
 2a0:	c5 df       	rcall	.-118    	; 0x22c <wl_module_config_register>
 2a2:	6f e2       	ldi	r22, 0x2F	; 47
 2a4:	84 e0       	ldi	r24, 0x04	; 4
 2a6:	c2 df       	rcall	.-124    	; 0x22c <wl_module_config_register>
 2a8:	12 30       	cpi	r17, 0x02	; 2
 2aa:	39 f1       	breq	.+78     	; 0x2fa <wl_module_tx_config+0x82>
 2ac:	28 f4       	brcc	.+10     	; 0x2b8 <wl_module_tx_config+0x40>
 2ae:	11 23       	and	r17, r17
 2b0:	51 f0       	breq	.+20     	; 0x2c6 <wl_module_tx_config+0x4e>
 2b2:	11 30       	cpi	r17, 0x01	; 1
 2b4:	a9 f0       	breq	.+42     	; 0x2e0 <wl_module_tx_config+0x68>
 2b6:	58 c0       	rjmp	.+176    	; 0x368 <wl_module_tx_config+0xf0>
 2b8:	14 30       	cpi	r17, 0x04	; 4
 2ba:	d9 f1       	breq	.+118    	; 0x332 <wl_module_tx_config+0xba>
 2bc:	60 f1       	brcs	.+88     	; 0x316 <wl_module_tx_config+0x9e>
 2be:	15 30       	cpi	r17, 0x05	; 5
 2c0:	09 f4       	brne	.+2      	; 0x2c4 <wl_module_tx_config+0x4c>
 2c2:	45 c0       	rjmp	.+138    	; 0x34e <wl_module_tx_config+0xd6>
 2c4:	51 c0       	rjmp	.+162    	; 0x368 <wl_module_tx_config+0xf0>
 2c6:	87 ee       	ldi	r24, 0xE7	; 231
 2c8:	8d 83       	std	Y+5, r24	; 0x05
 2ca:	8c 83       	std	Y+4, r24	; 0x04
 2cc:	8b 83       	std	Y+3, r24	; 0x03
 2ce:	8a 83       	std	Y+2, r24	; 0x02
 2d0:	89 83       	std	Y+1, r24	; 0x01
 2d2:	ce 01       	movw	r24, r28
 2d4:	01 96       	adiw	r24, 0x01	; 1
 2d6:	cb df       	rcall	.-106    	; 0x26e <wl_module_set_TADDR>
 2d8:	ce 01       	movw	r24, r28
 2da:	01 96       	adiw	r24, 0x01	; 1
 2dc:	c3 df       	rcall	.-122    	; 0x264 <wl_module_set_RADDR>
 2de:	44 c0       	rjmp	.+136    	; 0x368 <wl_module_tx_config+0xf0>
 2e0:	82 ec       	ldi	r24, 0xC2	; 194
 2e2:	8d 83       	std	Y+5, r24	; 0x05
 2e4:	8c 83       	std	Y+4, r24	; 0x04
 2e6:	8b 83       	std	Y+3, r24	; 0x03
 2e8:	8a 83       	std	Y+2, r24	; 0x02
 2ea:	89 83       	std	Y+1, r24	; 0x01
 2ec:	ce 01       	movw	r24, r28
 2ee:	01 96       	adiw	r24, 0x01	; 1
 2f0:	be df       	rcall	.-132    	; 0x26e <wl_module_set_TADDR>
 2f2:	ce 01       	movw	r24, r28
 2f4:	01 96       	adiw	r24, 0x01	; 1
 2f6:	b6 df       	rcall	.-148    	; 0x264 <wl_module_set_RADDR>
 2f8:	37 c0       	rjmp	.+110    	; 0x368 <wl_module_tx_config+0xf0>
 2fa:	82 ec       	ldi	r24, 0xC2	; 194
 2fc:	8d 83       	std	Y+5, r24	; 0x05
 2fe:	8c 83       	std	Y+4, r24	; 0x04
 300:	8b 83       	std	Y+3, r24	; 0x03
 302:	8a 83       	std	Y+2, r24	; 0x02
 304:	83 ec       	ldi	r24, 0xC3	; 195
 306:	89 83       	std	Y+1, r24	; 0x01
 308:	ce 01       	movw	r24, r28
 30a:	01 96       	adiw	r24, 0x01	; 1
 30c:	b0 df       	rcall	.-160    	; 0x26e <wl_module_set_TADDR>
 30e:	ce 01       	movw	r24, r28
 310:	01 96       	adiw	r24, 0x01	; 1
 312:	a8 df       	rcall	.-176    	; 0x264 <wl_module_set_RADDR>
 314:	29 c0       	rjmp	.+82     	; 0x368 <wl_module_tx_config+0xf0>
 316:	82 ec       	ldi	r24, 0xC2	; 194
 318:	8d 83       	std	Y+5, r24	; 0x05
 31a:	8c 83       	std	Y+4, r24	; 0x04
 31c:	8b 83       	std	Y+3, r24	; 0x03
 31e:	8a 83       	std	Y+2, r24	; 0x02
 320:	84 ec       	ldi	r24, 0xC4	; 196
 322:	89 83       	std	Y+1, r24	; 0x01
 324:	ce 01       	movw	r24, r28
 326:	01 96       	adiw	r24, 0x01	; 1
 328:	a2 df       	rcall	.-188    	; 0x26e <wl_module_set_TADDR>
 32a:	ce 01       	movw	r24, r28
 32c:	01 96       	adiw	r24, 0x01	; 1
 32e:	9a df       	rcall	.-204    	; 0x264 <wl_module_set_RADDR>
 330:	1b c0       	rjmp	.+54     	; 0x368 <wl_module_tx_config+0xf0>
 332:	82 ec       	ldi	r24, 0xC2	; 194
 334:	8d 83       	std	Y+5, r24	; 0x05
 336:	8c 83       	std	Y+4, r24	; 0x04
 338:	8b 83       	std	Y+3, r24	; 0x03
 33a:	8a 83       	std	Y+2, r24	; 0x02
 33c:	85 ec       	ldi	r24, 0xC5	; 197
 33e:	89 83       	std	Y+1, r24	; 0x01
 340:	ce 01       	movw	r24, r28
 342:	01 96       	adiw	r24, 0x01	; 1
 344:	94 df       	rcall	.-216    	; 0x26e <wl_module_set_TADDR>
 346:	ce 01       	movw	r24, r28
 348:	01 96       	adiw	r24, 0x01	; 1
 34a:	8c df       	rcall	.-232    	; 0x264 <wl_module_set_RADDR>
 34c:	0d c0       	rjmp	.+26     	; 0x368 <wl_module_tx_config+0xf0>
 34e:	82 ec       	ldi	r24, 0xC2	; 194
 350:	8d 83       	std	Y+5, r24	; 0x05
 352:	8c 83       	std	Y+4, r24	; 0x04
 354:	8b 83       	std	Y+3, r24	; 0x03
 356:	8a 83       	std	Y+2, r24	; 0x02
 358:	86 ec       	ldi	r24, 0xC6	; 198
 35a:	89 83       	std	Y+1, r24	; 0x01
 35c:	ce 01       	movw	r24, r28
 35e:	01 96       	adiw	r24, 0x01	; 1
 360:	86 df       	rcall	.-244    	; 0x26e <wl_module_set_TADDR>
 362:	ce 01       	movw	r24, r28
 364:	01 96       	adiw	r24, 0x01	; 1
 366:	7e df       	rcall	.-260    	; 0x264 <wl_module_set_RADDR>
 368:	10 92 75 00 	sts	0x0075, r1	; 0x800075 <PTX>
 36c:	6e e4       	ldi	r22, 0x4E	; 78
 36e:	80 e0       	ldi	r24, 0x00	; 0
 370:	5d df       	rcall	.-326    	; 0x22c <wl_module_config_register>
 372:	0f 90       	pop	r0
 374:	0f 90       	pop	r0
 376:	0f 90       	pop	r0
 378:	0f 90       	pop	r0
 37a:	0f 90       	pop	r0
 37c:	df 91       	pop	r29
 37e:	cf 91       	pop	r28
 380:	1f 91       	pop	r17
 382:	08 95       	ret

00000384 <wl_module_send>:


void wl_module_send(uint8_t * value, uint8_t len) 
// Sends a data package to the default address. Be sure to send the correct
// amount of bytes as configured as payload on the receiver.
{
 384:	1f 93       	push	r17
 386:	cf 93       	push	r28
 388:	df 93       	push	r29
 38a:	ec 01       	movw	r28, r24
 38c:	16 2f       	mov	r17, r22
    while (PTX) {}                  // Wait until last paket is send
 38e:	80 91 75 00 	lds	r24, 0x0075	; 0x800075 <PTX>
 392:	81 11       	cpse	r24, r1
 394:	fc cf       	rjmp	.-8      	; 0x38e <wl_module_send+0xa>

    wl_module_CE_lo;
 396:	c0 98       	cbi	0x18, 0	; 24
uart_puts("e");
 398:	82 e7       	ldi	r24, 0x72	; 114
 39a:	90 e0       	ldi	r25, 0x00	; 0
 39c:	0c df       	rcall	.-488    	; 0x1b6 <uart_puts>
    PTX = 1;                        // Set to transmitter mode
 39e:	81 e0       	ldi	r24, 0x01	; 1
 3a0:	80 93 75 00 	sts	0x0075, r24	; 0x800075 <PTX>
    TX_POWERUP;                     // Power up
 3a4:	6e e4       	ldi	r22, 0x4E	; 78
 3a6:	80 e0       	ldi	r24, 0x00	; 0
 3a8:	41 df       	rcall	.-382    	; 0x22c <wl_module_config_register>
    
    wl_module_CSN_lo;                    // Pull down chip select
 3aa:	c1 98       	cbi	0x18, 1	; 24
    spi_fast_shift( FLUSH_TX );     // Write cmd to flush tx fifo
 3ac:	81 ee       	ldi	r24, 0xE1	; 225
 3ae:	2e df       	rcall	.-420    	; 0x20c <spi_fast_shift>
    wl_module_CSN_hi;                    // Pull up chip select
 3b0:	c1 9a       	sbi	0x18, 1	; 24
    
    wl_module_CSN_lo;                    // Pull down chip select
 3b2:	c1 98       	cbi	0x18, 1	; 24
    spi_fast_shift( W_TX_PAYLOAD ); // Write cmd to write payload
 3b4:	80 ea       	ldi	r24, 0xA0	; 160
 3b6:	2a df       	rcall	.-428    	; 0x20c <spi_fast_shift>
    spi_transmit_sync(value,len);   // Write payload
 3b8:	61 2f       	mov	r22, r17
 3ba:	ce 01       	movw	r24, r28
 3bc:	15 df       	rcall	.-470    	; 0x1e8 <spi_transmit_sync>
    wl_module_CSN_hi;                    // Pull up chip select
 3be:	c1 9a       	sbi	0x18, 1	; 24
    
    wl_module_CE_hi;                     // Start transmission
 3c0:	c0 9a       	sbi	0x18, 0	; 24
 3c2:	2f e9       	ldi	r18, 0x9F	; 159
 3c4:	86 e8       	ldi	r24, 0x86	; 134
 3c6:	91 e0       	ldi	r25, 0x01	; 1
 3c8:	21 50       	subi	r18, 0x01	; 1
 3ca:	80 40       	sbci	r24, 0x00	; 0
 3cc:	90 40       	sbci	r25, 0x00	; 0
 3ce:	e1 f7       	brne	.-8      	; 0x3c8 <wl_module_send+0x44>
 3d0:	00 c0       	rjmp	.+0      	; 0x3d2 <wl_module_send+0x4e>
 3d2:	00 00       	nop
  _delay_ms(500);            // Grünes Modul funktioniert nicht mit 10µs delay
  wl_module_CE_lo;
 3d4:	c0 98       	cbi	0x18, 0	; 24
 3d6:	df 91       	pop	r29
 3d8:	cf 91       	pop	r28
 3da:	1f 91       	pop	r17
 3dc:	08 95       	ret

000003de <_exit>:
 3de:	f8 94       	cli

000003e0 <__stop_program>:
 3e0:	ff cf       	rjmp	.-2      	; 0x3e0 <__stop_program>
