
Test_1_Empfaenger.elf:     file format elf32-avr

Sections:
Idx Name          Size      VMA       LMA       File off  Algn
  0 .text         000002a4  00000000  00000000  00000094  2**1
                  CONTENTS, ALLOC, LOAD, READONLY, CODE
  1 .data         0000000a  00800060  000002a4  00000338  2**0
                  CONTENTS, ALLOC, LOAD, DATA
  2 .bss          00000015  0080006a  0080006a  00000342  2**0
                  ALLOC
  3 .comment      00000030  00000000  00000000  00000342  2**0
                  CONTENTS, READONLY
  4 .note.gnu.avr.deviceinfo 0000003c  00000000  00000000  00000374  2**2
                  CONTENTS, READONLY
  5 .debug_aranges 000001a8  00000000  00000000  000003b0  2**0
                  CONTENTS, READONLY, DEBUGGING
  6 .debug_info   00001c05  00000000  00000000  00000558  2**0
                  CONTENTS, READONLY, DEBUGGING
  7 .debug_abbrev 00000bb4  00000000  00000000  0000215d  2**0
                  CONTENTS, READONLY, DEBUGGING
  8 .debug_line   00000cf1  00000000  00000000  00002d11  2**0
                  CONTENTS, READONLY, DEBUGGING
  9 .debug_frame  00000430  00000000  00000000  00003a04  2**2
                  CONTENTS, READONLY, DEBUGGING
 10 .debug_str    00000759  00000000  00000000  00003e34  2**0
                  CONTENTS, READONLY, DEBUGGING
 11 .debug_loc    00000f2c  00000000  00000000  0000458d  2**0
                  CONTENTS, READONLY, DEBUGGING
 12 .debug_ranges 00000168  00000000  00000000  000054b9  2**0
                  CONTENTS, READONLY, DEBUGGING

Disassembly of section .text:

00000000 <__vectors>:
   0:	0c 94 2a 00 	jmp	0x54	; 0x54 <__ctors_end>
   4:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
   8:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
   c:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  10:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  14:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  18:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  1c:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  20:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  24:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  28:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  2c:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  30:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  34:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  38:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  3c:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  40:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  44:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  48:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  4c:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>
  50:	0c 94 47 00 	jmp	0x8e	; 0x8e <__bad_interrupt>

00000054 <__ctors_end>:
  54:	11 24       	eor	r1, r1
  56:	1f be       	out	0x3f, r1	; 63
  58:	cf e5       	ldi	r28, 0x5F	; 95
  5a:	d4 e0       	ldi	r29, 0x04	; 4
  5c:	de bf       	out	0x3e, r29	; 62
  5e:	cd bf       	out	0x3d, r28	; 61

00000060 <__do_copy_data>:
  60:	10 e0       	ldi	r17, 0x00	; 0
  62:	a0 e6       	ldi	r26, 0x60	; 96
  64:	b0 e0       	ldi	r27, 0x00	; 0
  66:	e4 ea       	ldi	r30, 0xA4	; 164
  68:	f2 e0       	ldi	r31, 0x02	; 2
  6a:	02 c0       	rjmp	.+4      	; 0x70 <__do_copy_data+0x10>
  6c:	05 90       	lpm	r0, Z+
  6e:	0d 92       	st	X+, r0
  70:	aa 36       	cpi	r26, 0x6A	; 106
  72:	b1 07       	cpc	r27, r17
  74:	d9 f7       	brne	.-10     	; 0x6c <__do_copy_data+0xc>

00000076 <__do_clear_bss>:
  76:	20 e0       	ldi	r18, 0x00	; 0
  78:	aa e6       	ldi	r26, 0x6A	; 106
  7a:	b0 e0       	ldi	r27, 0x00	; 0
  7c:	01 c0       	rjmp	.+2      	; 0x80 <.do_clear_bss_start>

0000007e <.do_clear_bss_loop>:
  7e:	1d 92       	st	X+, r1

00000080 <.do_clear_bss_start>:
  80:	af 37       	cpi	r26, 0x7F	; 127
  82:	b2 07       	cpc	r27, r18
  84:	e1 f7       	brne	.-8      	; 0x7e <.do_clear_bss_loop>
  86:	0e 94 49 00 	call	0x92	; 0x92 <main>
  8a:	0c 94 50 01 	jmp	0x2a0	; 0x2a0 <_exit>

0000008e <__bad_interrupt>:
  8e:	0c 94 00 00 	jmp	0	; 0x0 <__vectors>

00000092 <main>:
//Variablen
volatile uint8_t PTX;			//Global Variable
char itoabuffer[20];

int main(void)
{
  92:	cf 93       	push	r28
  94:	df 93       	push	r29
  96:	cd b7       	in	r28, 0x3d	; 61
  98:	de b7       	in	r29, 0x3e	; 62
  9a:	60 97       	sbiw	r28, 0x10	; 16
  9c:	0f b6       	in	r0, 0x3f	; 63
  9e:	f8 94       	cli
  a0:	de bf       	out	0x3e, r29	; 62
  a2:	0f be       	out	0x3f, r0	; 63
  a4:	cd bf       	out	0x3d, r28	; 61
	uint8_t nRF_status;						//STATUS information of nRF24L01+
	uint8_t zaehler = 0;
	
	//lcd_init();
	//lcd_clear();
	uart_init();
  a6:	0e 94 7b 00 	call	0xf6	; 0xf6 <uart_init>
	wl_module_init();		//Init nRF Module
  aa:	0e 94 bd 00 	call	0x17a	; 0x17a <wl_module_init>
	#else
		//round up by default
		__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
	#endif

	__builtin_avr_delay_cycles(__ticks_dc);
  ae:	2f e7       	ldi	r18, 0x7F	; 127
  b0:	88 e3       	ldi	r24, 0x38	; 56
  b2:	91 e0       	ldi	r25, 0x01	; 1
  b4:	21 50       	subi	r18, 0x01	; 1
  b6:	80 40       	sbci	r24, 0x00	; 0
  b8:	90 40       	sbci	r25, 0x00	; 0
  ba:	e1 f7       	brne	.-8      	; 0xb4 <main+0x22>
  bc:	00 c0       	rjmp	.+0      	; 0xbe <main+0x2c>
  be:	00 00       	nop
	_delay_ms(50);			//wait for Module
	sei();					//activate Interrupts
  c0:	78 94       	sei
	wl_module_config();		//config nRF as RX Module, simple Version
  c2:	0e 94 eb 00 	call	0x1d6	; 0x1d6 <wl_module_config>



    while(1)
    {
		while (!wl_module_data_ready());			//waits for RX_DR Flag in STATUS
  c6:	0e 94 c9 00 	call	0x192	; 0x192 <wl_module_data_ready>
  ca:	88 23       	and	r24, r24
  cc:	e1 f3       	breq	.-8      	; 0xc6 <main+0x34>
		uart_puts("t");
  ce:	80 e6       	ldi	r24, 0x60	; 96
  d0:	90 e0       	ldi	r25, 0x00	; 0
  d2:	0e 94 88 00 	call	0x110	; 0x110 <uart_puts>
		nRF_status = wl_module_get_data(payload);	//reads the incomming Data to Array payload
  d6:	ce 01       	movw	r24, r28
  d8:	01 96       	adiw	r24, 0x01	; 1
  da:	0e 94 ff 00 	call	0x1fe	; 0x1fe <wl_module_get_data>
    } else if (__radix < 2 || __radix > 36) {
	*__s = 0;
	return __s;
    } else {
	extern char *__itoa_ncheck (int, char *, unsigned char);
	return __itoa_ncheck (__val, __s, __radix);
  de:	89 81       	ldd	r24, Y+1	; 0x01
  e0:	4a e0       	ldi	r20, 0x0A	; 10
  e2:	6b e6       	ldi	r22, 0x6B	; 107
  e4:	70 e0       	ldi	r23, 0x00	; 0
  e6:	90 e0       	ldi	r25, 0x00	; 0
  e8:	0e 94 1b 01 	call	0x236	; 0x236 <__itoa_ncheck>
		zaehler = payload[0];
		//lcd_clear();
	//	lcd_home();
		itoa(zaehler, itoabuffer, 10);				//conversion into String
		//lcd_string(itoabuffer);
		uart_puts(itoabuffer);
  ec:	8b e6       	ldi	r24, 0x6B	; 107
  ee:	90 e0       	ldi	r25, 0x00	; 0
  f0:	0e 94 88 00 	call	0x110	; 0x110 <uart_puts>
		//_delay_ms(1000);
		
    }
  f4:	e8 cf       	rjmp	.-48     	; 0xc6 <main+0x34>

000000f6 <uart_init>:
}


void uart_init(void)
{
	UBRRH = UBRR_VAL >> 8;	//Baudrate festlegen
  f6:	10 bc       	out	0x20, r1	; 32
	UBRRL = UBRR_VAL & 0xFF;
  f8:	83 e3       	ldi	r24, 0x33	; 51
  fa:	89 b9       	out	0x09, r24	; 9
	
	UCSRB |= (1 << TXEN) | (1<<RXEN);	//Senden einschatel TX
  fc:	8a b1       	in	r24, 0x0a	; 10
  fe:	88 61       	ori	r24, 0x18	; 24
 100:	8a b9       	out	0x0a, r24	; 10
	UCSRC =  (1<<URSEL) | (1<<UCSZ1) | (1<<UCSZ0); //Asynchron 8N1
 102:	86 e8       	ldi	r24, 0x86	; 134
 104:	80 bd       	out	0x20, r24	; 32
 106:	08 95       	ret

00000108 <uart_putc>:

//Senden

int uart_putc(unsigned char c)
{
	while (!(UCSRA & (1<<UDRE))) //Warten bis senden möglich
 108:	5d 9b       	sbis	0x0b, 5	; 11
 10a:	fe cf       	rjmp	.-4      	; 0x108 <uart_putc>
	{}
	UDR = c;	//Zeichen senden
 10c:	8c b9       	out	0x0c, r24	; 12
	
}
 10e:	08 95       	ret

00000110 <uart_puts>:

void uart_puts(char *s)
{
 110:	cf 93       	push	r28
 112:	df 93       	push	r29
 114:	ec 01       	movw	r28, r24
	while (*s)
 116:	88 81       	ld	r24, Y
 118:	88 23       	and	r24, r24
 11a:	31 f0       	breq	.+12     	; 0x128 <uart_puts+0x18>
 11c:	21 96       	adiw	r28, 0x01	; 1
	{// so lange *s != '\0' also ungleich dem "String-Endezeichen(Terminator)"
		uart_putc(*s);
 11e:	0e 94 84 00 	call	0x108	; 0x108 <uart_putc>
	
}

void uart_puts(char *s)
{
	while (*s)
 122:	89 91       	ld	r24, Y+
 124:	81 11       	cpse	r24, r1
 126:	fb cf       	rjmp	.-10     	; 0x11e <uart_puts+0xe>
	{// so lange *s != '\0' also ungleich dem "String-Endezeichen(Terminator)"
		uart_putc(*s);
		s++;
	}
}
 128:	df 91       	pop	r29
 12a:	cf 91       	pop	r28
 12c:	08 95       	ret

0000012e <spi_init>:

void spi_transmit_sync (uint8_t * dataout, uint8_t len)
// Shift full array to target device without receiving any byte
{
       uint8_t i;      
       for (i = 0; i < len; i++) {
 12e:	87 b3       	in	r24, 0x17	; 23
 130:	8f 70       	andi	r24, 0x0F	; 15
 132:	87 bb       	out	0x17, r24	; 23
 134:	87 b3       	in	r24, 0x17	; 23
 136:	80 6b       	ori	r24, 0xB0	; 176
 138:	87 bb       	out	0x17, r24	; 23
 13a:	81 e5       	ldi	r24, 0x51	; 81
 13c:	8d b9       	out	0x0d, r24	; 13
 13e:	81 e0       	ldi	r24, 0x01	; 1
 140:	8e b9       	out	0x0e, r24	; 14
 142:	08 95       	ret

00000144 <spi_transfer_sync>:
 144:	44 23       	and	r20, r20
 146:	99 f0       	breq	.+38     	; 0x16e <spi_transfer_sync+0x2a>
 148:	fc 01       	movw	r30, r24
 14a:	a6 2f       	mov	r26, r22
 14c:	b7 2f       	mov	r27, r23
 14e:	41 50       	subi	r20, 0x01	; 1
 150:	24 2f       	mov	r18, r20
 152:	30 e0       	ldi	r19, 0x00	; 0
 154:	2f 5f       	subi	r18, 0xFF	; 255
 156:	3f 4f       	sbci	r19, 0xFF	; 255
 158:	28 0f       	add	r18, r24
 15a:	39 1f       	adc	r19, r25
 15c:	91 91       	ld	r25, Z+
 15e:	9f b9       	out	0x0f, r25	; 15
 160:	77 9b       	sbis	0x0e, 7	; 14
 162:	fe cf       	rjmp	.-4      	; 0x160 <spi_transfer_sync+0x1c>
 164:	9f b1       	in	r25, 0x0f	; 15
 166:	9d 93       	st	X+, r25
 168:	e2 17       	cp	r30, r18
 16a:	f3 07       	cpc	r31, r19
 16c:	b9 f7       	brne	.-18     	; 0x15c <spi_transfer_sync+0x18>
 16e:	08 95       	ret

00000170 <spi_fast_shift>:
}

uint8_t spi_fast_shift (uint8_t data)
// Clocks only one byte to target device and returns the received one
{int test;
    SPDR = data;
 170:	8f b9       	out	0x0f, r24	; 15
    while((SPSR & (1<<SPIF))==0);
 172:	77 9b       	sbis	0x0e, 7	; 14
 174:	fe cf       	rjmp	.-4      	; 0x172 <spi_fast_shift+0x2>
//	itoa(data,test,10);
//	uart_puts(test);
    return SPDR;
 176:	8f b1       	in	r24, 0x0f	; 15
}
 178:	08 95       	ret

0000017a <wl_module_init>:
extern uint8_t wl_module_get_rx_pipe_reading_status()
{
	uint8_t pipe;
	pipe = wl_module_get_one_byte(NOP);
	return ((pipe & 0x0E) >> 1);
}
 17a:	87 b3       	in	r24, 0x17	; 23
 17c:	83 60       	ori	r24, 0x03	; 3
 17e:	87 bb       	out	0x17, r24	; 23
 180:	c0 98       	cbi	0x18, 0	; 24
 182:	c1 9a       	sbi	0x18, 1	; 24
 184:	8a e0       	ldi	r24, 0x0A	; 10
 186:	85 bf       	out	0x35, r24	; 53
 188:	80 e2       	ldi	r24, 0x20	; 32
 18a:	8b bf       	out	0x3b, r24	; 59
 18c:	0e 94 97 00 	call	0x12e	; 0x12e <spi_init>
 190:	08 95       	ret

00000192 <wl_module_data_ready>:
 192:	cf 93       	push	r28
 194:	80 91 6a 00 	lds	r24, 0x006A	; 0x80006a <__data_end>
 198:	81 11       	cpse	r24, r1
 19a:	0d c0       	rjmp	.+26     	; 0x1b6 <wl_module_data_ready+0x24>
 19c:	c1 98       	cbi	0x18, 1	; 24
 19e:	8f ef       	ldi	r24, 0xFF	; 255
 1a0:	0e 94 b8 00 	call	0x170	; 0x170 <spi_fast_shift>
 1a4:	c8 2f       	mov	r28, r24
 1a6:	c1 9a       	sbi	0x18, 1	; 24
 1a8:	82 e6       	ldi	r24, 0x62	; 98
 1aa:	90 e0       	ldi	r25, 0x00	; 0
 1ac:	0e 94 88 00 	call	0x110	; 0x110 <uart_puts>
 1b0:	8c 2f       	mov	r24, r28
 1b2:	80 74       	andi	r24, 0x40	; 64
 1b4:	01 c0       	rjmp	.+2      	; 0x1b8 <wl_module_data_ready+0x26>
 1b6:	80 e0       	ldi	r24, 0x00	; 0
 1b8:	cf 91       	pop	r28
 1ba:	08 95       	ret

000001bc <wl_module_config_register>:
	return status;
}

void wl_module_config_register(uint8_t reg, uint8_t value)
// Clocks only one byte into the given wl-module register
{
 1bc:	cf 93       	push	r28
 1be:	c6 2f       	mov	r28, r22
    wl_module_CSN_lo;
 1c0:	c1 98       	cbi	0x18, 1	; 24
    spi_fast_shift(W_REGISTER | (REGISTER_MASK & reg));
 1c2:	8f 71       	andi	r24, 0x1F	; 31
 1c4:	80 62       	ori	r24, 0x20	; 32
 1c6:	0e 94 b8 00 	call	0x170	; 0x170 <spi_fast_shift>
    spi_fast_shift(value);
 1ca:	8c 2f       	mov	r24, r28
 1cc:	0e 94 b8 00 	call	0x170	; 0x170 <spi_fast_shift>
    wl_module_CSN_hi;
 1d0:	c1 9a       	sbi	0x18, 1	; 24
}
 1d2:	cf 91       	pop	r28
 1d4:	08 95       	ret

000001d6 <wl_module_config>:
void wl_module_config() 
// Sets the important registers in the wl-module and powers the module
// in receiving mode
{
    // Set RF channel
    wl_module_config_register(RF_CH,wl_module_CH);
 1d6:	62 e0       	ldi	r22, 0x02	; 2
 1d8:	85 e0       	ldi	r24, 0x05	; 5
 1da:	0e 94 de 00 	call	0x1bc	; 0x1bc <wl_module_config_register>
	// Set data speed & Output Power configured in wl_module.h
	wl_module_config_register(RF_SETUP,wl_module_RF_SETUP);
 1de:	66 e2       	ldi	r22, 0x26	; 38
 1e0:	86 e0       	ldi	r24, 0x06	; 6
 1e2:	0e 94 de 00 	call	0x1bc	; 0x1bc <wl_module_config_register>
	// Set length of incoming payload 
    wl_module_config_register(RX_PW_P0, wl_module_PAYLOAD);
 1e6:	60 e1       	ldi	r22, 0x10	; 16
 1e8:	81 e1       	ldi	r24, 0x11	; 17
 1ea:	0e 94 de 00 	call	0x1bc	; 0x1bc <wl_module_config_register>
	
    // Start receiver 
    PTX = 0;        // Start in receiving mode
 1ee:	10 92 6a 00 	sts	0x006A, r1	; 0x80006a <__data_end>
    RX_POWERUP;     // Power up in receiving mode
 1f2:	6f e4       	ldi	r22, 0x4F	; 79
 1f4:	80 e0       	ldi	r24, 0x00	; 0
 1f6:	0e 94 de 00 	call	0x1bc	; 0x1bc <wl_module_config_register>
    wl_module_CE_hi;     // Listening for pakets
 1fa:	c0 9a       	sbi	0x18, 0	; 24
 1fc:	08 95       	ret

000001fe <wl_module_get_data>:

}

extern uint8_t wl_module_get_data(uint8_t * data) 
// Reads wl_module_PAYLOAD bytes into data array
 {	uart_puts(" z "); 
 1fe:	1f 93       	push	r17
 200:	cf 93       	push	r28
 202:	df 93       	push	r29
 204:	ec 01       	movw	r28, r24
 206:	86 e6       	ldi	r24, 0x66	; 102
 208:	90 e0       	ldi	r25, 0x00	; 0
 20a:	0e 94 88 00 	call	0x110	; 0x110 <uart_puts>
	uint8_t status;
    wl_module_CSN_lo;                               // Pull down chip select
 20e:	c1 98       	cbi	0x18, 1	; 24
    status = spi_fast_shift( R_RX_PAYLOAD );            // Send cmd to read rx payload
 210:	81 e6       	ldi	r24, 0x61	; 97
 212:	0e 94 b8 00 	call	0x170	; 0x170 <spi_fast_shift>
 216:	18 2f       	mov	r17, r24
    spi_transfer_sync(data,data,wl_module_PAYLOAD); // Read payload
 218:	40 e1       	ldi	r20, 0x10	; 16
 21a:	be 01       	movw	r22, r28
 21c:	ce 01       	movw	r24, r28
 21e:	0e 94 a2 00 	call	0x144	; 0x144 <spi_transfer_sync>
    wl_module_CSN_hi;                               // Pull up chip select
 222:	c1 9a       	sbi	0x18, 1	; 24
    wl_module_config_register(STATUS,(1<<RX_DR));   // Reset status register
 224:	60 e4       	ldi	r22, 0x40	; 64
 226:	87 e0       	ldi	r24, 0x07	; 7
 228:	0e 94 de 00 	call	0x1bc	; 0x1bc <wl_module_config_register>
	return status;
}
 22c:	81 2f       	mov	r24, r17
 22e:	df 91       	pop	r29
 230:	cf 91       	pop	r28
 232:	1f 91       	pop	r17
 234:	08 95       	ret

00000236 <__itoa_ncheck>:
 236:	bb 27       	eor	r27, r27
 238:	4a 30       	cpi	r20, 0x0A	; 10
 23a:	31 f4       	brne	.+12     	; 0x248 <__itoa_ncheck+0x12>
 23c:	99 23       	and	r25, r25
 23e:	22 f4       	brpl	.+8      	; 0x248 <__itoa_ncheck+0x12>
 240:	bd e2       	ldi	r27, 0x2D	; 45
 242:	90 95       	com	r25
 244:	81 95       	neg	r24
 246:	9f 4f       	sbci	r25, 0xFF	; 255
 248:	0c 94 27 01 	jmp	0x24e	; 0x24e <__utoa_common>

0000024c <__utoa_ncheck>:
 24c:	bb 27       	eor	r27, r27

0000024e <__utoa_common>:
 24e:	fb 01       	movw	r30, r22
 250:	55 27       	eor	r21, r21
 252:	aa 27       	eor	r26, r26
 254:	88 0f       	add	r24, r24
 256:	99 1f       	adc	r25, r25
 258:	aa 1f       	adc	r26, r26
 25a:	a4 17       	cp	r26, r20
 25c:	10 f0       	brcs	.+4      	; 0x262 <__utoa_common+0x14>
 25e:	a4 1b       	sub	r26, r20
 260:	83 95       	inc	r24
 262:	50 51       	subi	r21, 0x10	; 16
 264:	b9 f7       	brne	.-18     	; 0x254 <__utoa_common+0x6>
 266:	a0 5d       	subi	r26, 0xD0	; 208
 268:	aa 33       	cpi	r26, 0x3A	; 58
 26a:	08 f0       	brcs	.+2      	; 0x26e <__utoa_common+0x20>
 26c:	a9 5d       	subi	r26, 0xD9	; 217
 26e:	a1 93       	st	Z+, r26
 270:	00 97       	sbiw	r24, 0x00	; 0
 272:	79 f7       	brne	.-34     	; 0x252 <__utoa_common+0x4>
 274:	b1 11       	cpse	r27, r1
 276:	b1 93       	st	Z+, r27
 278:	11 92       	st	Z+, r1
 27a:	cb 01       	movw	r24, r22
 27c:	0c 94 40 01 	jmp	0x280	; 0x280 <strrev>

00000280 <strrev>:
 280:	dc 01       	movw	r26, r24
 282:	fc 01       	movw	r30, r24
 284:	67 2f       	mov	r22, r23
 286:	71 91       	ld	r23, Z+
 288:	77 23       	and	r23, r23
 28a:	e1 f7       	brne	.-8      	; 0x284 <strrev+0x4>
 28c:	32 97       	sbiw	r30, 0x02	; 2
 28e:	04 c0       	rjmp	.+8      	; 0x298 <strrev+0x18>
 290:	7c 91       	ld	r23, X
 292:	6d 93       	st	X+, r22
 294:	70 83       	st	Z, r23
 296:	62 91       	ld	r22, -Z
 298:	ae 17       	cp	r26, r30
 29a:	bf 07       	cpc	r27, r31
 29c:	c8 f3       	brcs	.-14     	; 0x290 <strrev+0x10>
 29e:	08 95       	ret

000002a0 <_exit>:
 2a0:	f8 94       	cli

000002a2 <__stop_program>:
 2a2:	ff cf       	rjmp	.-2      	; 0x2a2 <__stop_program>
