xilinx.com
xci
unknown
1.0
blk_mem_gen_0
4096
1
0
0
0
1
100000000
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
1
0
0
0
1
100000000
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0.000
AXI4LITE
READ_WRITE
0
0
0
0
0
OTHER
NONE
8192
32
1
OTHER
NONE
8192
32
1
100000000
0
0.000
0
4
4
1
4
0
1
9
0
1
0
NONE
0
0
0
./
0
0
0
0
0
0
0
0
Estimated Power for IP : 2.7096 mW
kintex7
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
blk_mem_gen_0.mem
blk_mem_gen_0.mif
0
1
3
0
1
16
16
1
1
16
16
0
0
CE
CE
ALL
0
0
0
0
0
0
0
1
1
16
16
WRITE_FIRST
WRITE_FIRST
16
16
kintex7
4
Memory_Slave
AXI4_Full
false
Minimum_Area
false
9
NONE
../../../../coe_32_kHz_Order_15_2000_2200.coe
ALL
blk_mem_gen_0
false
false
false
false
false
false
false
false
false
Always_Enabled
Always_Enabled
Single_Bit_Error_Injection
false
Native
true
no_mem_loaded
Single_Port_ROM
WRITE_FIRST
WRITE_FIRST
0
0
BRAM
0
100
100
0
0
0
0
8kx2
false
false
1
1
16
16
false
true
false
false
0
false
false
CE
CE
SYNC
false
false
false
false
false
false
false
16
16
16
No_ECC
false
false
false
Stand_Alone
kintex7
digilentinc.com:genesys2:part0:1.1
xc7k325t
ffg900
VHDL
VHDL
-2
TRUE
TRUE
IP_Flow
4
TRUE
.
.
2019.2
OUT_OF_CONTEXT