set_clock_groups -asynchronous -group [get_clocks *clk_out1*] -group [get_clocks *clk_out2*] set_property CFGBVS VCCO [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] #### This file is a general .xdc for the Genesys 2 Rev. H #### To use it in a project: #### - uncomment the lines corresponding to used pins #### - rename the used ports (in each line, after get_ports) according to the top level signal names in the project ## Clock Signal set_property -dict {PACKAGE_PIN AD11 IOSTANDARD LVDS} [get_ports sysclk_n] set_property -dict {PACKAGE_PIN AD12 IOSTANDARD LVDS} [get_ports sysclk_p] ## PMOD Header JA set_property -dict {PACKAGE_PIN U28 IOSTANDARD LVCMOS33} [get_ports { DA_LRCK }]; set_property -dict {PACKAGE_PIN U27 IOSTANDARD LVCMOS33} [get_ports { DA_MCLK }]; set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS33} [get_ports { DA_SDIN }]; set_property -dict {PACKAGE_PIN T26 IOSTANDARD LVCMOS33} [get_ports { DA_SCLK }]; set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS33} [get_ports { AD_LRCK }]; set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS33} [get_ports { AD_MCLK }]; set_property -dict {PACKAGE_PIN T21 IOSTANDARD LVCMOS33} [get_ports { AD_SDOUT }]; set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS33} [get_ports { AD_SCLK }]; ## UART set_property -dict { PACKAGE_PIN Y23 IOSTANDARD LVCMOS33 } [get_ports { FT232R_TX }]; #uart_rx_out }]; #IO_L1P_T0_12 Sch=uart_rx_out set_property -dict { PACKAGE_PIN Y20 IOSTANDARD LVCMOS33 } [get_ports { FT232R_RX }]; #uart_tx_in }]; #IO_0_12 Sch=uart_tx_in