library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity AudioInterface is port( sysclk_p : in std_logic; sysclk_n : in std_logic; --**********all PMOD Pins in Entity************ DA_LRCK : OUT STD_LOGIC; DA_MCLK : OUT STD_LOGIC; DA_SDIN : OUT STD_LOGIC; DA_SCLK : OUT STD_LOGIC; AD_LRCK : OUT STD_LOGIC; AD_MCLK : OUT STD_LOGIC; AD_SDOUT : IN STD_LOGIC; AD_SCLK : OUT STD_LOGIC); --************************************************* end AudioInterface; architecture Behavioral of AudioInterface is component i2s_data_interface Port( i2s_MCLK : in std_logic; filtered_data_left : in std_logic_vector(23 downto 0); filtered_data_right : in std_logic_vector(23 downto 0); unfiltered_data_left : out std_logic_vector(23 downto 0); unfiltered_data_right : out std_logic_vector(23 downto 0); new_sample : out std_logic; i2s_SCLK : in std_logic; i2s_DA_SDIN : out std_logic; i2s_AD_SDOUT : in std_logic; i2s_LRCK : in std_logic); end component; component clk_wiz_0 port( -- Clock out ports clk_out1 : out std_logic; clk_out2 : out std_logic; -- Status and control signals reset : in std_logic; locked : out std_logic; -- Clock in ports clk_in1_p : in std_logic; clk_in1_n : in std_logic); end component; component FIRFilter generic( CHANNEL : natural := 0; -- 0: Left, 1: Right NBTAP : natural := 82; DSIZE : natural := 24; COESIZE : natural := 16); port( clk_100_MHz : in std_logic; datain : in std_logic_vector(23 downto 0); firout : out std_logic_vector(23 downto 0); new_sample : in std_logic); end component; ------------------------------------------------------ signal s_reset : std_logic:='0'; signal s_clk_100_MHz : std_logic:='0'; signal s_clk_8_192_MHz_MCLK : std_logic:='0'; signal s_clk_2_048_MHz_SCLK : std_logic:='0'; signal s_clk_32_kHz_LRCK : std_logic:='0'; signal clkdiv : unsigned(7 downto 0):=(others => '0'); ------------------------------------------------------ signal s_filtered_data_left : std_logic_vector(23 downto 0) := (others => '0'); signal s_filtered_data_right : std_logic_vector(23 downto 0) := (others => '0'); ------------------------------------------------------ signal s_unfiltered_data_left : std_logic_vector(23 downto 0) := (others => '0'); signal s_unfiltered_data_right : std_logic_vector(23 downto 0) := (others => '0'); ------------------------------------------------------ signal s_new_sample : std_logic:='0'; signal s_DA_SDIN : std_logic:='0'; signal s_new_sample_sr : std_logic_vector(1 downto 0):="00"; signal s_begin_filter : std_logic := '0'; begin process begin wait until rising_edge(s_clk_8_192_MHz_MCLK); clkdiv <= clkdiv +1; end process; s_clk_2_048_MHz_SCLK <= clkdiv(1); s_clk_32_kHz_LRCK <= clkdiv(7); NEW_SAMPLE_PROC : process begin wait until rising_edge(s_clk_100_MHz); s_new_sample_sr <= s_new_sample_sr(0) & s_new_sample; s_begin_filter <= '0'; if s_new_sample_sr = "01" then s_begin_filter <= '1'; end if; end process; --*************************instantiate PMOD Pins****************************************** DA_LRCK <= s_clk_32_kHz_LRCK; DA_MCLK <= s_clk_8_192_MHz_MCLK; DA_SCLK <= s_clk_2_048_MHz_SCLK; ------------------------------------ AD_LRCK <= s_clk_32_kHz_LRCK; AD_MCLK <= s_clk_8_192_MHz_MCLK; AD_SCLK <= s_clk_2_048_MHz_SCLK; ------------------------------------ DA_SDIN <= s_DA_SDIN; --**************************************************************************************** FIR_Left_Channel : FIRFilter generic map( CHANNEL => 0, NBTAP => 82, DSIZE => 24, COESIZE => 16) port map( clk_100_MHz => s_clk_100_MHz, datain => s_unfiltered_data_left, firout => s_filtered_data_left, new_sample => s_begin_filter); FIR_Right_Channel : FIRFilter generic map( CHANNEL => 1, NBTAP => 82, DSIZE => 24, COESIZE => 16) port map( clk_100_MHz => s_clk_100_MHz, datain => s_unfiltered_data_right, firout => s_filtered_data_right, new_sample => s_begin_filter); clk_wiz : clk_wiz_0 port map( -- Clock out ports clk_out1 => s_clk_100_MHz, clk_out2 => s_clk_8_192_MHz_MCLK, -- Status and control signals reset => '0', locked => open, -- Clock in ports clk_in1_p => sysclk_p, clk_in1_n => sysclk_n); i2s_interface : i2s_data_interface port map( i2s_MCLK => s_clk_8_192_MHz_MCLK, filtered_data_left => s_filtered_data_left, -- std_logic_vector as Input for conversion as serial output (left channel part) filtered_data_right => s_filtered_data_right, -- std_logic_vector as Input for conversion as serial output (right channel part) unfiltered_data_left => s_unfiltered_data_left, -- converted input data unfiltered_data_right => s_unfiltered_data_right, -- converted input data new_sample => s_new_sample, i2s_SCLK => s_clk_2_048_MHz_SCLK, i2s_DA_SDIN => s_DA_SDIN, i2s_AD_SDOUT => AD_SDOUT, i2s_LRCK => s_clk_32_kHz_LRCK); end Behavioral;