Release 9.1.03i par J.33 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. UNI-514965:: Mon Mar 23 10:22:10 2009 par -w -intstyle ise -ol std -t 1 test_top_map.ncd test_top.ncd test_top.pcf Constraints file: test_top.pcf. Loading device for application Rf_Device from file '3s700a.nph' in environment C:\Xilinx. "test_top" is an NCD, version 3.1, device xc3s700a, package fg484, speed -4 Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) Device speed data version: "PRODUCTION 1.34 2007-03-08". Design Summary Report: Number of External IOBs 17 out of 372 4% Number of External Input IOBs 7 Number of External Input IBUFs 7 Number of LOCed External Input IBUFs 7 out of 7 100% Number of External Output IOBs 10 Number of External Output IOBs 10 Number of LOCed External Output IOBs 10 out of 10 100% Number of External Bidir IOBs 0 Number of BUFGMUXs 1 out of 24 4% Number of Slices 48 out of 5888 1% Number of SLICEMs 20 out of 2944 1% Overall effort level (-ol): Standard Placer effort level (-pl): High Placer cost table entry (-t): 1 Router effort level (-rl): Standard Starting initial Timing Analysis. REAL time: 5 secs ERROR:Par:228 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A physical timing constraint summary follows. This summary will show a MINIMUM net delay for the paths. The "Actual" delays listed in this summary are the UNROUTED delays with a 100 ps timing budget for each route, NOT the achieved timing. Any constraint in the summary showing a failure ("*" in the first column) has a constraint that is too tight. These constraints must be relaxed before PAR can continue. Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to identify the problem paths. For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference manual; for more information on TRCE, consult the Xilinx Development System Reference Guide "TRACE" chapter. INFO:Timing:3284 - This timing report was generated using estimated delay information. For accurate numbers, please refer to the post Place and Route timing report. Asterisk (*) preceding a constraint indicates it was not met. This may be due to a setup or hold violation. ------------------------------------------------------------------------------------------------------ Constraint | Check | Worst Case | Best Case | Timing | Timing | | Slack | Achievable | Errors | Score ------------------------------------------------------------------------------------------------------ * OFFSET = OUT 20 ns AFTER COMP "CLK_50M" | MAXDELAY| -12.659ns| 32.659ns| 1| 12659 ------------------------------------------------------------------------------------------------------ OFFSET = IN 10 ns VALID 20 ns BEFORE COMP | SETUP | 8.502ns| 1.498ns| 0| 0 "CLK_50M" | HOLD | N/A| | N/A| 0 ------------------------------------------------------------------------------------------------------ NET "CLK_50M_BUFGP/IBUFG" PERIOD = 20 ns | SETUP | 14.797ns| 5.203ns| 0| 0 HIGH 50% | HOLD | 0.413ns| | 0| 0 ------------------------------------------------------------------------------------------------------ 1 constraint not met. Generating "PAR" statistics. ************************** Generating Clock Report ************************** +---------------------+--------------+------+------+------------+-------------+ | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| +---------------------+--------------+------+------+------------+-------------+ | CLK_50M_BUFGP* | Global| No | 48 | 0.000 | | +---------------------+--------------+------+------+------------+-------------+ * Some of the Clock networks are NOT completely routed * Net Skew is the difference between the minimum and maximum routing only delays for the net. Note this is different from Clock Skew which is reported in TRCE timing report. Clock Skew is the difference between the minimum and maximum path delays which includes logic delays. The Delay Summary Report The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 99 The AVERAGE CONNECTION DELAY for this design is: 0.100 The MAXIMUM PIN DELAY IS: 0.100 The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 0.100 Listing Pin Delays by value: (nsec) d < 1.00 < d < 2.00 < d < 3.00 < d < 4.00 < d < 5.00 d >= 5.00 --------- --------- --------- --------- --------- --------- 371 0 0 0 0 0 Timing Score: 12659 WARNING:Par:62 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design. Review the timing report using Timing Analyzer (In ISE select "Post-Place & Route Static Timing Report"). Go to the failing constraint(s) and select the "Timing Improvement Wizard" link for suggestions to correct each problem. Increase the PAR Effort Level setting to "high" Rerun Map with "-timing" (ISE process "Perform Timing -Driven Packing and Placement" Run Multi-Pass Place and Route in PAR using at least 5 "PAR Iterations" (ISE process "Multi Pass Place & Route"). Use the Xilinx "xplorer" script to try special combinations of options known to produce very good results. See http://www.xilinx.com/ise/implementation/Xplorer.htm for details. Visit the Xilinx technical support web at http://support.xilinx.com and go to either "Troubleshoot->Tech Tips->Timing & Constraints" or " TechXclusives->Timing Closure" for tips and suggestions for meeting timing in your design. Generating Pad Report. 99 signals are not completely routed. WARNING:Par:100 - Design is not completely routed. Total REAL time to PAR completion: 6 secs Total CPU time to PAR completion: 6 secs Peak Memory Usage: 171 MB Placement: Completed - errors found. Routing: Completed - errors found. Timing: Completed - 1 errors found. Number of error messages: 1 Number of warning messages: 3 Number of info messages: 0 Writing design to file test_top.ncd PAR done!