--- Definition --- package MP_PACK is -- Konstantendeklaration constant A_BREITE : integer := 12; -- 12-Bit Adressen constant D_BREITE : integer := 18; -- 16-Bit Daten -- Typendeklaration type OPTYPE is ( SHLA, STAabs, STAind, LDAind, LDAunm, LDAabs, ADDA, SUBA, ORA, ANDA, EORA, JMP, JE, JNE, JGE, JLT ); subtype D_TYPE is std_logic_vector(D_BREITE-1 downto 0); subtype A_TYPE is std_logic_vector(A_BREITE-1 downto 0); end MP_PACK; --- TOP Modul --- entity Controller is Port ( CLK : in STD_LOGIC; RESET : in STD_LOGIC; IO : inout STD_LOGIC_VECTOR (17 downto 0)); end Controller; architecture SoftCore of Controller is -- Componenten component ram is port ( clk : in std_logic; wr : in std_logic; addr : in A_TYPE; data : inout D_TYPE ); end component; COMPONENT CPU PORT( CLK : IN std_logic; RESET : IN std_logic; D : INOUT D_TYPE; A : OUT A_TYPE; READWRITE : OUT std_logic ); END COMPONENT; signal D : D_TYPE; signal D2 : D_TYPE; signal A : A_TYPE; signal A2 : A_TYPE; signal RW : std_logic; for all: CPU use entity WORK.CPU(STRUKTUR); for all: RAM use entity WORK.RAM(ram_arch); begin InstCPU: CPU PORT MAP( CLK => CLK, RESET => RESET, D => D, A => A, READWRITE => RW ); InstRAM: RAM port map( clk => CLK, wr => RW, addr => A2, data => D2 ); A2 <= A; D <= D2; end SoftCore; --- RAM --- use WORK.MP_PACK.ALL; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ram is port ( clk : in std_logic; wr : in std_logic; addr : in A_TYPE; data : inout D_TYPE ); end ram; ----------------------------------------------------------------------------- architecture ram_arch of ram is type ram_t is array ((2**A_BREITE)-1 downto 0) of std_logic_vector(D_BREITE-1 downto 0); signal ram : ram_t; ------------------------------------------------- begin process(clk) begin if(clk'event and clk = '1') then if(wr = '1') then ram(conv_integer(addr)) <= data; else data <= ram(conv_integer(addr)); end if; end if; end process; end ram_arch; -- Fehler -- -- ERROR:Xst:528 - Multi-source in Unit on signal > -- Sources are: -- Output signal of BUFT instance -- Output port doA<0> of instance of inferred macro RAM -- Und so wieter und so fort...